DATASHEET 2MHz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers FN2894 Rev 1. comprise a series of operational amplifiers delivering an unsurpassed combination of specifications for slew rate, bandwidth and settling time. These dielectrically isolated amplifiers are controlled at closed loop gains greater than 3 without external compensation. In addition, these high performance components also provide low offset current and high input impedance. 12V/µs slew rate and 2ns (.2%) settling time of these amplifiers make them ideal components for pulse amplification and data acquisition designs. These devices are valuable components for RF and video circuitry requiring up to 2MHz gain bandwidth and 2MHz power bandwidth. For accurate signal conditioning designs the s superior dynamic specifications are complemented by 1nA offset current, 1M input impedance and offset trim capability. Features High slew rate........................... 12V/µs Fast settling............................... 2ns Full power bandwidth........................ 2MHz Gain bandwidth (A V 3)..................... 2MHz High input impedance...................... 1M Low offset current............................1na Compensation pin for unity gain capability Pb-free PDIP available (RoHS compliant) Applications Data acquisition systems RF amplifiers Video amplifiers Signal generators Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE HA2-22-2 HA2-22-2 - to +12 8 Ld Metal Can T8.C HA7-22-2 HA7-22-2 - to +12 8 Ld CerDIP F8.3A HA2-222-2 HA2-222-2 - to +12 8 Ld Metal Can T8.C HA3-22-Z (Notes 1, 2) HA3-22-Z to +7 8 Ld PDIP E8.3 PKG. DWG. # 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 1% matte tin plate - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-2. 2. Pb-Free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN2894 Rev 1. Page 1 of 12
Pinouts HA-22, HA-22 (8 LD CERDIP, 8 LD PDIP) TOP VIEW BAL 1 8 COMP -IN +IN 2 3 - + 7 6 V+ OUT V- 4 BAL HA-22, HA-222 (8 LD METAL CAN) TOP VIEW COMP 8 BAL 1 7 V+ IN- 2 - + 6 OUT IN+ 3 4 V- BAL FN2894 Rev 1. Page 2 of 12
Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals)............ 4V Differential Input Voltage.............................. 1V Output Current..................................... ma Operating Conditions Temperature Range HA-22/222-2......................... - C to +12 C HA-22-................................ C to +7 C Thermal Information Thermal Resistance (Typical, Notes 3, 4) JA ( C/W) JC ( C/W) Metal Can Package............... 16 8 PDIP Package*.................. 96 N/A CERDIP Package................. 13 Maximum Junction Temperature (Hermetic Packages)..... +17 C Maximum Junction Temperature (Plastic Package)...... +1 C Maximum Storage Temperature Range......... -6 C to +1 C Pb-Free Reflow Profile............................seeTB493 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 3. JA is measured with the component mounted on an evaluation PC board in free air. 4. For JC, the case temp location is taken at the package top center. Electrical Specifications V SUPPLY = ±1V HA-22-2 HA-222-2 HA-22- PARAMETER TEMP ( C) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage 2 4 8 1 1 mv Full 11 14 14 mv Offset Voltage Drift Full 2 2 3 µv/ C Bias Current 2 1 2 12 2 12 2 na Full 4 na Offset Current 2 1 2 2 2 na Full 1 1 na Input Resistance (Note ) 2 1 4 1 4 1 M Common Mode Range Full ±1 ±1 ±1 V TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Notes 6, 9) Common Mode Rejection Ratio (Note 7) 2 1 1 7. 1 7. 1 kv/v Full 7. kv/v Full 8 9 74 9 74 9 db Gain Bandwidth (Notes, 8) 2 1 2 1 2 1 2 MHz Minimum Stable Gain 2 3 3 3 V/V OUTPUT CHARACTERISTICS Output Voltage Swing (Note 6) Full ±1 ±12 ±1 ±12 ±1 ±12 V Output Current (Note 9) 2 ±1 ±2 ±1 ±2 ±1 ±2 ma Full Power Bandwidth (Notes 9, 14) 2 1. 2. 1.2 2. 1.2 2. MHz FN2894 Rev 1. Page 3 of 12
Electrical Specifications V SUPPLY = ±1V (Continued) HA-22-2 HA-222-2 HA-22- PARAMETER TEMP ( C) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS TRANSIENT RESPONSE (A V = +3) Rise Time (Notes 6, 1, 11, 13) 2 2 2 2 ns Overshoot (Notes 6, 1, 11, 13) 2 2 4 2 2 % Slew Rate (Notes 6, 1, 17, 1) 2 ±1 ±12 ±8 ±12 ±8 ±12 V/µs Settling Time (Notes 6, 1, 17, 1) 2.2.2.2 µs POWER SUPPLY CHARACTERISTICS Supply Current 2 4 6 4 6 4 6 ma Power Supply Rejection Ratio (Note 12) Full 8 9 74 9 74 9 db. This parameter value is based on design calculations. 6. R L = 2kΩ 7. V CM = ±1V. 8. A V > 1. 9. V O = ±1V. 1. C L = pf. 11. V O = ±2mV. 12. V = ±V. 13. See Transient Response Test Circuits and Waveforms. Slew Rate 14. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = ----------------------------. 2 V 1. V OUT = ±V. PEAK 16. Parameters with MIN and/or MAX limits are 1% tested at +2 C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 17. See Slew Rate and Settling Time Test Circuits and Waveforms. FN2894 Rev 1. Page 4 of 12
Test Circuits and Waveforms +1.67V INPUT -1.67V +V 7% OUTPUT V 2% ERROR BAND -V SLEW ±1mV FROM t RATE FINAL VALUE = V/ t SETTLING TIME FIGURE 1. SLEW RATE AND SETTLING TIME INPUT V ±2mV 9% OUTPUT 1% V ±67mV OVERSHOOT RISE TIME NOTE: Measured on both positive and negative transitions from V to +2mV and V to -2mV at the output. FIGURE 2. TRANSIENT RESPONSE V+ 1F INPUT 667.2Ω 2 3 7.1µF 6 + - 4 1µF OUTPUT 1pF IN + - pf 1333Ω 667Ω pf OUT D G 2N4416 S 2kΩ 1667Ω CR 1 CR 2 V-.1µF 21Ω 4999.9Ω SETTLING TIME TEST POINT FIGURE 3. SLEW RATE AND TRANSIENT RESPONSE 18. A V = -3. 19. Feedback and summing resistor ratios should be.1% matched. 2. Clipping diodes CR 1 and CR 2 are optional. HP82-281 recommended. FIGURE 4. SETTLING TIME TEST CIRCUIT V+ 2kΩ IN BAL. COMP OUT V- C C NOTE: Tested offset adjustment range is V OS + 1mV minimum referred to output. Typical ranges are ±2mV with R T = 2k FIGURE. SUGGESTED V OS ADJUSTMENT AND COMPENSATION HOOK-UP FN2894 Rev 1. Page of 12
Schematic Diagram PIN 1 OFFSET- BAL 1 BAL 2 OFFSET+ COMP V+ Q 3 2 R 2AA 2 R 2BB R 21 R 1 Q 29 R 13 R 11 44 1.8k R 2A 44 1.8k R 2B R 12 Q 28 Q 27 R 16 Q 16 Q 3A Q 4A Q 3B Q 4B C 1 1pF Q 23 Q 8 Q 1 R 9 Q 12A +INPUT R 1 Q 1A Q 2A Q 2B Q 1B Q 11B D 138 Q 12B R 17 OUTPUT Q 17 R 1A R 1B Q 7 R 18 3 Q 24 D 13A Q 18 Q 19 Q 31 Q Q 2 21A Q A Q 26 Q 21B Q 6 Q B Q 1 Q 2 R 6A Q22 R 6B R 3A R 3B R 19 Q 9 D 14 R 1 Q 11A V- -INPUT Typical Application Inverting Unity Gain Circuit Figure 6 shows a Compensation Circuit for an inverting unity gain amplifier. The circuit was tested for functionality with supply voltages from ±4V to ±1V, and the performance as tested was: Slew Rate 12V/µs; Bandwidth 1MHz; and Settling Time (.1%) ns. Figure 7 illustrates the amplifier s frequency response, and it is important to note that capacitance at pin 8 must be minimized for maximum bandwidth. 1k GAIN (db) 1 1 - -1-1 PHASE GAIN -4-9 -13-18 PHASE SHIFT ( ) IN 1k 2k pf k + - HA-22 OUT 1k 1k 1M 1M FIGURE 7. FREQUENCY RESPONSE FOR INVERTING UNITY GAIN CIRCUIT FIGURE 6. INVERTING UNITY GAIN CIRCUIT FN2894 Rev 1. Page 6 of 12
Typical Performance Curves V S = 1V, T A = +2 C, Unless Otherwise Specified OFFSET VOLTAGE (mv) 6 4 3 2 1-1 -2-3 -6-4 -2 2 4 6 8 1 12 BIAS CURRENT (na) -4 - -6-7 -8-9 -1-11 -12-13 -14-1 -16-6 -4-2 2 4 6 8 1 12 TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) FIGURE 9. BIAS CURRENT vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) OFFSET BIAS CURRENT (na) 4 3 2 1-1 -2-3 -6-4 -2 2 4 6 8 1 12 TEMPERATURE ( C) A VOL (kv/ V) 22 21 2 19 18 17 16 1 14 13 12 11 1 9 8 7 6-6 -4-2 2 4 6 8 1 12 TEMPERATURE ( C) FIGURE 1. OFFSET CURRENT vs TEMPERATURE ( TYPICAL UNITS FROM 3 LOTS) FIGURE 11. OPEN LOOP GAIN vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) OUTPUT CURRENT (±ma) 4 3 2 1-1 -2-3 -4 4 6 8 1 12 14 SUPPLY VOLTAGE ( V) OUTPUT VOLTAGE SWING (±V) 14 12 R L = 2k 1 8 6 4 2-2 -4-6 -8-1 -12 4 6 8 1 12 14 SUPPLY VOLTAGE ( V) FIGURE 12. OUTPUT CURRENT vs SUPPLY VOLTAGE FIGURE 13. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE FN2894 Rev 1. Page 7 of 12
Typical Performance Curves V S = 1V, T A = +2 C, Unless Otherwise Specified (Continued) SUPPLY CURRENT (ma).4.2. 4.8 4.6 4.4 4.2 4. 3.8 3.6 3.4 3.2 3. 2.8 2.6 2.4 +12 C +2 C - C 4 6 8 1 12 14 SUPPLY VOLTAGE (±V) FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE GAIN (db) 1 8 6 4 2 1 GAIN AT A V = 1 PHASE AT A V = 1 OPEN LOOP PHASE 1k OPEN LOOP GAIN -18 1k 1k 1M 1M 1M FREQUENCY (Hz) FIGURE 1. FREQUENCY RESPONSE -4-9 -13 PHASE ANGLE (DEGREES) 1 1 1 8 6 4 2 1pF 3pF pf 1pF 3pF pf INPUT NOISE VOLTAGE (nv/ Hz) 1 1 INPUT NOISE CURRENT INPUT NOISE VOLTAGE 1 1. INPUT NOISE CURRENT (pa/ Hz) -2 1 1k 1k 1k 1M 1M 1M FREQUENCY (Hz) FIGURE 16. OPEN LOOP FREQUENCY RESPONSE FOR VARIOUS VALUES OF CAPACITORS FROM COMP PIN TO GROUND 1.1 1 1 1 1k 1k 1k FREQUENCY (Hz) FIGURE 17. INPUT NOISE CHARACTERISTICS OUTPUT VOLTAGE SWING (V P-P ) 3 3 2 2 1 1 V SUPPLY = 2V V SUPPLY = 1V V SUPPLY = 1V NORMALIZED TO ±1V DATA 1.2 1.1 1..9.8.7.6. R L = 2k C L = pf BANDWIDTH NEGATIVE SLEW RATE POSITIVE SLEW RATE 1k 1k 1M 1M FREQUENCY (Hz) FIGURE 18. OUTPUT VOLTAGE SWING vs FREQUENCY.4 7 9 11 13 1 17 19 SUPPLY VOLTAGE ( V) FIGURE 19. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE 2 FN2894 Rev 1. Page 8 of 12
Die Characteristics SUBSTRATE POTENTIAL: Unbiased TRANSISTOR COUNT: 4 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout COMP V+ OUT BAL BAL -IN +IN V- FN2894 Rev 1. Page 9 of 12
Metal Can Packages (Can) ØD ØD1 F Q A REFERENCE PLANE Øb1 A A L L2 L1 Øb1 Øb ØD2 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and. from the reference plane. Diameter is uncontrolled in L1 and beyond. from the reference plane. 2. Measured from maximum diameter of the product. 3. a is the basic spacing from the centerline of the tab to terminal 1 and b is the basic spacing of each lead or lead position (N -1 places) from a, looking at the bottom of the package. 4. N is the maximum number of terminal positions.. Dimensioning and tolerancing per ANSI Y14.M - 1982. 6. Controlling dimension: INCH. Øe BASE AND SEATING PLANE BASE METAL SECTION A-A Øb2 2 e1 LEAD FINISH 1 N k k1 C L T8.C MIL-STD-183 MACY1-X8 (A1) 8 LEAD METAL CAN PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.16.18 4.19 4.7 - Øb.16.19.41.48 1 Øb1.16.21.41.3 1 Øb2.16.24.41.61 - ØD.33.37 8.1 9.4 - ØD1.3.33 7.7 8.1 - ØD2.11.16 2.79 4.6 - e.2 BSC.8 BSC - e1.1 BSC 2.4 BSC - F -.4-1.2 - k.27.34.69.86 - k1.27.4.69 1.14 2 L..7 12.7 19. 1 L1 -. - 1.27 1 L2.2-6.3-1 Q.1.4.2 1.14 - a 4 BSC 4 BSC 3 b 4 BSC 4 BSC 3 N 8 8 4 Rev. /18/94 FN2894 Rev 1. Page 1 of 12
Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.M - 1982. 1. Controlling dimension: INCH E L M c1 ea/2 S D S aaa M C A - B LEAD FINISH BASE METAL b1 M (b) SECTION A-A S ea c D S (c) F8.3A MIL-STD-183 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -.2 -.8 - b.14.26.36.66 2 b1.14.23.36.8 3 b2.4.6 1.14 1.6 - b3.23.4.8 1.14 4 c.8.18.2.46 2 c1.8.1.2.38 3 D -.4-1.29 E.22.31.9 7.87 e.1 BSC 2.4 BSC - ea.3 BSC 7.62 BSC - ea/2.1 BSC 3.81 BSC - L.12.2 3.18.8 - Q.1.6.38 1.2 6 S1. -.13-7 9 1 9 1 - aaa -.1 -.38 - bbb -.3 -.76 - ccc -.1 -.2 - M -.1 -.38 2, 3 N 8 8 8 Rev. 4/94 FN2894 Rev 1. Page 11 of 12
Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 N 1 2 3 N/2 B D e D1 E1 A 1.1 (.2) M C A A2 L B S -B- -C- -A- 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 9. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 inch (.2mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed.1 inch (.2mm). 9. N is the maximum number of terminal positions. 1. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of.3 -.4 inch (.76-1.14mm). A e C E C L e A C e B E8.3 (JEDEC MS-1-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A -.21 -.33 4 A1.1 -.39-4 A2.11.19 2.93 4.9 - B.14.22.36.8 - B1.4.7 1.1 1.77 8, 1 C.8.14.24.3 - D.3.4 9.1 1.16 D1. -.13 - E.3.32 7.62 8.2 6 E1.24.28 6.1 7.11 e.1 BSC 2.4 BSC - e A.3 BSC 7.62 BSC 6 e B -.43-1.92 7 L.11.1 2.93 3.81 4 N 8 8 9 Rev. 12/93 Copyright Intersil Americas LLC 24-214. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2894 Rev 1. Page 12 of 12