NTHDP Power MOSFET. V,. A Dual PChannel ChipFET Features Offers an Ultra Low R DS(on) Solution in the ChipFET Package Miniature ChipFET Package % Smaller Footprint than TSOP making it an Ideal Device for Applications where Board Space is at a Premium Low Profile (<. mm) Allows it to Fit Easily into Extremely Thin Environments such as Portable Electronics Designed to Provide Low R DS(on) at Gate Voltage as Low as. V, the Operating Voltage used in many Logic ICs in Portable Electronics Simplifies Circuit Design since Additional Boost Circuits for Gate Voltages are not Required Operated at Standard Logic Level Gate Drive, Facilitating Future Migration to Lower Levels using the same Basic Topology PbFree Package is Available Applications Optimized for Battery and Load Management Applications in Portable Equipment such as MP Players, Cell Phones, Digital Cameras, Personal Digital Assistant and other Portable Applications Charge Control in Battery Chargers Buck and Boost Converters MAXIMUM RATINGS (T J = C unless otherwise noted) Rating Symbol Value Unit DraintoSource Voltage V DSS. V GatetoSource Voltage Continuous V GS. V Drain Current Continuous I D. A seconds I D. Total Power Dissipation Continuous @ T A = C ( sec) @ T A = C Continuous @ C ( sec) @ C Operating Junction and Storage Temperature Range Continuous Source Current (Diode Conduction) Thermal Resistance (Note ) JunctiontoAmbient, sec JunctiontoAmbient, Continuous Maximum Lead Temperature for Soldering Purposes, / from case for seconds P D.... T J, T stg to + W C Is. A R JA R JA C/W T L C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Surface Mounted on FR Board using in sq pad size (Cu area =.7 in sq [ oz] including traces). G V (BR)DSS. V S D PChannel MOSFET PIN CONNECTIONS D D D D 7 R DS(on) TYP m @. V m @. V m @. V S G S G G D PChannel MOSFET ORDERING INFORMATION Device Package Shipping NTHDPT ChipFET /Tape & Reel NTHDPTG S I D MAX. A ChipFET CASE A STYLE MARKING DIAGRAM For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. ChipFET (PbFree) D M D = Specific Device Code M = Month Code = PbFree Package 7 /Tape & Reel Semiconductor Components Industries, LLC, November, Rev. Publication Order Number: NTHDP/D
NTHDP ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note ) Temperature Coefficient (Positive) V (Br)DSS V GS = V, I D = A. V GateBody Leakage Current Zero I GSS V DS = V, V GS =. V na Zero Gate Voltage Drain Current I DSS V DS =. V, V GS = V V DS =. V, V GS = V, T J = C.. A ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(th) V DS = V GS, I D = A.. V Static DraintoSource OnResistance R DS(on) V GS =. V, I D =. A V GS =. V, I D =.7 A V GS =. V, I D =. A Forward Transconductance g FS V DS =. V, I D =. A. S Diode Forward Voltage V SD I S =. A, V GS = V.. V DYNAMIC CHARACTERISTICS Input Capacitance C iss V DS =. V 7 pf Output Capacitance C oss V GS = V Transfer Capacitance C rss f =. MHz SWITCHING CHARACTERISTICS (Note TurnOn Delay Time t d(on) V DD =. V. ns Rise Time t r V GS =. V TurnOff Delay Time t d(off) I D =. A Fall Time t f R G =. Gate Charge Q g V GS =. V. nc Q gs I D =. A. Q gd V DS =. V. SourceDrain Reverse Recovery Time t rr I F =.9 A, di/dt = na. Pulse Test: Pulse Width = s, Duty Cycle = %.. Switching characteristics are independent of operating junction temperatures. m
NTHDP TYPICAL ELECTRICAL CHARACTERISTICS. thru V T J = C I D, Drain Current (A) V. V. V. V I D, Drain Current (A) C T j = C C V DS, DraintoSource Voltage (V) Figure. OnRegion Characteristics..... V GS, GatetoSource Voltage (V) Figure. Transfer Characteristics. r DS(on), OnResistance ( Ω )..... V GS =. V V GS =. V. V GS =. V 7 I D, Drain Current (A) Figure. OnResistance vs. Drain Current and Gate Voltage r DS(on), OnResistance (Ω ) (Normalized)....9 V GS =. V. 7 T J, Junction Temperature ( C) Figure. OnResistance Variation vs. Temperature IDSS, Leakage (na) V GS = V T J = C T j = C C, Capacitance (pf) 9 C iss C rss T J = C C iss C oss C rss V DS, DraintoSource Voltage (V) Figure. DraintoSource Leakage Current vs. Voltage V DS, DraintoSource Voltage (V) Figure. Capacitance Variation
V GS, GatetoSource Voltage (V) Q Q T Q V DS 7 Q g, Total Gate Charge (nc) NTHDP TYPICAL ELECTRICAL CHARACTERISTICS V GS T J = C I D =. A Figure 7. GatetoSource and DraintoSource Voltage vs. Total Charge V DS, DraintoSource Voltage (V) t, Time (ns) V DD = V I D = A V GS =. V t d(off) R G, Gate Resistance (Ohms) t d(on) Figure. Resistive Switching Time Variation vs. Gate Resistance t f t r I SȘource Current (A) V GS = V T J = C Power (W)....7..9. V SD, SourcetoDrain Voltage (V) Figure 9. Diode Forward Voltage vs. Current Time (sec) Figure. Single Pulse Power
NTHDP TYPICAL ELECTRICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance Duty Cycle =. Notes:. P DM t t... t. Duty Cycle, D = t.. Per Unit Base = R JA = 9 C/W. T JM T A = P DM Z (t) JA Single Pulse. Surface Mounted. Square Wave Pulse Duration (sec) Figure. Normalized Thermal Transient Impedance, JunctiontoAmbient Normalized Effective Transient Thermal Impedance. Duty Cycle =..... Single Pulse. Square Wave Pulse Duration (sec) Figure. Normalized Thermal Transient Impedance, JunctiontoFoot
NTHDP PACKAGE DIMENSIONS ChipFET CASE A ISSUE G H E e D 7 e b E A L c. (.) 7 STYLE : PIN. SOURCE. GATE. SOURCE. GATE. DRAIN. DRAIN 7. DRAIN. DRAIN NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER.. MOLD GATE BURRS SHALL NOT EXCEED. MM PER SIDE.. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED. MM.. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A....9.. b...... c...... D.9..... E...7...7 e. BSC. BSC e. BSC. BSC L......7 HE..9..7.7.79 NOM NOM.. SOLDERING FOOTPRINT*...7......9..7.7...7. SCALE : mm inches.7... Basic Style *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D... SCALE : mm inches ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Phoenix, Arizona USA Phone: 977 or Toll Free USA/Canada Fax: 9779 or 7 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguroku, Tokyo, Japan Phone: 77 ON Semiconductor Website: Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTHDP/D