FSER: Fas nalysis of Sof Error Suscepibiliy for Cell-ased Designs in Zhang, Wei-Shen Wang and Michael Orshansky Deparmen of Elecrical and Compuer Engineering, Universiy of Texas bsrac This paper is concerned wih saically analyzing he suscepibiliy of arbirary combinaional circuis o single even upses ha are becoming a significan concern for reliabiliy of commercial elecronics. For he firs ime, a fas and accurae mehodology FSER based on saic, vecor-less analysis of error raes due o single even upses in general combinaional circuis is proposed. ccurae models are based on ST-like pre-characerizaion mehods, and logical masking is compued via binary decision diagrams wih circui pariioning. Experimenal resuls indicae ha FSER achieves good accuracy compared o he SPICE-based simulaion mehod. The average error across he benchmark circuis is 2% a over 9,X speed-up. The accuracy can be furher improved by more accurae cell library characerizaion. The run-ime for ISCS 85 benchmark circuis ranges from o 2 minues. The esimaed bi error rae (ER) for he ISCS 85 benchmark circuis implemened in he nm CMOS echnology is abou -5 FIT.. Inroducion Reliabiliy of commercial elecronics wih respec o he single even upses (SEU) caused by exrinsic radiaion is becoming a significan concern. Hisorically, he mos significan impac of SEU was on memory unis (laches, flip-flops, regisers, and arrays). However, as he ransisor feaure size scales down, he error rae due o single even upses in he combinaional logic becomes subsanial. I is prediced ha by 2, he sof error rae (SER) due o combinaional logic may be comparable o ha of he memory unis []. ecause of he increasing error raes in combinaional circuiry, new ools and analysis mehodologies are needed o ensure circui reliabiliy. Sysem designers, micro-archiecs, and circui designers need accurae predicion of error raes in he designed componens. Having his capaciy is a prerequisie for choosing he proper hardening sraegy for he design. sof error may occur when a high-energy paricle, ypically, an alpha paricle, or a neuron, his he diffusion regions of an MOS ransisor and produces charge ha leads o a fauly ransiion. The pulse will cause an error only if i successfully propagaes o he laching elemen and is lached a he clock arrival (sampling) ime. There are several mechanisms ha reduce he overall likelihood of he pulse producing an erroneous value a he memory unis, making he acual SER subsanially lower han he raw paricle srike rae. In he lieraure [-6], hese mechanisms are referred o as elecrical masking, logic masking, and laching-window masking. In his paper, we propose an efficien and accurae approach for SER analysis of cell-based designs. The efficiency is achieved by resoring o symbolic represenaion of he error pulses using binary decision diagrams (DD). The accuracy is guaraneed by relying on he precise descripion of he non-linear gae ransfer characerisics using he SPICEbased pre-characerizaion of he cells in he library. In addiion o he elecrical properies of he cells, he logic srucure of he circui also has a significan impac on he SER. Failing o accoun for logic masking may overesimae SER by order of magniude (25X for a reesrucured circui wih logic deph 7), as illusraed in Figure. I is eviden ha as he logic deph increases, logic masking plays a more imporan role. ccuraely ye efficienly accouning for he reducion of error rae likelihood due o hese masking mechanisms is he focus of his work. Prior work in his area has concenraed on modeling and describing he paricle ineracions a he very low nuclear level [7], performing device-level simulaions o predic he elecrical response of individual ransisors o a paricle srike [8], and performing circui-simulaion of a small se of gaes o model he propagaion of pulses []. Several auhors Sof Error Raes (a.u.).6.5.4.3.2. Wih Logic Masking Wihou Logic Masking 2 3 4 5 6 7 Logic Deph Figure. Sof error analysis ignoring logic masking can overesimae sof error raes by up o 25X.
have addressed he problem of SER analysis for general combinaional logic [2-4]. ccuraely esimaing he SER due o paricle srikes on combinaional logic gaes represens a significan compuaional challenge. The primary reason is ha SER de-raings due o elecrical, logic, and laching-window masking are all inpu vecor dependen. Exising echniques approach his problem by explicily enumeraing all inpu vecors, or a se of randomly picked inpu vecors [2-4]. However, he size of he inpu vecor space is exponenial in he number of primary inpus, and for circuis wih a large number of primary inpus hese echniques usually ake hours, or even days, o achieve reasonable accuracy [4]. The res of he paper is organized as follows. Secion 2 describes he cell characerizaion procedure. In Secions 3, 4 and 5, we discuss he saic analysis of SER. Secion 6 presens he experimenal resuls, and we draw conclusions in Secion 7. 2. Cell Library Characerizaion The proposed saic SER analysis mehodology FSER is argeed owards he use wih he cell-based design mehodology. ccurae library characerizaion is hus a key consideraion. The wo essenial characerizaion seps are pulse generaion and pulse aenuaion (propagaion). high-energy paricle sriking a node deposis charge which leads o a ime-varying volage pulse of a cerain magniude and shape. The characerisics of he pulse are dependen on he specific ransisor nework of each gae. Thus, he goal of he library characerizaion is o predic for every library gae he waveforms produced a he cell oupu for paricle srikes a each vulnerable region. The curren flow creaed by he charge deposied ino he node is modeled as a single exponenial for cosmic-ray relaed sof errors [][4] (alernaive models for alpha-paricle relaed sof errors are also in exisence [7-9]): 2q T Iq (,) = e s () πts Ts where q is he colleced charge and T s is he echnologydependen charge-collecion ime consan. Colleced charge q depends on he paricle energy, and follows an exponenial disribuion [][4]. Figure 2 shows he SPICE simulaion seup for characerizaion of pulse generaion, where every vulnerable node is aken ino accoun. The simulaions are performed for a range of charge values (q) and load capaciances (C load ). The volage pulses produced a he cell oupu by a specific charge deposied on an inra-cell node srongly depends on he biasing condiion deermined by he inpu vecor. In he example circui of Figure 2, boh n and are sensiive if he inpu vecor is (he pulse generaed a is slighly aenuaed by he ransisor above i), while only n is sensiive if he inpu vecor is or. When he inpu vecor is, he pull-up nework has he smalles resisance, resuling in he smalles falling pulse generaed. Exising ools [-6] eiher ignore he effecs of biasing condiions, or assume he wors case biasing condiions for every gae in he circui. Experimens show a difference of.5x - 4X beween he SPICE simulaion resul and he analysis performed under he wors-case assumpions. Clearly, accurae sof error analysis ool needs o consider differen biasing condiions of he gaes. The volage pulse produced a he cell oupu is approximaed by a rapezoidal waveform, and are capured by wo parameers, pulse widh (pw) measured a.5v DD and maximum volage value (V max ). The rise and fall imes of he rapezoidal waveform are chosen o be ypical values. fer a ransien fauly pulse is generaed, i propagaes oward he primary oupus of he circui. In he course of is propagaion, he pulse s elecrical properies, such as widh and magniude, evolve as a resul of he low-pass characerisics of he gaes i propagaes hrough. Shor pulses end o be aenuaed, while long pulses end o mainain heir original widh and magniude afer passing hrough a combinaional logic gae. Figure 3 shows he SPICE simulaion seup for characerizaion of his dynamic ransfer funcion, where pw and V max of he oupu pulse is found as a funcion of he inpu pulse. While differen inpupin o oupu pahs may be characerized by somewha differen ransfer characerisics, his is a secondary effec, which we have for now ignored. Pulses may re-converge and overlap a a gae in a circui if muliple pahs exis beween he paricle-sriking poin (faul-sie) and he gae. The ineracion of wo pulses arriving simulaneously can be modeled. Currenly, characerizaion capures only he firs-order effec of pulseoverlapping wih he oupu produced by simple superposiion, followed by low-pass filering by he gae s dynamic ransfer funcion. The error of esimaion for circui SER due o his approximaion appears o be minor compared wih SPICE simulaion for he benchmark circuis we have esed. Oupu (V).2.6 V max pw n I() n,, n, 2 Time (ps) Oupu (V) q=7.5fc, C load =ff Inpus Node n n n C load 27 64 68 66 T clk pw (ps) V max (V) Figure 2. Pulse generaion is characerized by circui simulaion wih SPICE. The able shows he pulse produced a he oupu of NND gae...8.7.5
Volage (V).2.6 Inpu (V) Volage (V).2 Oupu (V) C load Oupu Inpu.6 Inpu Oupu 5 5 Time (ps) Time (ps) Figure 3. Pulse propagaion is characerized by circui simulaion wih SPICE. The curves show he low-pass characerisic of NND gae. 3. Saic nalysis of Faul Evens Propagaion FSER is a saic SER analysis mehodology in ha i relies on he implici enumeraion of he inpu vecor space. The algorihm formally encodes and propagaes he error pulses using binary decision diagrams. inary decision diagrams are a powerful daa srucure proposed by ryan [9] for efficien represenaion and manipulaion of oolean funcions. y propagaing he faul-encoding funcion o he primary oupus he algorihm can accuraely predic oupu error probabiliies. The error propagaes only if he pah from a faul-sie o he oupu is sensiizable under he specific assignmen of side inpus o he gaes. The proposed DD-based symbolic error manipulaion algorihm succeeds in effecively capuring such logical masking [3][4]. However, he formaion and propagaion of he pulses symbolically is inrinsically linked in he algorihm wih he accurae characerizaion of cell elecrical properies, conained in he library. This guaranees accurae modeling of elecrical masking [3]. The DD describing he oolean funcion a a given node in an error-free environmen is ermed saic DD. I is consruced using he classic rules of [9]. paricle srike a a node creaes a ransien pulse ha can be represened by modifying he saic DD. Such a daa srucure is referred o as even DD. In he even DD, he erminal verices encode boh he error pulses and he original saic logic values. The even DD encoding will conain he arrival ime (T), he maximum volage (V max ), and he widh of he pulse (pw). Figure 4 shows faul-encoding wih even DD for biasing condiion. If he pins of he gaes are no primary inpus, he DD describing he oolean funcion of he biasing condiion is found firs, which is hen modified o conain a pulse a one of is erminal verex o become an even DD. Consrucing he oupu even DD for an operaion on wo inpu even DDs is a recursive process similar o ha of consrucing he saic DD, which uilizes he sandard DD operaions [9]. The operaions are differen only in how he erminal verices are processed. Specifically, when T clk he erminal verex of one operand is reached, we check if he sae of he oupu can be deermined. If i can, a erminal verex for he oupu even DD is generaed. Oherwise, a non-erminal verex for he oupu is generaed, and he even DD of he oher operand is searched one level deeper. Deermining he sae of he oupu is hrough logic operaion and able look-up from he library. Logic operaion is performed, for example, if one operand has a conrolling value and has no pulse, in which case, he oupu value is deermined regardless of he sae of anoher operand (logic masking). Table lookup is performed when he analog characerisics of he oupu pulse is o be deermined (elecrical masking). s noed in he previous secion, differen biasing condiions may resul in very disinc oupu pulse, sensiive area and hence laching error probabiliy due o paricle srikes a a given gae. In order o achieve near SPICE-level accuracy, his dependence needs o be aken ino accoun during he analysis, which requires enumeraing all gae biasing condiions and all inra-gae nodes. This clearly increases he compuaional burden on he algorihm since for each biasing condiion and each inra-gae node an even DD is now generaed a he faul sie and propagaed o he laches. We have found ha his is crucial for accuracy improvemen and ha he penaly is affordable in mos cases. Indeed, assuming ha he average cell fan-in is k, he increase in complexiy due o his enumeraion is O(k2 k ). Since k is ypically beween and 3, he cos is manageable. Propagaing he faul evens saically is equivalen o consrucing he even DDs for he circui nodes in he fanou cone of he faul-sie where he paricle-srike occurs. The even DD of a circui node is simply is saic DD if i is ouside he fan-ou-cone of he faul sie, since no errorpulses will occur a he node. To illusrae fully he working of he algorihm, consider a small circui example of Figure 5. To simplify he discussion, he pulse magniude is ignored and only he pulse widh is aken ino accoun. Given he colleced charge, an even DD is generaed for each biasing condiion and inra-gae node of he faul sie (node M) is consruced. Due o elecrical masking, he pulse widh changes along he propagaion. The error-pulse is logicallymasked when =. The even DD a node X is he same as is saic DD because he pulse a node X is oo small due o re-convergence o reach he gae hreshold volage. 4. lgorihm Flow and Laching Probabiliy Compuaion Ulimaely, he saic analysis of FSER is based on compuing he probabiliy of an error a he lach due o he oaliy of pulses propagaing owards primary oupus. Firs, i is assumed ha a paricle can srike every node (diffusion region) in he circui wih he probabiliy given by he raio of he node area o oal area. Second, he primary inpus remain sable. The validiy of his assumpion for SER analysis was demonsraed in [2]. Third, he equilibrium probabiliies of he primary inpus are known
Saic DD before srike X V max Even DD afer srike Figure 4. Faul-encoding wih even DD for he biasing condiion. The srengh of he pulse depends on he biasing condiion and he srike locaion wihin he gae. M 4 N 2 2 5 N 25 2 X M 4 X Figure 5. Pulse propagaion in a simple circui. Numbers inside he gaes are heir propagaion delays. Terminals of even DDs conain pulse propagaion delays and duraions. Pulses encoded wih even DDs of N and M cancel each oher, resuling in no pulse a X. and independen of each oher. This las assumpion has been successfully applied for power esimaion and circui reliabiliy assessmen []. Sof error esimaion for circuis wih srongly correlaed primary inpus will be our fuure work. The core of he algorihm is o find he condiional laching error probabiliy P(q, bc,i, j, k), given he colleced charge q, biasing condiion bc of he vicim gae (faul sie), inragae node j of gae i, and lach k. Calculaing P(q, bc,i, j, k) is discussed in he nex paragraph. The conribuion o he bi error rae (ER) of lach k by gae i is, ER(, i k) = P( q, bc, i, j, k)( R ( q, i, j) Δq) (2) j bc q where R(,, q i j) Δq is he srike rae for colleced charge in he range of q andq +Δ q, which is proporional o he area of node j of gae i. We use he average ER of all oupu laches by paricle srikes on all gaes as a meri of a circui s sof error suscepibiliy. However, oher crieria, such as he larges ER of he laches, can be used as well, depending on he applicaion. Propagaing an even DD o he primary oupu gives us a reliable measure of he occurrence probabiliies and srenghs of he pulses ha will appear a he lach inpus. However, he laching error probabiliy is linked o anoher masking mechanism, known as laching window masking. Laching window masking occurs due o he emporal randomness of he paricle srike ime [-4], and he realizaion ha he pulse arrival ime a he lach has o be wihin he laching window for he error o occur. ssuming a uniform srike-ime probabiliy, he acual laching probabiliy for a pulse is: pw w PL = (3) Tclk where PL is he laching probabiliy, pw is he widh of he fauly pulse presen a he inpu of he lach, w is lachingwindow size of he lach, and T clk is he clock period. Given an even described by he se of parameers (q, bc,i, j, k), he even DD a he primary oupu k is consruced firs (Figure 6). Wih he assumpion ha he primary inpus are independen of each oher, each edge of he even DD is assigned a probabiliy, based on he primary inpu he edge corresponds o. y recursively raversing he even DD, he probabiliy for an even conained in a erminal v o occur, pv () can be calculaed []. The condiional laching error probabiliy P(q, bc,i, j, k), is hen Pqbci (,,,, jk) = pvplv () () (4) where PL() v is he laching error probabiliy of he pulse conained in erminal v of he even DD, deermined by (3). 5. Circui Pariioning for Speed-Up I is well known ha he wors-case complexiy of he DD encodings of logic funcions is exponenial in he number of variables [9]. To make manipulaion of DDs efficien, a pariioning heurisic is adoped. This is a common pracice in CD echniques ha use DDs [4][5]. The use of pariioning allows a significan speed-up wihou a noiceable loss of predicion accuracy. The circui is pariioned ino smaller domains as shown in Figure 7. Some nodes are designaed o be pseudo primary inpus, and serve as he boundary beween he pariions. Signal correlaions are only considered wihin he domains. To esimae he laching error probabiliy due o a pariclesrike on a paricular gae, an even DD is generaed a he faul sie and propagaed o he boundary nodes, where he pulse occurrence probabiliies are esimaed by raversing he even DDs. Nex, hese pulses are reaed as being generaed a he boundary nodes and assumed o be independen of each oher. In principle, hese secondary pulses can be independenly propagaed furher o he laches. The laching error probabiliy due o paricle srike a he faul sie is approximaed by he sum of he laching probabiliies of he secondary pulses weighed by heir respecive occurrence probabiliies. In pracice, if we process he faul sies backward saring from he gaes closes o he laches, he laching probabiliies of he secondary pulses can be direcly esimaed from he laching error probabiliies due o paricle-srike a he boundary nodes, wihou furher propagaion of he secondary pulses. v
Generae saic DD for every circui node; ER ; for all combinaions of (q, bc, i, j, k). Rerieve he generaed pulse shape for (q, bc, i, j, k), and generae an even DD a he faul sie i. 2. Propagae he even DD in he fan-ou cone of faul sie i. 3. The even DD a he primary oupu k (inpu of lach k) is raversed o find P(q, bc, i, j, k). 4. ER += P( q, bc, i, j, k)( R ( q, i, j) Δ q) end ER ER / num_of_laches; Figure 6. Pseudo-code of FSER flow. / / Figure 7. Pariioning circuis for speed-up leads o he loss of correlaions beween pulses of differen domains. The loss of accuracy is minimal for pariion size beyond a cerain poin. We define he pariion size as he maximum number of primary/pseudo primary inpus of each domain. larger pariion size allows a more global accoun of signal correlaions bu a he cos of a rapidly growing run ime and memory usage. The radeoff beween speed and accuracy is performed by adjusing he pariion size. We believe ha he mos significan impac of signal correlaion on pulse propagaion occurs in he neighborhood of he faul sie. Therefore, he improvemen of accuracy beyond a cerain pariion size (ypically, 5-2) is expeced o be minimal, and his is confirmed by he experimenal resuls. 6. Experimenal Resuls The saic SER analysis ool FSER was implemened in C++. The experimens invesigaed he accuracy of he saic echnique, he runime of he algorihm, and he speedaccuracy rade-off using he pariion heurisic. FSER akes a echnology-mapped nelis, equilibrium probabiliy of he primary inpus, clock period, and flux rae of he highenergy neurons, and gives ER of he laches a he primary oupus. The widely uilized flux raes for New York Ciy were used for analysis [6]. The SPICE echnology files were based on he erkeley Predicive Technology Model (PTM) for he nm echnology []. In order o verify he validiy of he FSER, an experimen based on SPICE simulaion was uilized. Since SPICE simulaion is very ime-consuming, we were only able o perform he ess on small arificially consruced benchmark circuis, wih he larges circui conaining 35 gaes. The SPICE simulaion is designed o measure he laching error probabiliy given a paricle srike wih a random daa se of (colleced charge q, srike ime, gae i, node j, inpu vecor V). Colleced charge q follows an exponenial disribuion [][4]. Srike ime is uniformly disribued beween and T clk. The probabiliy for a srike o occur in node j of gae i is proporional o node j s area. We assume ha all inpu vecors have equal probabiliy. The experimens were conduced as follows. For each daa se of (q,, i, j, V), a curren pulse wih magniude corresponding o he colleced charge q and polariy corresponding o node j s diffusion ype is injeced o node j of gae i a ime, wih inpu vecor V. Volage samples are aken a he lach oupu a T clk and 2T clk. If eiher value did no mach he correc one, an error is declared. Under his se-up, he condiional laching error probabiliy is equal o he number of errors divided by he oal number of simulaions. The run ime of he SPICE simulaions ranges from 5 minues o 45 minues for he arificial benchmark circuis. FSER akes ino accoun 5 differen pulse srenghs and is run-ime for every es circui is less han. seconds, giving a speed-up of over 9,X. ll experimens are conduced on a Dell GX26 worksaion running Redha Linux. The laching error probabiliies of he benchmark circuis are compared in Figure 8. The average error beween he wo ses of daa is 2% and can be well aribued o he simplified 2-parameer modeling of he error pulse in cell library characerizaion. Figure 9 shows he laching error probabiliy due o each gae in circui C. FSER wih circui pariioning heurisic is validaed on he ISCS 85 benchmark circuis. Pariion size is expressed in erms of he maximum number of primary/pseudo primary inpus of he pulse propagaion domains. Experimenal resuls in Table I show ha good accuracy can be achieved wih relaively small pariion size. The run-ime varies beween 22 seconds and 638 seconds for pariion size 5 (Table II). The runime increases rapidly wih pariion size as shown in Table II. However, improvemen in accuracy is very small for pariion sizes beyond 5. The esimaed ER for nm CMOS echnology is on he order of -5 FIT, where FIT is defined as failure in 9 hours. I is o be noed ha he pariion size is no he sole facor ha affecs he run ime. The circui srucure and he choice of pseudo primary inpus in pariioning also can grealy affec he DD size, which is a well known propery of DD. s a proxy of he memory usage, he maximum DD size in erms of he number of verices of he DD is measured and shown in Table II. The general rend is ha he DD size increases drasically wih pariion size. The increase of DD size wih respec o he circui size under he same pariion size is due o he increased complexiy of he nodal funcions.
Error Probabiliy.2. SPICE FSER C C2 C3 C4 C5 C6 C7 enchmark Circui Figure 8. Error probabiliies by FSER and SPICE simulaion. The average error is 2%. Error Probabiliy.4.3.2. SPICE FSER G G2 G3 G4 G5 Gae Figure 9. Laching error probabiliy due o each gae in circui C. Table I. i Error Raes for ISCS 85 benchmark circuis wih differen pariion sizes (Np) Circuis i Error Raes ( -5 FIT) Np=5 Np=2 Np=3 C432 3. 3.2 3. C499 2. 2. 2. C98 2.2 2..9 C355 2. 2. 2. C354 2.6 2.6 2.4 C535... C7552.9.8.8 7. Conclusions In his paper, we proposed a fas saic sof error analysis ool FSER. ccurae models are based on ST-like precharacerizaion mehods, and logical masking is compued via binary decision diagrams wih circui pariioning. Experimenal resuls indicae ha he FSER achieves good accuracy compared o he SPICE-based simulaion mehod. The average error across he benchmark circuis is 2% a over 9,X speed-up. Fuure work will focus on esimaing he sof error raes wih srong correlaions among he primary inpus. The correlaions of sof errors a he primary oupus will also be invesigaed. 8. cknowledgmen This research was suppored in par by GSRC, SRC, NSF, SUN, and Inel. 9. References [] P. Shivakumar, e al, Modeling he Effec of Technology Trends on he Sof Error Rae of Combinaional Logic, Proc. DSTN, pp. 389-398, 22. [2] H. Cha, e al, Gae-Level Simulaion Environmen for lpha-paricle-induced, IEEE Trans. Compuers, Vol. 45, pp. 248-256, 996. [3] K. Mohanram, e al, Cos-Effecive pproach for Reducing Sof Error Failure Rae in Logic Circuis, Proc. ITC, pp. 893-9, 23. [4] M. Zhang, e al, Sof Error Rae nalysis (SER) Mehodology, Proc. ICCD, pp.-8, 24. [5] Q. Zhou, e al, ''Transisor Sizing for Radiaion Hardening,'' Proc. IRPS, pp. 3-35, 24. [6] Q. Zhou, e al, ''Cos-Effecive Radiaion Hardening Technique for Combinaional Logic,'' Proc. ICCD, pp. - 6, 24. [7] P. C. Murley, e al, Sof-error Mone Carlo modeling program, SEMM, IM J. Res. Develop., Vol. 4, pp. 9-8, 996. [8] P. Hazucha, e al, Impac of CMOS Technology Scaling on he mospheric Neuron Sof Error Rae, IEEE Trans. Nucl. Sci., Vol. 47, pp. 2586 2594, 2. [9] R. ryan, Graph-based algorihms for oolean funcion manipulaion, IEEE Trans. Compuers., Vol. 35, pp.677-69, 986. [] F. Najm, Transiion densiy, a sochasic measure of aciviy in digial circuis, Proc. DC, pp.644-649, 99. [] PTM, hp://www-device.eecs.berkeley.edu/~pm/. [2] K. Mohanram, Closed-form simulaion and robusness models for SEU oleran design, Proc. VLSI Tes Symposium, pp. 327 333, 25. [3] K. Mohanram, ''Simulaion of ransiens caused by singleeven upses in combinaional logic,'' Proc. ITC, 25. [4] J. Jain, e al. Funcional pariioning for verificaion and relaed problems, rown/mit VLSI Conference, 992. [5] D. Sahoo, e al, Pariioning Mehodology for DD-based Verificaion, Proc. FMCD, 24. [6] P. E. Dodd, e al, asic mechanisms and modeling of single-even upse in digial microelecronics, IEEE Trans. Nucl. Sci. Vol. 5, pp. 583 62, 23. [7] P. Dahlgren, e al, swich-level algorihm for simulaion of ransiens in combinaional logic, Proc. In. Faul- Toleran Compuing Symp., pp. 27-26, 995 [8] G. C. Messenger, Collecion of charge on juncion nodes from ion racks, IEEE Trans. Nucl. Sci., Vol. 29, pp.224-23, 982 [9] G. R. Srinivasan, e al, ccurae predicive modeling of sof error rae due o cosmic rays and chip alpha radiaion, Proc. Inl. Reliabiliy Phys. Symp., pp. 2-6, 994. Table II. Run-ime and he maximum DD size for he ISCS 85 benchmark circuis. Circui Run-ime (s) Max DD Size Np=5 Np=2 Np=3 Np=5 Np=2 Np=3 C432 22 76 465 99 223 8683 C499 39 63 29 45 44 C98 66 86 5 69 87 26393 C355 4 62 9 45 46 C354 49 95 54 28 353 786 C535 278 546 55 372 65 2 C7552 638 78 72 83 672 62