Class D Audio Amplifier Design

Class D Audio Amplifier Design Class D Amplifier Introduction Theory of Class D operation, topology comparison Gate Driver How to drive the gate, key parameters in gate drive stage MOSFET How to choose, tradeoff relationships, loss calculation Package Importance of layout and package, new packaging technology Design Example 200W+200W stereo Class D amplifier Prepared Oct.8 2003 by Jun Honda and Jorge Cerezo

Trend in Class D Amplifiers Make it smaller! - higher efficiency - smaller package - Half Bridge Make it sound better! - THD improvement - fully digitally processed modulator

Traditional Linear Amplifier Feed back Vcc Error amp Bias Vcc Class AB amplifier uses linear regulating transistors to modulate output voltage. η = 30% at temp rise test condition.

How a Class D Amplifier Works Feed back Triangle Level Shift Nch +V C C Error Amp COMP Dead Time Nch -V C C Class D amplifier uses MOSFETs that are either ON or OFF. PWM technique is used to express analog audio signals with ON or OFF states in output devices.

Basic PWM Operation The output signal of comparator goes high when the sine wave is higher than the sawtooth. COMP Class D switching stage LPF Using f PWM =400KHz to modulate 25KHz sinusoidal waveform

Topology Comparison: Class AB vs Class D η Temp rise test condition η Efficiency Output Output Constant over Vbus Good Gain PSRR Proportional to Vbus 0 db Always from supply to load Direction of energy flow Both way Creates Vbus pumping phenomena

4 4 8 8 System Gate Drive MOSFET Design Example Analogy to Buck DC-DC Converter Buck Converter Class D Amplifier Gate Driver Gate Driver Fc of LPF is above 20KHz Q1 MOSFET Q1 MOSFET U1A Vref 3 + 1 2 - U1A ERROR AMP L1 INDUCTOR Q2 MOSFET C1 CAPACITOR R1 LOAD Audio signal input as a reference voltage 3 2 + - 1 ERROR AMP L1 INDUCTOR Q2 MOSFET C1 CAPACITOR R1 LOAD Load Current Direction Duty ratio is fixed Independent optimization for HS/LS Low R DS(ON) for longer duty, low Qg for shorter duty Both current directions Influence of dead time is different Dead time needs to be very tight Duty varies but average is 50% Same optimization for both MOSFETs Same R DS(ON) required for both sides

Loss in Power Device Loss Loss in class AB 2 CC V Pc = 0.2 8 R L P C π 1 Vcc Vcc = ω 2 π 2 2 R 0 L 2 2 Vcc 2K K = 8π RL π 2 Loss in Class D P TOTAL = Psw + Pcond + Pgd Pcond = Psw = C R OSS R ( 1 K sinω t) K sinω t d t DS ( ON ) L V 2 BUS Po f PWM + I Pgd = 2 Qg Vgs D V DS Regardless of output device parameters. t f f PWM f PWM Loss K=2/π K=1 Efficiency can be improved further! K=1 K is a ratio of Vbus and output voltage.

Supply voltage Current ratings MOSFET Gate Driver Linearity DC Offset PWM pattern Notes System Gate Drive MOSFET Design Example Half Bridge vs Full Bridge 0.5 x 2ch 1 1 2 2 MOSFETs/CH 4 MOSFETs/CH 1 Gate Driver/CH 2 Gate Drivers/CH Superior (No even order HD) Adjustment is needed Can be cancelled out 2 level 3 level PWM can be implemented Pumping effect Suitable for open loop design Need a help of feed back

Major Cause of Imperfection Pulse width error Quantization error Perturbation Zo Bus Pumping +V C C Non linear inductance / Capacitance DCR Audio source PWM Gate Driver Dead time Delay time -V C C Finite R DS(on) Vth and Qg Body diode recovery R DS(ON) ON delay OFF delay Finite dv/dt

ON System Gate Drive MOSFET Design Example THD and Dead Time High Side Dead Time Low Side Dead Time High Side OFF ON Low Side OFF 34 40 30 Dead Time 40nS Dead Time 15nS 20 High Side edges 10 Vout() t 0 10 Falling edges THD=2.1% THD=0.18% 34 20 30 Low Side edges 40 0 5.10 4 0.001 0.0015 0.002 0 t 0.0021 Note: THD (Total Harmonic Distortion) is a means to measure linearity with sinusoidal signal. THD = V + V 2 2 2 3 V fundamental +

Shoot Through and Dead Time Rg=10 ohm High side Vgs Low side Vgs 120 100 Q st as a function of O verlap Tim e & R g Vbus = 60V, Id = 2A, Vgs = 12V (O verlap tim e m easured from 50% Vgs high side fall to 10% Vgs low side rise) 80 60 Rg=1Ohms Rg=5Ohms rg=10o hm s Shoot through current 2A/div 40 20 0-10 -5 0 5 10 15 20 O verlap tim e (ns) -Shoot through charge increases rapidly as dead time gets shorter. -Need to consider manufacturing tolerances and temperature characteristics.

Power Supply Pumping Load Current Supply voltage Pumping effect +Vcc Vo Commutation current Half Bridge -Vcc Load Current V BUS Full Bridge max = 8 π f PWM VBUS R LOAD C BUS -Significant at low frequency output -Significant at low load impedance -Significant at small bus capacitors -Largest at duty = 25%, and 75% Commutation current

EMI consideration: Qrr in Body Diode 1 2 3 1. Low side drains inductor current 2. During dead time body diode of low side conducts and keep inductor current flow 3. At the moment high side is turned ON after dead time, the body diode is still conducting to wipe away minority carrier charge stored in the duration of forward conduction. This current generates large high frequency current waveform and causes EMI noises.

Gate Driver: Why is it Needed? Gate of MOSFET is a capacitor to be charged and discharged. Typical effective capacitance is 2nF. High side needs to have a gate voltage referenced to it s Source. Gate voltage must be 10-15V higher than the drain voltage. Need to control HS and LS independently to have dead time.

Functional Block Diagram Inside Gate Driver International Rectifier's family of MOS gate drivers integrate most of the functions required to drive one high side and one low side power MOSFET in a compact package. With the addition of few components, they provide very fast switching speeds and low power dissipation. Input Logic High side well

Boot Strap High Side Power Supply Charge Discharge ON ON When Vs is pulled down to ground through the low side FET, the bootstrap capacitor (C BOOT ) charges through the bootstrap diode (Dbs) from the Vcc supply, thus providing a supply to Vbs.

Boot Strap High Side Power Supply (Cont d) Boot Strap Capacitor Selection System Gate Drive MOSFET Design Example To minimize the risk of overcharging and further reduce ripple on the Vbs voltage the Cbs value obtained from the above equation should be should be multiplied by a factor of 15 (rule of thumb). Boot Strap Diode Selection The bootstrap diode (Dbs) needs to be able to block the full power rail voltage, which is seen when the high side device is switched on. It must be a fast recovery device to minimize the amount of charge fed back from the bootstrap capacitor into the Vcc supply. VRRM = Power rail voltage, max trr = 100ns, IF > Qbs x f For more details on boot strap refer to DT98-2

Power Dissipation in Gate Driver Whenever a capacitor is charged or discharged through a resistor, half of energy that goes into the capacitance is dissipated in the resistor. Thus, the losses in the gate drive resistance, internal and external to the MGD, for one complete cycle is the following: P G = V f SW Q G For two IRF540 HEXFET MOSFETs operated at 400kHz with Vgs = 12V, we have: PG = 2 12 37 10-9 400 10 3 = 0.36W R3 High Side SW1 R3 High Side R2 Low Side C1 Ciss R2 Low Side SW1 C1 Ciss For more details on gate driver ICs, refer to AN978

Power Dissipation in Gate Driver (Cont d) The use of gate resistors reduces the amount of gate drive power that is dissipated inside the MGD by the ratio of the respective resistances. These losses are not temperature dependent. Junction Tem perature (C) 150.00 125.00 200 100 100.00 10 75.00 50.00 25.00 0.00 1.E+03 1.E+04 1.E+05 1.E+06 Frequency (Hz) Figure 32: IR2010S Tj vs Frequency R G ATE = 10 O hm, V cc = 15V w ith IR FP E50

Layout Considerations Stray inductance LD1+LS1 contribute to undershoot of the Vs node beyond the ground IR2011 As with any CMOS device, driving any of parasitic diodes into forward conduction or reverse breakdown may cause parasitic SCR latch up.

Key Specs System Gate Drive MOSFET Design Example Gate Driver for Class D Applications IR2011(S) Fully operational up to +200V Low power dissipation at high switching frequency 3.3V and 5V input logic compatible Matched propagation delay for both channels Tolerant to negative transient voltage, dv/dt immune SO-8/DIP-8 Package SO-8

How MOSFETs Work A MOSFET is a voltage-controlled power switch. A voltage must be applied between Gate and Source terminals to produce a flow of current in the Drain.

MOSFET Technologies (1) IR is striving to continuously improve the power MOSFET to enhance the performance, quality and reliability. Hexagonal Cell Technology Planar Stripe Technology Trench Technology

MOSFET Technologies (2) Power MOSFET FOMs (R*Qg) have significantly improved between the released IR MOSFET technologies

Key Parameters of MOSFETs (1) Voltage Rating, BV DSS System Gate Drive MOSFET Design Example This is the drain-source breakdown voltage (with VGS = 0). BV DSS should be greater than or equal to the rated voltage of the device, at the specified leakage current, normally measured at Id=250uA. This parameter is temperature-dependent and frequently BV DSS / Tj (V/ C) is specified on datasheets. BV DSS MOSFET voltages are available from tens to thousand volts.

Key Parameters of MOSFETs (2) Gate Charge, Qg This parameter is directly related to the MOSFET speed and is temperatureindependent. Lower Qg results in faster switching speeds and consequently lower switching losses. The total gate charge has two main components: the gatesource charge, Qgs and, the gate-drain charge, Qgd (often called the Miller charge). System Gate Drive MOSFET Design Example Basic Gate Charge Waveform

Key Parameters of MOSFETs (3) Static Drain-to-Source On-Resistance, R DS(ON) This is the drain-source resistance, typically specified on data sheet at 25 C with VGS = 10V. R DS(ON) parameter is temperature-dependent, and is directly related to the MOSFET conduction losses. lower R DS(ON) results in lower conduction losses. Normalized On-Resistance vs. Temperature

Key Parameters of MOSFETs (4) Body Diode Reverse Recovery Characteristics, Q rr, t rr, I rr and S factor. Power MOSFETs inherently have an integral reverse body-drain diode. This body diode exhibits reverse recovery characteristics. Reverse Recovery Charge Qrr, Reverse Recovery Time trr, Reverse Recovery Current Irr and Softness factor (S = tb/ta), are typically specified on data sheets at 25 C and di/dt = 100A/us. Reverse recovery characteristics are temperature-dependent and lower trr, Irr and Qrr improves THD, EMI and Efficiency η. System Gate Drive MOSFET Design Example Typical Voltage Current Waveforms for a MOSFET Body Diode

Key Parameters of MOSFETs (5) Package MOSFET devices are available in several packages as SO-8,TO-220, D-Pak, I-Pak, TO- 262, DirectFET, etc. The selection of a MOSFET package for a specific application depends on the package characteristics such as dimensions, power dissipation capability, current capability, internal inductance, internal resistance, electrical isolation and mounting process.

Choosing the MOSFET Voltage Rating for Class D applications (1) MOSFET voltage rating for a Class D amplifier is determined by: Desired P OUT and load impedance (i.e. 250W on 4Ω) Topology (Full Bridge or Half Bridge) Modulation Factor M (80-90%) VB DSS min = 2 * P OUT * R LOAD M * 1.5 Typical additional factor due to stray resistance, power supply fluctuations and MOSFET Turn-Off peak voltage

Choosing the MOSFET Voltage Rating for Class D Applications (2) Full-Bridge Topology Class D amplifier Half-Bridge Configuration Class D amplifier Note 1. Modulation Factor M = 85%

Calculation of Switching Loss (1) Switching Losses are the result of turn-on and turn-off switching times MOSFET Turn-On MOSFET Turn-Off

Calculation of Switching Loss (2) Gate resistance Rg, and gate charge Qg, have a significant influence on turn-on and turn-off switching times Rg Ig t SWITCHING P SWITCHING R G Qg t SWITCHING P SWITCHING

Estimation of Switching Losses (1) Switching losses can be obtained by calculating the switching energy dissipated in the MOSFET E sw = 0 t System Gate Drive MOSFET Design Example V DS (t) * I D (t) dt Where t is the length of the switching pulse. Switching losses can be obtained by multiplying switching energy with switching frequency. P SWITCHING = E SW * F SW

Estimation of Conduction Loss (2) Conduction losses can be calculated using R DS(ON) @ Tj max and I DRMS current of MOSFET P CONDUCTION = (I D RMS ) 2 * R DS(ON) I D RMS is determined using amplifier specifications: I D RMS = P OUT R LOAD R DS(ON) data can be obtained from the MOSFET data sheet.

Maximum allowed power dissipation for a MOSFET mounted on a heat sink: System Gate Drive MOSFET Design Example Thermal Design P max = Tj / R thja max P max = (T amb Tj max ) / (R thjc max +R thcs max +R ths max +R thsa max ) Where: T amb = Ambient Temperature Tj max = Max. Junction Temperature R thjc max = Max. Thermal Resistance Junction to Case R thcs max = Max. Thermal Resistance Case to Heatsink R ths max = Max. Thermal Resistance of Heatsink R thsa max = Max. Thermal Resistance Heatsink to Ambient

R DS(ON) vs Qg There is tradeoff between Static Drain-to-Source On- Resistance, R DS(ON) and Gate charge, Qg Higher R DS(ON) Lower Qg Higher P CONDUCTION & Lower P SWITCHING Lower R DS(ON) Higher Qg Higher P SWITCHING &Lower P CONDUCTION Gen 7.5 100V MOSFET Platform R DS(ON) vs. Qg

Die Size vs Power Loss (1) Die size has a significant influence on MOSFET power losses Smaller Die Higher P CONDUCTION & Lower P SWITCHING Bigger Die Higher P SWITCHING &Lower P CONDUCTION Total Loss System Gate Drive MOSFET Design Example Gen 7 100V MOSFET Platform Power Losses @ 384kHz Conduction Loss Switching Loss

Die Size vs Power Loss (2) Die size is directly related with R DS(ON) and R THjc of the MOSFET Smaller Die Higher R DS(ON) and Higher R THjc Bigger Die Lower R DS(ON) and Lower R THjc 55V Trench Technology MosFET Die Size vs. R DS(ON) 55V Trench Technology MosFET Die Size vs. R THjc

Choosing the Right MOSFET for Class D Applications (1) The criteria to select the right MOSFET for a Class D amplifier application are: VB DSS should be selected according to amplifier operating voltage, and it should be large enough to avoid avalanche condition during operation Efficiency η is related to static drain-to-source on-resistance, R DS(ON). smaller R DS(ON) improves efficiency η. R DS(ON) is recommended to be smaller than 200mΩ for mid and high-end power, full-bandwidth amplifiers Low gate charge, Qg, improves THD and efficiency η. Qg is recommended to be smaller than 20nC for mid and high-end power, full-bandwidth amplifiers

Choosing the Right MOSFET for Class D Application (2) Amplifier performance such as THD, EMI and efficiency η are also related to MOSFET reverse recovery characteristics. Lower trr, Irr and Qrr improves THD, EMI and efficiency η Rthjc should be small enough to dissipate MOSFET power losses and keep Tj < limit Better reliability and lower cost are achieved with higher MOSFET Tj max Finally, selection of device package determines the dimensions, electrical isolation and mounting process. These factors should be considered in package selection. Because cost, size and amplifier performance depend on it.

Development of Class D Dedicated Devices Performance of the Class D amplifying stage strongly depends on the characteristics of MOSFETs and ICs. Designers of driver IC and MOSFET silicon need to keep the special requirements of the Class D application in mind.

Influences of Stray Inductance PCB layout and the MOSFET internal package inductances contribute to the stray inductance (L S ) in the circuit. Stray inductances affect the MOSFET performance and EMI of the system.

Influences of Stray Inductance Drain and source stray inductances reduces the gate voltage during turn-on resulting in longer switching time. Also during turn-off, drain and source stray inductances generate a large voltage drop due to di D /dt, producing drain to source overvoltage transients.

DirectFET Packaging copper drain clip passivated die die attach material Use a single multiple-finned heat sink to dissipate heat from devices DirectFET devices gate connection source connection copper track on board Circuit board Both Side Cooling Thermal interface gap filler material or pad 4.8mm ~ Remove wirebonds from package and replace with large area solder contacts Reduced package inductance and resistance Copper can enables dual sided cooling

DirectFET Packaging DirectFET waveform SO-8 waveform 30A VRM output current 500 khz per phase Silicon of the near identical active area, voltage and generation used in both packages Inductance related ringing greater in case of SO-8

Class D Amp Reference Design Specs Topology: Half Bridge IR Devices: IR2011S, IRFB23N15D Switching frequency: 400kHz (Adjustable) Rated Output Power: 200W+200W / 4 ohm THD: 0.03% @1kHz, Half Power Frequency Response: 5Hz to 40kHz (-3dB) Power Supply: ~ ±50V Size: 4.0 x 5.5

Class D Amp Reference Board: Block Diagram Feed back +V C C + Integrator LT1220 Level Shifter 2N5401 LPF GND IR2011S Gate Driver Comparator 74HC04 -V C C IRFB23N15D -VCC

4 1 8 7 1 2 3 4 D R1 CH1 R3 +50V D 47K 1K C J1 1418-ND C3 R10 10K R8 10uF, 50V D1 330K GNDP D2 1N4148 1N4148 GNDP C6 dummy C8 GNDP 0.1uF, 50V 3 2 R21 5K U1 6 LT1220CS8 C26 0.1uF,50V GNDP C17 1000pF, 100V R23 100 R26 C18 1K 1000pF, 100V R4 1K MMBT5401 C E R11 10K Q9 MMBT3904 Q1 U2 1 8 2 7 3 6 4 5 TC7WH04FU C9 1uF, 16V U4 1 8 2 7 3 6 4 5 TC7WH08FU 6 5 U6 Lin Hin HO VB VS VCC COM 8 LO IR2011 Gate Driver 3 2 4 1 7 C1 220pF, 100V R28 22K C23 0.33uF, 25V D14 MURS120DICT Q2 MMBT5401 R31 9.1 R50 9.1 C25 0.01uF R35 470 MA2YD23 D6 1 MA2YD23 D7 IRFB23N15D 1 IRFB23N15D 3 2 3 2 R37 47mOHM, 2W Q5 Q6 R39 1 0.1uF, 100VC49 C30 0.22uF, 100V L1 18uH R12 10K R53 R54 R55 R56 dummy dummy dummy dummy C51 0.22uF, 100V C31 470uF, 50V C38 J3 1 2 3 MKDS5/3-9.5 J5 1 2 MKDS5/2-9.5 C B R44 4.7K B C19 dummy 1 1 System Gate Drive MOSFET Design Example Circuit Diagram Feed Back Path Input analog GNDP Integrator GNDP C42 R13 B 10K 3.3uF, 35V C? R41.01uF, 50V 100K +5V Level Shift TP3 PAD TP PROTECT TP4 PAD TP Quantize R82 10K R64 10 VDD_1 GNDP R49 4.7 Over Current D10 MURS120 D11 MURS120 GNDP LPF GNDP GNDP 0.47uF, 100V GNDP GNDP R61 10, 1W 8 GNDP RLY1A 5 255-1054 (1) -50V CH1 OUT GNDP C33 Speaker output 0.22uF, 100V -5V SD1 R47 10 C44 1uF, 16V Snubber -50+VCC R14 10K C32 0.22uF, 100V C39 470uF, 50V -50_1 A CLASS D REFERENCE BOARD --- CHANNEL 1 Sheet 2 of 4 Number: Drawn by: Revision:1.0 File: 1. ClassD_Refbd_R2-0_CH1.~ch 23-Sep-2003 Time: Date: 15:13:04 1 2 3 4 Title GNDP GNDP GNDP Approved by: INTERNATIONAL RECTIFIER EL SEGUNDO, CALIFORNIA, USA A

Class D Amp Reference Board: Layout Analog Input (CH1) Analog Input (CH2) Modulator (CH1) ±5V Regulator Modulator (CH2) Gate Driver Gate Driver MOSFET MOSFET HeatSink Bus Capacitor Protection LPF (CH1) LPF (CH2) Speaker (CH1) Speaker (CH2) +12V DC/DC Power Supply

Performance 50W / 4Ω, 1KHz, THD+N=0.0078% 9.35 10 HP8903B THD+N v.s. Output Power CH1, f=1khz, RL=4Ω 1 VCC=±50.0V f PWM =426KHz THD 0.1 342W / 4Ω, 1KHz, THD+N=10% 0.01 7.5 10 1.10 3 3 0.1 1 10 100 1.10 3 0.16 Output_Power 342.3 Peak Output Power (f=1khz) 120W / 8Ω / ch, THD=1% 180W / 8Ω / ch, THD=10% 245W / 4Ω / ch, THD=1% 344W / 4Ω / ch, THD=10%

Switching waveform System Gate Drive MOSFET Design Example Performance (Cont d) 10 10 1 THD+N v.s. Frequency HP8903B CH1, Po=50W, RL=4Ω VCC=±50.0V f PWM =364KHz THD 0.1 0.01 7.1 10 1.10 3 3 10 100 1.10 3 1.10 4 1.10 5 20 Frequency 210 4 LPF Residual Noise: 62.5µVrms, A-Weighted, 30KHz-LPF

Conclusion Highly efficient Class D amplifiers now provide similar performance to conventional Class AB amplifiers - If key components are carefully selected and the layout takes into account the subtle, yet significant impact due to parasitic components. Constant innovation in semiconductor technologies helps the growing Class D amplifiers usage due to improvements in higher efficiency, increased power density and better audio performance.