UA11 UNIBUS ANALYZER USER MANUAL

S H I R E S O F T UA11 UNIBUS ANALYZER USER MANUAL Version 1.0A January 22, 2007 1206-B Mountainview-Alviso Rd Sunnyvale, CA 94089 telephone: 408 541-1383 fax: 408 541-1626 w w w. s h i r e s o f t. c o m

Table of Contents Introduction 1 Using UA11 3 Unbuffered Test Points 3 Buffered Test Points 4 Trigger Test Points 5 Making Timing Measurements 6 Placement of UA11 on the UNIBUS 6 Parts Selection 7 Assembling the UA11 9 EC-001 11 UA11 Schematics 15 S h i r e s o f t, I n c. i

Introduction At one time or another while maintaining or restoring a UNIBUS based system, examining one or more of the signals will be required. The problem has always been to identify the individual signals. Another problem is that the signals are easily accessible only on the bottom of the backplane. As is usually the case while debugging a problem, some UNIBUS signals need to be examined while also looking at signals on an individual board. This usually means setting probes on both the top and bottom of the system. The UA11 is diagnostic tool for examining and diagnosing problems on the UNIBUS. It can be used alone or with an oscilloscope and/or logic analyzer. LEDs are provided for direct monitoring of all of the UNIBUS signals. Comparators are provided to allow for the triggering an oscilloscope or logic analyzer when an address and/or data value is matched. All of the signals are brought out to header blocks for easy probing and access. Each of the signals on the headers are paired with a ground for easy attaching of probes. S h i r e s o f t, I n c. 1

Using UA11 The UA11 can be installed into any SPC slot. However, to be fully useful it should be installed into quad extender. By being placed into an extender, easy access can be gained to the test points, switches and LEDs. The UA11 also acts as a double grant card. It provides continuity for both the bus grant and NPG signals. All of the test points on the UA11 are paired with a ground pin to allow for easy connection of probes for either a logical analyzer or oscilloscope. The following sections describe the different test points and their uses. Unbuffered Test Points The unbuffered test points provide direct access to the UNIBUS signals as they exist on the bus. These test points allow the signals to be easily probed and are most useful in looking at the exact signals with an oscilloscope to determine if there are electrical issues on the bus or if extremely accurate timing information needs to be gathered. Transfer Type Control Address Bus Parity Initialization Requests & Grants Data Bus Unbuffered Test Points S h i r e s o f t, I n c. 3

Buffered Test Points The buffered tests points buffer the individual signals, sharpen the rising and falling edges and provide the signals in their logical levels. Many UNIBUS signals are inverted, that is a logical 1 is represented by the signal being at 0V. All of the buffered signals represent a logical 1 as a TTL high level (something over 2.4V). The buffered signals also present the transfer type signals in their decoded form so there is an individual test point for each of the four transfer types. Transfer Type Control Address Bus Parity Initialization Requests & Grants Data Bus Buffered Test Points These test points are a bit easier to use than the unbuffered test points because the signals are presented in their true form and the transfer types are decoded. S h i r e s o f t, I n c. 4

Trigger Test Points The trigger test points allow for an address and data values to be matched and the result to be used to trigger an oscilloscope or a logic analyzer. The trigger is qualified by both the exact value (as entered on the appropriate set of switches) and the MSYN signal. This means that the value is only checked from the device (or CPU) that is driving the bus. It is also important to note that the trigger is positive going (that is, a match is indicated when the match signal is at a logic 1 ). Address Match Data Match Trigger Test Points S h i r e s o f t, I n c. 5

Making Timing Measurements There are a few things to consider when timing measurements are being made using the UA11. This also includes interpretation of signals when using the Address and/or Data Match test points. 1. The buffered signals have a 15 to 22ns delay from the unbuffered signals. This is the propagation delay through the 74LS14. 2. The buffered transfer type signals have an additional 5 to 12ns delay over the other buffered signals. Thus the total delay from the unbuffered signals is between 20 and 34ns. This is the propagation delay through the 74S139 in addition to the delay through the 74LS14. 3. The address and data match signals have an additional 20 to 45ns delay over the other buffered signals. Thus the total delay from the unbuffered signals is between 35 to 67ns. This is due to the propagation delay through the comparator logic. High speed logic families (74S, 74AS and 74ALS) where used in this section to keep the delays to a minimum. Placement of UA11 on the UNIBUS For the most part, where the UA11 is on UNIBUS is not important. However, if any of the Bus Request (BRx), Bus Grant (BGx), Non-Processor Request (NPR) or Non-Processor Grant (NPG) signals are to be monitored, the UA11 must appear before any device that might use or generate those signals. This is because those signals are daisy chained and may not be visible to the UA11. S h i r e s o f t, I n c. 6

Parts Selection The following table lists the parts that are required. All of the components listed below are available from various component suppliers (Digikey, Mouser Electronics, etc.). Certain components were selected for low propagation delays (ie AS, ALS, and S components) do not substitute other components. The 74LS14N was used for receivers on the UNIBUS because of the relatively long rise and fall times of signals on the UNIBUS. The use of Schmitt trigger devices allows for the slow edges of those signals to be converted to sharp edged signals for use on the remainder of the board. Do not subsitute. PART VALUE DESCRIPTION C1 - C4 100uf @ 10V Alxial lead electrolytic C11 - C19, C24, C31, C33 - C37, C39, C41, C45, C51 - C59 10nf @ 50 V Ceramic disc IC1 - IC9, IC14 74LS14N Hex Schmitt trigger inverter IC21, IC23, IC26 - IC28 74ALS520N 8 bit comparitor IC24 74AS27N Triple 3 input NOR gate IC25 74AS04N Hex inverter IC35 74S139N Dual 2 to 4 decoder IC31, IC41 - IC48 7406N Hex Inverter w/hv OC outputs IC49 7407N Hex buffer w/hv OC outputs LED101 - LED112, LED201 - LED212, LED301 - LED316, LED401 - LED418 Kingbright L7113SRD/E 5mm Red LED R101 - R112, R201 - R212, R301 - R316, R401 - R418 JP1, JP11 JP2, JP3, JP12, JP13, JP18 JP4, JP14 JP5, JP8, JP15 JP6, JP16 JP7, JP17 150 ohm 1/8 watt 2 x 16 header 0.1 spacing 2 x 4 header 0.1 spacing 2 x 3 header 0.1 spacing 2 x 2 header 0.1 spacing 2 x 18 header 0.1 spacing 2 x 7 header 0.1 spacing S1, S2, S4, S5 8 position DIP switch S6 2 position DIP switch S h i r e s o f t, I n c. 7

The resistors are used for current limiting of the LEDs. Use values that limit the current through the LEDs to below the maximum current allowed by the LED chosen. In general, more current through a LED provides for a brighter LED when it is on. The 150 ohm value selected for the specified LED is almost too bright (by providing for about 20ma max current through the LED). However, this is somewhat personal preference. S h i r e s o f t, I n c. 8

Assembling the UA11 Before starting assembly, clean the PCB with a no residue contact cleaner. That will remove any oils and residue that may be present on the board after the manufacturing process. It also goes without saying to use good soldering techniques. The following page illustrates the board layout with the identification of the parts on the UA11 board. Note that the parts are not numbered sequentially. They are numbered in an row - column manner. Row 1 for a particular type of component is the row closest to the edge connector. It is best to insert and then solder the components in the order of the hight they are above the board. This reduces the chances of a component being askew once soldered. Pay particular attention to the headers. Make sure that the ICs are placed in their correct locations and orientations. Check that C1 through C4 are inserted with the correct polarity. The same holds true for all of the LEDs. For the switches, it is best to orient them so that the on position of the switch is towards the edge connectors. This allows the switches to be set/read more easily (1 is up, 0 is down), but it s personal preference and may vary depend upon which type of DIP switch is used. Examine all of the solder joints to make sure that there is enough solder. The joints should look clean and bright and there should be no solder bridges. Remedy any defects at this point. S h i r e s o f t, I n c. 9

Once complete, clean the board with a good no residue flux cleaner that corresponds to the type of flux used in the solder. S h i r e s o f t, I n c. 10

EC-001 Unfortunately the first version of the UA11 has a bug where sense of the NPG and BG4 through BG7 had the wrong sense. This is most obvious in that the LEDs for these signals are lit when the signals are deasserted (they like all other signals should be not lit unless they are asserted). This change remedies that defect and only affects the A revision of the board. This change is not absolutely required. It is completely functional without this change. However it must be remembered that the above signals will be inverted on all of the test points as well. The A revision can be identified by no revision identification on the board. It can also be identified by a copyright 2005 in the silkscreen. Later revision boards have a later copyright date. This change is implemented as 5 trace cuts and 10 wire adds. No additional components are required. The following tables identify the cuts and adds. There are also illustrations which show the preferred locations for the cuts. There are no illustrations for the adds, since they are done with individual wires it is less critical and subject to individual taste. Traces to be cut Wires to be added IC PIN FROM TO IC5 10 IC5 8 IC5 2 IC5 4 IC5 6 Package Pin Package Pin IC5 10 IC25 11 IC5 8 IC25 9 IC5 2 IC25 13 IC5 4 IC25 3 IC5 6 IC25 5 IC25 10 IC43 3 IC25 8 IC43 9 IC25 12 IC44 5 IC25 4 IC44 9 IC25 6 IC44 11 The illustrations show the cuts in red. There are two cuts on the bottom (non-component side) of the board. All of the remaining cuts and all of the adds are on the top (component side) of the board. All cuts should be done with a very sharp fine point knife (e.g. X-Acto). Do not cut any deeper than necessary to ensure that the trace has been cut. It is better to make two cuts a slight distance (1/16 ) apart than to make a deep cut. Perform all of the cuts and check with an ohmmeter before doing any of the adds. S h i r e s o f t, I n c. 11

It is recommended that fine gauge wire (30 gauge) be used for the adds. The wires should be kept reasonably short. It is not necessary to run the wires directly from IC25 to IC43 and IC44. There are vias on some traces that can be used as attach points for some of the wires. A minimum amount of solder and heat should be used since in some cases soldering directly to one of the leads of an IC is required. It is important to watch for solder bridges during this step. Any that occur should be removed immediately. Top (component side) of board showing location of cuts Cut trace from IC5 pin 6. Cut trace from IC5 pin 8. Cut trace from IC5 pin 2. S h i r e s o f t, I n c. 12

Bottom (solder side) of board showing locations of the cuts Cut trace from IC5 pin 10. Cut trace from IC5 pin 4. S h i r e s o f t, I n c. 13

UA11 Schematics The following schematics represent the A revision of the board. They will updated (confined to sheet 4) once the B revision has been released. S h i r e s o f t, I n c. 15