FDMA0PZ Dual P-Channel PowerTrench MOSFET 0V,.7A, 7m Features Max r DS(on) = 7m at V GS =.V, I D =.7A Max r DS(on) = 9m at V GS =.V, I D =.A Max r DS(on) = 0m at V GS =.8V, I D =.0A Max r DS(on) = 9m at V GS =.V, I D =.0A Low profile - 0.8 mm maximum - in the new package MicroFET x mm HBM ESD protection level > kv typical (Note ) RoHS Compliant Free from halogenated compounds and antimony oxides Pin General Description July 0 This device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra-portable applications. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses. When connected in the typical common source configuration, bi-directional current flow is possible. The MicroFET X package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. FDMA0PZ Dual P-Channel PowerTrench MOSFET S G D D D S 6 D G G MicroFET X D G S D S MOSFET Maximum Ratings T A = C unless otherwise noted Symbol Parameter Ratings Units V DS Drain to Source Voltage 0 V V GS Gate to Source Voltage ±8 V Drain Current -Continuous (Note a).7 I D -Pulsed 6 P D Power Dissipation (Note a) (Note b) T J, T STG Operating and Storage Junction Temperature Range to +0 C Thermal Characteristics. 0.7 A W R JA Thermal Resistance for Single Operation, Junction to Ambient (Note a) 86 R JA Thermal Resistance for Single Operation, Junction to Ambient (Note b) 7 R JA Thermal Resistance for Dual Operation, Junction to Ambient (Note c) 69 R JA Thermal Resistance for Dual Operation, Junction to Ambient (Note d) Package Marking and Ordering Information C/W Device Marking Device Package Reel Size Tape Width Quantity 0 FDMA0PZ MicroFET X 7 8mm 000 units 009 Fairchild Semiconductor Corporation FDMA0PZ Rev.C
Electrical Characteristics T J = C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain to Source Breakdown Voltage I D = 0 A, V GS = 0V 0 V BV DSS Breakdown Voltage Temperature I T J Coefficient D = 0 A, referenced to C mv/ C I DSS Zero Gate Voltage Drain Current V DS = 6V, V GS = 0V A I GSS Gate to Source Leakage Current V GS = ±8V, V DS = 0V ±0 A On Characteristics V GS(th) Gate to Source Threshold Voltage V GS = V DS, I D = 0 A 0. 0.7.0 V V GS(th) T J r DS(on) Gate to Source Threshold Voltage Temperature Coefficient Static Drain to Source On-Resistance I D = 0 A, referenced to C. mv/ C V GS =.V, I D =.7A 60 7 V GS =.V, I D =.A 7 9 V GS =.8V, I D =.0A 00 0 V GS =.V, I D =.0A 0 9 V GS =.V, I D =.7A,T J = C 8 9 g FS Forward Transconductance V DS = V, I D =.7A S Dynamic Characteristics C iss Input Capacitance 90 6 pf V DS = 0V, V GS = 0V, C oss Output Capacitance 00 pf f = MHz C rss Reverse Transfer Capacitance 90 pf m FDMA0PZ Dual P-Channel PowerTrench MOSFET Switching Characteristics t d(on) Turn-On Delay Time 9 8 ns V DD = 0V, I D = A t r Rise Time ns V GS =.V, R GEN = 6 t d(off) Turn-Off Delay Time 6 0 ns t f Fall Time 7 60 ns Q g(tot) Total Gate Charge V DD = 0V, I D =.7A 8.6 nc Q gs Gate to Source Gate Charge V GS =.V 0.7 nc Q gd Gate to Drain Miller Charge.0 nc Drain-Source Diode Characteristics I S Maximum Continuous Source-Drain Diode Forward Current. A V SD Source to Drain Diode Forward Voltage V GS = 0V, I S =.A (Note ) 0.8. V t rr Reverse Recovery Time 8 ns I F =.7A, di/dt = 00A/ s Q rr Reverse Recovery Charge nc FDMA0PZ Rev.C
Notes: : R JA is determined with the device mounted on a in oz. copper pad on a. x. in. board of FR- material. R JC is guaranteed by design while R JA is determined by the user's board design. (a) R JA = 86 C/W when mounted on a in pad of oz copper,." x." x 0.06" thick PCB. For single operation. (b) R JA = 7 C/W when mounted on a minimum pad of oz copper. For single operation. (c) R JA = 69 o C/W when mounted on a in pad of oz copper,. x. x 0.06 thick PCB, For dual operation. (d) R JA = o C/W when mounted on a minimum pad of oz copper. For dual operation. a) 86 o C/W when mounted on a in pad of oz copper. : Pulse Test : Pulse Width < 00us, Duty Cycle <.0% b) 7 o C/W when mounted on a minimum pad of oz copper. c) 69 o C/W when mounted on a in pad of oz copper. : The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. d) o C/W when mounted on a minimum pad of oz copper. FDMA0PZ Dual P-Channel PowerTrench MOSFET FDMA0PZ Rev.C
Typical Characteristics T J = C unless otherwise noted -ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 6 0 0.0 0..0..0 Figure..6...0 0.8 V GS = -.8V V GS = -.V V GS = -.0V V GS = -.V V GS = -.0V V GS = -.V PULSE DURATION = 00 s DUTY CYCLE =.0%MAX -VDS, DRAIN TO SOURCE VOLTAGE (V) I D = -.7A V GS = -.V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE.0 PULSE DURATION = 00 s V GS = -.V DUTY CYCLE =.0%MAX 0.6 0 6 -ID, DRAIN CURRENT(A) On Region Characteristics Figure. Normalized On-Resistance vs Drain Current and Gate Voltage 0.6-0 - 0 0 7 00 0 T J, JUNCTION TEMPERATURE ( o C) Figure. Normalized On-Resistance vs Junction Temperature rds(on), DRAIN TO SOURCE ON-RESISTANCE (m ).6..8. 00 60 0 80 V GS = -.V I D = -.8A Figure. V GS = -.0V T J = o C V GS = -.8V V GS = -.0V V GS = -.V PULSE DURATION = 00 s DUTY CYCLE =.0%MAX T J = o C 0 0 6 -V GS, GATE TO SOURCE VOLTAGE (V) On-Resistance vs Gate to Source Voltage FDMA0PZ Dual P-Channel PowerTrench MOSFET -I D, DRAIN CURRENT (A) 6 PULSE DURATION = 00 s DUTY CYCLE =.0%MAX V DD = -V T J = o C T J = - o C 0 0.0 0..0..0 -V GS, GATE TO SOURCE VOLTAGE (V) Figure. Transfer Characteristics T J = o C -IS, REVERSE DRAIN CURRENT (A) 0 0. 0.0 E- V GS = 0V T J = o C T J = o C T J = - o C E- 0.0 0. 0. 0.6 0.8.0.. -V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Source to Drain Diode Forward Voltage vs Source Current FDMA0PZ Rev.C
Typical Characteristics T J = C unless otherwise noted -VGS, GATE TO SOURCE VOLTAGE(V) -ID, DRAIN CURRENT (A) I D = -.7A 0 0 6 8 0 Q g, GATE CHARGE(nC) Figure 7. 0 0 0. r DS(on) LIMIT V GS =-.V SINGLE PULSE R JA =7 o C/W T A = o C V DD = -V V DD = -V V DD = -0V 000 Gate Charge Characteristics Figure 8. 0.0 0. 0 -VDS, DRAIN to SOURCE VOLTAGE (V) Figure 9. Forward Bias Safe Operating Area 00us ms 0ms 00ms s 0s DC 60 CAPACITANCE (pf) P(PK), PEAK TRANSIENT POWER (W) 00 f = MHz V GS = 0V C iss C oss C rss 0 0. 0 -V DS, DRAIN TO SOURCE VOLTAGE (V) 00 0 V GS = -0V Capacitance Characteristics SINGLE PULSE R JA = 7 o C/W T A = o C I = I SINGLE PULSE 0. 0-0 - 0-0 - 0 0 0 0 0 t, PULSE WIDTH (s) FOR TEMPERATURES ABOVE o C DERATE PEAK CURRENT AS FOLLOWS: 0 T A ---------------------- Figure 0. Single Pulse Maximum Power Dissipation T A = o C 0 FDMA0PZ Dual P-Channel PowerTrench MOSFET NORMALIZED THERMAL IMPEDANCE, Z JA 0. 0.0 DUTY CYCLE-DESCENDING ORDER D = 0. 0. 0. 0.0 0.0 0.0 SINGLE PULSE 0.00 0-0 - 0-0 - 0 0 0 0 0 t, RECTANGULAR PULSE DURATION (s) Figure. Transient Thermal Response Curve P DM t t NOTES: DUTY FACTOR: D = t /t PEAK T J = P DM x Z JA x R JA + T A FDMA0PZ Rev.C
Dimensional Outline and Pad Layout FDMA0PZ Dual P-Channel PowerTrench MOSFET Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http:///package/packagedetails.html?id=pn_mldeb-x06 FDMA0PZ Rev.C 6
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Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I68 7
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