SPC564Bxx SPC56ECxx. 32-bit MCU family built on the Power Architecture for automotive body electronics applications. Features

SP564Bxx SP56Exx 32-bit MU family built on the Power Architecture for automotive body electronics applications Datasheet - production data Features e200z4d, 32-bit Power Architecture Up to 120 MHz and 200 MPs operation e200z0h, 32-bit Power Architecture Up to 80 MHz and 75 MPs operation Memory Up to 3 MByte on-chip Flash with E Up to 256 KByte on-chip SRAM with E 64KByte on-chip Data Flash with E 16-entry memory protection unit (MPU) User selectable Memory BST nterrupts 255 interrupt sources with 16 priority levels Up to 54 ext. RQ including 30 wake-up GPs: from 147 (LQFP176) to 199 (LBGA256) LBGA256 (17 x 17 x 1.7 mm) System timer units 8-ch. 32-bit periodic interrupt timer (PT) 4-channel 32-bit system timer (STM) Safety System Watchdog Timer (SWT) Real-time clock timer (RT/AP) ems, 16-bit counter timed units Up to 64 channels with PWM/M// Two AD (10-bit and 12-bit) Up to 62 channels extendable to 90 ch. Multiple Analog Watchdog Dedicated diagnostic features for lighting Advanced shiffted PWM generation AD conversion synchronized on PWM ommunication interfaces LQFP208 LQFP176 (28 x 28 x 1.4 mm) (24 x 24 x 1.4 mm) Up to 6 FlexAN with 64 buffers each Up to 10 LNFlex/UART channels Up to 8 buffered DSP channels 2 interface ne FleyRay (dual-ch.) with 128 buffers Fast Ethernet ontroller ryptographic Services Engine (SE) AES-128 en/decryption, MA auth. Secured device boot mode 32-ch. edma with multiple request sources lock generation 4 to 40 MHz main oscillator 16 MHz internal R oscillator Software-controlled FMPLL 128 khz internal R oscillator 32 khz auxiliary oscillator lock Monitoring Unit (MU) Low power capabilities Ultra low power STANDBY AN Sampler to store AN D in STBY Fast wake-up and exectute from RAM Exhaustive debugging capability Nexus 3+ interface on LBGA256 only Nexus 1 on all devices Voltage supply Single 5 V or 3.3 V supply n-chip Vreg with external ballast transitor perating temperature range -40 to 125 March 2016 DocD17478 Rev 9 1/123 This is information on a product in full production. www.st.com

SP564Bxx-SP56Exx Table 1. Device summary Package Part number 1.5 MByte 2 MByte 3 MByte LQFP176 LQFP208 SP564B64L7 SP56E64L7 SP564B64L8 SP56E64L8 SP564B70L7 SP56E70L7 SP564B70L8 SP56E70L8 SP564B74L7 SP56E74L7 SP564B74L8 SP56E74L8 LBGA256 SP56E64B3 SP56E70B3 SP56E74B3 2/123 DocD17478 Rev 9

SP564Bxx-SP56Exx ontents ontents 1 ntroduction................................................ 9 1.1 Document verview.......................................... 9 1.2 Description................................................. 9 1.3 Block diagram.............................................. 12 2 Package pinouts and signal descriptions....................... 15 2.1 Pad types................................................. 18 2.2 System pins............................................... 18 2.3 Functional ports............................................ 19 3 Electrical haracteristics.................................... 51 3.1 Parameter classification...................................... 51 3.2 NVUSR register........................................... 51 3.2.1 NVUSR [PAD3V5V(0)] field description....................... 52 3.2.2 NVUSR [PAD3V5V(1)] field description....................... 52 3.3 Absolute maximum ratings.................................... 52 3.4 Recommended operating conditions............................ 54 3.5 Thermal characteristics...................................... 57 3.5.1 Package thermal characteristics.............................. 57 3.5.2 Power considerations...................................... 58 3.6 pad electrical characteristics............................... 58 3.6.1 pad types............................................. 58 3.6.2 input D characteristics.................................. 59 3.6.3 output D characteristics................................. 60 3.6.4 utput pin transition times................................... 62 3.6.5 pad current specification................................. 63 3.7 RESET electrical characteristics............................... 65 3.8 Power management electrical characteristics..................... 67 3.8.1 Voltage regulator electrical characteristics...................... 67 3.8.2 VDD_BV options.......................................... 68 3.8.3 Voltage monitor electrical characteristics........................ 69 3.9 Low voltage domain power consumption......................... 70 3.10 Flash memory electrical characteristics.......................... 72 DocD17478 Rev 9 3/123 5

ontents SP564Bxx-SP56Exx 3.10.1 Program/Erase characteristics................................ 72 3.10.2 Flash memory power supply D characteristics.................. 74 3.10.3 Flash memory start-up/switch-off timings....................... 75 3.11 Electromagnetic compatibility (EM) characteristics................ 75 3.11.1 Designing hardened software to avoid noise problems............. 75 3.11.2 Electromagnetic interference (EM)............................ 76 3.11.3 Absolute maximum ratings (electrical sensitivity)................. 76 3.12 Fast external crystal oscillator (4 40 MHz) electrical characteristics.... 77 3.13 Slow external crystal oscillator (32 khz) electrical characteristics...... 80 3.14 FMPLL electrical characteristics................................ 83 3.15 Fast internal R oscillator (16 MHz) electrical characteristics......... 83 3.16 Slow internal R oscillator (128 khz) electrical characteristics........ 85 3.17 AD electrical characteristics.................................. 85 3.17.1 ntroduction.............................................. 85 3.18 Fast Ethernet ontroller...................................... 96 3.18.1 M Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_LK). 96 3.18.2 M Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_LK).... 97 3.18.3 M Async nputs Signal Timing (RS and L).................. 97 3.18.4 M Serial Management hannel Timing (MD and MD).......... 98 3.19 n-chip peripherals......................................... 99 3.19.1 urrent consumption....................................... 99 3.19.2 DSP characteristics...................................... 100 3.19.3 Nexus characteristics...................................... 106 3.19.4 JTAG characteristics...................................... 108 4 Package characteristics.................................... 110 4.1 EPAK...............................................110 4.2 Package mechanical data....................................110 4.2.1 LQFP176 package mechanical drawing....................... 110 4.2.2 LQFP208 package mechanical drawing....................... 112 4.2.3 LBGA256 package mechanical drawing....................... 114 5 rdering information...................................... 116 Appendix A Abbreviations.......................................... 117 4/123 DocD17478 Rev 9

SP564Bxx-SP56Exx ontents Revision history................................................... 118 DocD17478 Rev 9 5/123 5

List of tables SP564Bxx-SP56Exx List of tables Table 1. Device summary.......................................................... 2 Table 2. SP564Bxx and SP56Exx family comparison................................ 10 Table 3. SP564Bxx and SP56Exx series block summary............................. 13 Table 4. System pin descriptions................................................... 18 Table 5. Functional port pin descriptions............................................. 19 Table 6. Parameter classifications.................................................. 51 Table 7. PAD3V5V(0) field description............................................... 52 Table 8. PAD3V5V(1) field description............................................... 52 Table 9. Absolute maximum ratings................................................. 52 Table 10. Recommended operating conditions (3.3 V)................................... 54 Table 11. Recommended operating conditions (5.0 V)................................... 55 Table 12. LQFP thermal characteristics............................................... 57 Table 13. LBGA256 thermal characteristics............................................ 57 Table 14. input D electrical characteristics......................................... 59 Table 15. pull-up/pull-down D electrical characteristics............................... 60 Table 16. SLW configuration output buffer electrical characteristics........................ 60 Table 17. MEDUM configuration output buffer electrical characteristics...................... 61 Table 18. FAST configuration output buffer electrical characteristics......................... 62 Table 19. utput pin transition times................................................. 62 Table 20. supplies............................................................. 63 Table 21. consumption......................................................... 64 Table 22. Reset electrical characteristics.............................................. 66 Table 23. Voltage regulator electrical characteristics..................................... 68 Table 24. Low voltage monitor electrical characteristics................................... 70 Table 25. Low voltage power domain electrical characteristics............................. 71 Table 26. ode flash memoryprogram and erase specifications.......................... 72 Table 27. Data flash memoryprogram and erase specifications........................... 73 Table 28. Flash memory module life.................................................. 73 Table 29. Flash memory read access timing........................................... 74 Table 30. Flash memory power supply D electrical characteristics......................... 74 Table 31. Start-up time/switch-off time................................................ 75 Table 32. EM radiated emission measurement......................................... 76 Table 33. ESD absolute maximum ratings............................................. 76 Table 34. Latch-up results......................................................... 77 Table 35. rystal description....................................................... 78 Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics................ 79 Table 37. rystal motional characteristics............................................. 81 Table 38. Slow external crystal oscillator (32 khz) electrical characteristics................... 82 Table 39. FMPLL electrical characteristics............................................. 83 Table 40. Fast internal R oscillator (16 MHz) electrical characteristics...................... 83 Table 41. Slow internal R oscillator (128 khz) electrical characteristics..................... 85 Table 42. AD input leakage current................................................. 91 Table 43. AD conversion characteristics (10-bit AD_0)................................. 91 Table 44. onversion characteristics (12-bit AD_1)..................................... 94 Table 45. M Receive Signal Timing................................................. 96 Table 46. M transmit signal timing.................................................. 97 Table 47. M Async nputs Signal Timing............................................. 97 Table 48. M serial management channel timing........................................ 98 6/123 DocD17478 Rev 9

SP564Bxx-SP56Exx List of tables Table 49. n-chip peripherals current consumption...................................... 99 Table 50. DSP timing............................................................ 100 Table 51. Nexus debug port timing.................................................. 106 Table 52. JTAG characteristics..................................................... 108 Table 53. LQFP176 mechanical data................................................ 111 Table 54. LQFP208 mechanical data................................................ 113 Table 55. LBGA256 mechanical data................................................ 115 Table 56. Abbreviations.......................................................... 117 Table 57. Revision history........................................................ 118 DocD17478 Rev 9 7/123 7

List of figures SP564Bxx-SP56Exx List of figures Figure 1. SP564Bxx and SP56Exx block diagram................................... 12 Figure 2. 176-pin LQFP configuration................................................ 15 Figure 3. 208-pin LQFP configuration................................................ 16 Figure 4. 256-pin BGA configuration................................................. 17 Figure 5. input D electrical characteristics definition................................. 59 Figure 6. Start-up reset requirements................................................ 65 Figure 7. Noise filtering on reset signal............................................... 65 Figure 8. Voltage regulator capacitance connection..................................... 67 Figure 9. Low voltage monitor vs. Reset.............................................. 70 Figure 10. rystal oscillator and resonator connection scheme............................. 78 Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics................ 79 Figure 12. rystal oscillator and resonator connection scheme............................. 80 Figure 13. Equivalent circuit of a quartz crystal.......................................... 81 Figure 14. Slow external crystal oscillator (32 khz) electrical characteristics................... 82 Figure 15. AD_0 characteristic and error definitions..................................... 86 Figure 16. nput equivalent circuit (precise channels)..................................... 87 Figure 17. nput equivalent circuit (extended channels)................................... 88 Figure 18. Transient behavior during sampling phase..................................... 88 Figure 19. Spectral representation of input signal........................................ 90 Figure 20. AD_1 characteristic and error definitions..................................... 93 Figure 21. M receive signal timing diagram............................................ 96 Figure 22. M transmit signal timing diagram........................................... 97 Figure 23. M async inputs timing diagram............................................. 98 Figure 24. M serial management channel timing diagram................................. 98 Figure 25. DSP classic SP timing master, PHA = 0................................... 102 Figure 26. DSP classic SP timing master, PHA = 1................................... 102 Figure 27. DSP classic SP timing slave, PHA = 0.................................... 103 Figure 28. DSP classic SP timing slave, PHA = 1.................................... 103 Figure 29. DSP modified transfer format timing master, PHA = 0......................... 104 Figure 30. DSP modified transfer format timing master, PHA = 1......................... 104 Figure 31. DSP modified transfer format timing slave, PHA = 0.......................... 105 Figure 32. DSP modified transfer format timing slave, PHA = 1.......................... 105 Figure 33. DSP PS strobe (PSS) timing........................................... 106 Figure 34. Nexus output timing..................................................... 107 Figure 35. Nexus TD, TMS, TD timing.............................................. 108 Figure 36. Timing diagram - JTAG boundary scan...................................... 109 Figure 37. LQFP176 package mechanical drawing...................................... 110 Figure 38. LQFP208 mechanical drawing............................................. 112 Figure 39. LBGA256 mechanical drawing............................................. 114 Figure 40. rdering information scheme.............................................. 116 8/123 DocD17478 Rev 9

SP564Bxx-SP56Exx ntroduction 1 ntroduction 1.1 Document verview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the SP564Bxx and SP56Exx device. To ensure a complete understanding of the device functionality, refer also to the SP564Bxx and SP56Exx Reference Manual. 1.2 Description The SP564Bxx and SP56Exx is a new family of next generation microcontrollers built on the Power Architecture embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. The SP564Bxx and SP56Exx family expands the range of the SP560B microcontroller family. t provides the scalability needed to implement platform approaches and delivers the performance required by increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the SP564Bxx and SP56Exx automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original Power Architecture user instruction set architecture (USA). t operates at speeds of up to 120 MHz and offers high performance processing optimized for low power consumption. t also capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. DocD17478 Rev 9 9/123 122

10/123 DocD17478 Rev 9 Table 2. SP564Bxx and SP56Exx family comparison (1) Feature SP564B64 SP56E64 SP564B70 SP56E70 SP564B74 SP56E74 Package LQFP 176 LQFP 208 LQFP 176 LQFP 208 LBGA 256 LQFP 176 PU e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h Execution speed (2) Up to 120 MHz (e200z4d) Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h) (3) LQFP 208 Up to 120 MHz (e200z4d) LQFP 176 LQFP 208 Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h) (3) LBGA 256 LQFP 176 LQFP 208 Up to 120 MHz (e200z4d) ode flash memory 1.5 MB 2 MB 3 MB Data flash memory 4 x16 KB LQFP 176 LQFP 208 Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h) (3) SRAM 128 KB 192 KB 160 KB 256 KB 192 KB 256 KB MPU edma (4) 10-bit AD 12-bit AD TU dedicated (5), (6) shared with 12-bit AD (7) dedicated (8) shared with 10-bit AD (7) Total timer (9) ems 16-entry 32 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 19 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 19 ch 64 ch 64 ch, 16-bit S (LNFlexD) 10 SP (DSP) 8 AN (FlexAN) (10) 6 LBGA 256 ntroduction SP564Bxx-SP56Exx

DocD17478 Rev 9 11/123 FlexRay STU (11) Ethernet No Yes No Yes No Yes 2 1 32 khz oscillator (SXS) Yes GP (12) 147 177 147 177 199 147 177 147 177 199 147 177 147 177 199 Debug ryptographic Services Engine (SE) Table 2. SP564Bxx and SP56Exx family comparison (1) (continued) Feature SP564B64 SP56E64 SP564B70 SP56E70 SP564B74 SP56E74 Package LQFP 176 LQFP 208 JTAG LQFP 176 LQFP 208 LBGA 256 Nexus 3+ LQFP 176 JTAG Yes Yes ptional 1. Feature set dependent on selected peripheral multiplexing; table shows example. 2. Based on 125 ambient operating temperature and subject to full device characterization. 3. The e200z0h can run at speeds up to 80 MHz. However, if system frequency is >80 MHz (e.g., e200z4d running at 120 MHz) the e200z0h needs to run at 1/2 system frequency. There is a configurable e200z0 system clock divider for this purpose. 4. DMAMUX also included that allows for software selection of 32 out of a possible 57 sources. 5. Not shared with 12-bit AD, but possibly shared with other alternate functions. 6. There are 23 dedicated ANS plus 4 dedicated ANX channels on LQPF176. For higher pin count packages, there are 29 dedicated ANS plus 4 dedicated ANX channels. 7. 16x precision channels (ANP) and 3x standard (ANS). 8. Not shared with 10-bit AD, but possibly shared with other alternate functions. 9. As a minimum, all timer channels can function as PWM or nput apture and utput ontrol. Refer to the ems section of the device reference manual for information on the channel configuration and functions. 10. AN Sampler also included that allows D of AN message to be captured when in low power mode. 11. STU controls MBST activation and reporting. 12. Estimated count for proposed packages based on multiplexing with peripherals. LQFP 208 LQFP 176 LQFP 208 LBGA 256 Nexus 3+ LQFP 176 LQFP 208 JTAG LQFP 176 LQFP 208 LBGA 256 Nexus 3+ SP564Bxx-SP56Exx ntroduction

ntroduction SP564Bxx-SP56Exx 1.3 Block diagram Figure 1 shows the detailed block diagram of the SP564Bxx and SP56Exx. Figure 1. SP564Bxx and SP56Exx block diagram JTAG Port Nexus Port Voltage regulator Nexus JTAG NM0 NM1 Nexus 3+ e200z0h e200z4d FE SE FlexRay nstructions (Master) Data (Master) nstructions (Master) Data (Master) 64-bit 8 x 5 crossbar switch MPU SRAM 2 128 KB ode Flash 2 1.5 MB Data Flash 64 KB 2 SRAM Flash memory controller controller (Slave) NM0 Nexus 3+ (Slave) NM1 locks FMPLL nterrupt requests from peripheral blocks MU NT MPU registers edma (Master) (Slave) DMAMUX AN Sampler STU 16 x Semaphores RT/AP 4 STM SWT ESM 8 PT RT M_RGM M_GM M_ME M_PU BAM SSM WKP Peripheral Bridge nterrupt Request SUL Reset ontrol External nterrupt Request MUX 10 ch (1) 1 12-bit AD 27 ch or 33 ch (2) 1 10-bit AD TU 2 32 ch ems 10 LNFlexD 8 DSP 2 6 FlexAN GP & Pad ontrol (3) (3) Legend: AD Analog-to-Digital onverter JTAG JTAG controller BAM Boot Assist Module LNFlexD Local nterconnect Network Flexible with DMA sup SE ryptographic Services Engine M_ME Mode Entry Module AN ontroller Area Network (FlexAN) M_GM lock Generation Module MU lock Monitor Unit M_PU Power ontrol Unit TU ross Triggering Unit M_RGM Reset Generation Module DMAMUX DMA hannel Multiplexer MPU Memory Protection Unit DSP Deserial Serial Peripheral nterface Nexus Nexus Development nterface edma enhanced Direct Memory Access NM Non-Maskable nterrupt FlexAN ontroller Area Network controller modules PT_RT Periodic nterrupt Timer with Real-Time nterrupt FE Fast Ethernet ontroller RT/AP Real-Time lock/ Autonomous Periodic nterrupt ems Enhanced Modular nput utput System SUL System ntegration Unit Lite ESM Error orrection Status Module SRAM Static Random-Access Memory FMPLL Frequency-Modulated Phase-Locked Loop SSM System Status onfiguration Module FlexRay FlexRay ommunication ontroller STM System Timer Module 2 nter-integrated ircuit Bus SWT Software Watchdog Timer MUX nternal Multiplexer STU Self Test ontrol Unit NT nterrupt ontroller WKPU Wakeup Unit Notes: 1) 10 dedicated channels plus up to 19 shared channels. See the device-comparison table. 2) Package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. See the device-comparison table. 3) 16 x precision channels (ANP) are mapped on input only cells. 12/123 DocD17478 Rev 9

SP564Bxx-SP56Exx ntroduction Table 3 summarizes the functions of the blocks present on the SP564Bxx and SP56Exx. Table 3. SP564Bxx and SP56Exx series block summary Block Function Analog-to-digital converter (AD) Boot assist module (BAM) lock monitor unit (MU) ross triggering unit (TU) ryptographic Security Engine (SE) rossbar (XBAR) switch DMA hannel Multiplexer (DMAMUX) Deserial serial peripheral interface (DSP) Error orrection Status Module (ESM) Enhanced Direct Memory Access (edma) Enhanced modular input output system (ems) Flash memory FlexAN (controller area network) FMPLL (frequency-modulated phase-locked loop) FlexRay (FlexRay communication controller) Fast Ethernet ontroller (FE) nternal multiplexer (MUX) SUL subblock nter-integrated circuit ( 2 ) bus nterrupt controller (NT) JTAG controller onverts analog voltages to digital values A block of read-only memory containing VLE code which is executed according to the boot mode of the device Monitors clock source (internal and external) integrity Enables synchronization of AD conversions with a timer event from the ems or from the PT Supports the encoding and decoding of any kind of data Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width Allows to route DMA sources (called slots) to DMA channels Provides a synchronous serial interface for communication with external devices Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Performs complex data transfers with minimal intervention from a host processor via n programmable channels. Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables Supports the standard AN communications protocol Generates high-speed system clocks and supports programmable frequency modulation Provides high-speed distributed control for advanced automotive applications Ethernet Media Access ontroller (MA) designed to support both 10 and 100 Mbps Ethernet/EEE 802.3 networks Allows flexible mapping of peripheral interface on the different pins of the device A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Provides priority-based preemptive scheduling of interrupt requests for both e200z0h and e200z4d cores Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode DocD17478 Rev 9 13/123 122

ntroduction SP564Bxx-SP56Exx Table 3. SP564Bxx and SP56Exx series block summary (continued) LinFlexD (Local nterconnect Network Flexible with DMA support) Memory protection unit (MPU) lock generation module (M_GM) Power control unit (M_PU) Reset generation module (M_RGM) Mode entry module (M_ME) Non-Maskable nterrupt (NM) Nexus Development nterface (ND) Periodic interrupt timer/ Real Time nterrupt Timer (PT_RT) Real-time counter (RT/AP) Static random-access memory (SRAM) System integration unit lite (SUL) System status and configuration module (SSM) System timer module (STM) Semaphores Block Wake Unit (WKPU) Function Manages a high number of LN (Local nterconnect Network protocol) messages efficiently with a minimum of PU load Provides hardware access control for all memory references generated in a device Provides logic and control required for the generation of system and peripheral clocks Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called power domains which are controlled by the PU entralizes reset sources and manages the device reset sequence of the device Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Handles external events that must produce an immediate response, such as power down detection Provides real-time development capabilities for e200z0h and e200z4d core processor Produces periodic interrupts and triggers A free running counter used for time keeping applications, the RT can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode). Supports autonomous periodic interrupt (AP) function to generate a periodic wakeup request to exit a low power mode or an interrupt request Provides storage for program code, constants, and variables Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable Provides a set of output compare events to support AutoSAR and operating system tasks Provides the hardware support needed in multi-core systems for sharing resources and provides a simple mechanism to achieve lock/unlock operations via a single write access. Supports external sources that can generate interrupts or wakeup events, of which can cause non-maskable interrupt requests or wakeup events. 14/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions 2 Package pinouts and signal descriptions The available LQFP pinouts and the LBGA ballmaps are provided in the following figures. For functional port pin description, see Table 6. Figure 2. 176-pin LQFP configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 LQFP176 Top view 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 PB[2] P[8] P[13] P[12] P[0] P[1] P[2] P[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] P[4] P[5] PE[3] PE[2] PH[9] P[0] VSS_LV VDD_LV VDD_HV_A VSS_HV P[1] PH[10] PA[6] PA[5] P[2] P[3] P[4] P[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] PB[3] P[9] P[14] P[15] PJ[4] VDD_HV_A VSS_HV PH[15] PH[13] PH[14] P[6] P[7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV_A VSS_HV RESET VSS_LV VDD_LV VR_TRL PG[9] PG[8] P[11] P[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] P[6] 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV_B VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] P[13] P[12] P[11] VDD_LV VSS_LV P[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] VDD_HV_AD1 VSS_HV_AD1 PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_AD0 VSS_HV_AD0 NTE 1) VDD_HV_B supplies the voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. 2)Availability of port pin alternate functions depends on product selection. P[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV_A PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] P[15] P[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV_A VSS_HV PD[8] PB[4] DocD17478 Rev 9 15/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Figure 3. 208-pin LQFP configuration PB[3] P[9] P[14] P[15] PJ[4] VDD_HV_A VSS_HV PH[15] PH[13] PH[14] P[6] P[7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV_A VSS_HV RESET VSS_LV VDD_LV VR_TRL PG[9] PG[8] P[11] P[10] PG[7] PG[6] PB[0] PB[1] PK[1] PK[2] PK[3] PK[4] PK[5] PK[6] PK[7] PK[8] PF[9] PF[8] PF[12] P[6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 LQFP208 Top view 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV_B VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] P[13] P[12] P[11] P[10] VDD_LV VSS_LV P[9] P[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] VDD_HV_A VSS_HV PD[12] VDD_HV_AD1 VSS_HV_AD1 PB[11] PD[11] PD[10] PD[9] PJ[5] PJ[6] PJ[7] PJ[8] PB[7] PB[6] PB[5] VDD_HV_AD0 VSS_HV_AD0 P[7] PF[10] PF[11] PA[15] PF[13] PA[14] PJ[12] PJ[11] PA[4] PK[0] PJ[15] PJ[14] PJ[13] PA[13] PJ[10] PJ[9] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV_A PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] P[15] P[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV_A VSS_HV PD[8] PB[4] PB[2] P[8] P[13] P[12] PL[0] PK[15] PK[14] PK[13] PK[12] PK[11] PK[10] PK[9] P[0] P[1] P[2] P[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] P[4] P[5] PE[3] PE[2] PH[9] P[0] VSS_LV VDD_LV VDD_HV_A VSS_HV P[1] PH[10] PA[6] PA[5] P[2] P[3] P[4] P[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] NTE 1) VDD_HV_B supplies the voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. 2) Availability of port pin alternate functions depends on product selection. 16/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A P[15] PB[2] P[13] P[1] PE[7] PH[8] PE[2] PE[4] P[4] PE[3] PH[9] P[4] PH[11] PE[14] PA[10] PG[11] A B PH[13] P[14] P[8] P[12] P[3] PE[6] PH[5] PE[5] P[5] P[0] P[2] PH[12] PG[10] PA[11] PA[9] PA[8] B PH[14] VDD_HV _A P[9] PL[0] P[0] PH[7] PH[6] VSS_LV VDD_HV _A PA[5] P[3] PE[15] PG[14] PE[12] PA[7] PE[13] D PG[5] P[6] PJ[4] PB[3] PK[15] P[2] PH[4] VDD_LV P[1] PH[10] PA[6] P[5] PG[15] PF[14] PF[15] PH[2] D E PG[3] P[7] PH[15] PG[2] VDD_LV VSS_LV PK[10] PK[9] PM[1] PM[0] PL[15] PL[14] PG[0] PG[1] PH[0] VDD_HV _A E F PA[2] PG[4] PA[1] PE[1] PL[2] PM[6] PL[1] PK[11] PM[5] PL[13] PL[12] PM[2] PH[1] PH[3] PG[12] PG[13] F G PE[8] PE[0] PE[10] PA[0] PL[3] VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV PK[12] VDD_HV _B P[13] P[12] PA[3] G H PE[9] VDD_HV _A PE[11] PK[1] PL[4] VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV VSS_HV PK[13] VDD_HV _A VDD_LV VSS_LV P[11] H J VSS_HV VR_T RL VDD_LV PG[9] PL[5] VSS_LV VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV PK[14] PD[15] P[8] P[9] P[10] J K RESET VSS_LV PG[8] P[11] PL[6] VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV PM[3] PD[14] PD[13] PB[14] PB[15] K L P[10] PG[7] PB[0] PK[2] PL[7] VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV PM[4] PD[12] PB[12] PB[13] VDD_HV _AD1 L M PG[6] PB[1] PK[4] PF[9] PK[5] PK[6] PK[7] PK[8] PL[8] PL[9] PL[10] PL[11] PB[11] PD[10] PD[11] VSS_HV _AD1 M N PK[3] PF[8] P[6] P[7] PJ[13] VDD_HV _A PB[10] PF[6] VDD_HV _A PJ[1] PD[2] PJ[5] PB[5] PB[6] PJ[6] PD[9] N P PF[12] PF[10] PF[13] PA[14] PJ[9] PA[12] PF[0] PF[5] PF[7] PJ[3] P[15] PD[4] PD[7] PD[8] PJ[8] PJ[7] P R PF[11] PA[15] PJ[11] PJ[15] PA[13] PF[2] PF[3] PF[4] VDD_LV PJ[2] PJ[0] PD[0] PD[3] PD[6] VDD_HV _AD0 PB[7] R T PJ[12] PA[4] PK[0] PJ[14] PJ[10] PF[1] XTAL EXTAL VSS_LV PB[9] PB[8] P[14] PD[1] PD[5] VSS_HV _AD0 PB[4] T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Notes: 1) VDD_HV_B supplies the voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], PA[3], PM[3], and PM[4]. 2)Availability of port pin alternate functions depends on product selection. Figure 4. 256-pin BGA configuration DocD17478 Rev 9 17/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx 2.1 Pad types n the device the following types of pads are available for system pins and functional port pins: S = Slow (a) M = Medium (a),(b) F = Fast (a),(b) = nput only with analog feature (a) A = Analog 2.2 System pins The system pins are listed in Table 4. Table 4. System pin descriptions Pin number Port pin Function direction Pad type RESET config. LQFP 176 LQFP 208 LBGA 256 RESET EXTAL XTAL Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator bypass mode is used. Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. Analog input for the clock generator when the oscillator is in bypass mode. M nput, weak pull-up only after PHASE2 29 29 K1 A (1) 58 74 T8 A (1) 56 72 T7 1. For analog pads, it is not recommended to enable BE if AP is enabled to avoid extra current in middle range voltage. a. See the pad electrical characteristics in the device datasheet for details. b. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. For example, Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by default. nly exception is P[1] which is in medium configuration by default (refer to PR.SR in the reference manual, Pad onfiguration Registers (PR0PR198)). 18/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions 2.3 Functional ports The functional port pins are listed in Table 5. Table 5. Functional port pin descriptions Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PA[0] PR[0] GP[0] E0U[0] LKUT E0U[13] WKPU[19] AN1RX SUL ems_0 M_GM ems_0 WKPU FlexAN_1 M/S Tristate 24 24 G4 PA[1] PR[1] GP[1] E0U[1] WKPU[2] AN3RX NM[0] (3) SUL ems_0 WKPU FlexAN_3 WKPU S Tristate 19 19 F3 PA[2] PR[2] GP[2] E0U[2] MA[2] WKPU[3] NM[1] (3) SUL ems_0 AD_0 WKPU WKPU S Tristate 17 17 F1 PA[3] PR[3] GP[3] E0U[3] LN5TX S4_1 RX_ER_LK ERQ[0] AD1_S[0] SUL ems_0 LNFlexD_5 DSP_1 FE SUL AD_1 M/S Tristate 114 138 G16 PA[4] PR[4] GP[4] E0U[4] S0_1 LN5RX WKPU[9] SUL ems_0 DSP_1 LNFlexD_5 WKPU S Tristate 51 61 T2 DocD17478 Rev 9 19/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PA[5] PR[5] GP[5] E0U[5] LN4TX SUL ems_0 LNFlexD_4 M/S Tristate 146 170 10 PA[6] PR[6] GP[6] E0U[6] S1_1 LN4RX ERQ[1] SUL ems_0 DSP_1 LNFlexD_4 SUL S Tristate 147 171 D11 PA[7] PR[7] GP[7] E0U[7] LN3TX RXD[2] ERQ[2] AD1_S[1] SUL ems_0 LNFlexD_3 FE SUL AD_1 M/S Tristate 128 152 15 PA[8] PR[8] GP[8] E0U[8] E0U[14] RXD[1] ERQ[3] ABS[0] LN3RX SUL ems_0 ems_0 FE SUL M_RGM LNFlexD_3 M/S nput, weak pull-up 129 153 B16 PA[9] PR[9] GP[9] E0U[9] S2_1 RXD[0] FAB SUL ems_0 DSP1 FE M_RGM M/S Pulldown 130 154 B15 20/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PA[10] PR[10] GP[10] E0U[10] SDA LN2TX L AD1_S[2] SN_1 SUL ems_0 2 LNFlexD_2 FE AD_1 DSP_1 M/S Tristate 131 155 A15 PA[11] PR[11] GP[11] E0U[11] SL RX_ER ERQ[16] LN2RX AD1_S[3] SUL ems_0 2 FE SUL LNFlexD_2 AD_1 M/S Tristate 132 156 B14 PA[12] PR[12] GP[12] E0U[28] S3_1 ERQ[17] SN_0 SUL ems_0 DSP1 SUL DSP_0 S Tristate 53 69 P6 PA[13] PR[13] GP[13] SUT_0 E0U[29] SUL DSP_0 ems_0 M/S Tristate 52 66 R5 PA[14] PR[14] GP[14] SK_0 S0_0 E0U[0] ERQ[4] SUL DSP_0 DSP_0 ems_0 SUL M/S Tristate 50 58 P4 PA[15] PR[15] GP[15] S0_0 SK_0 E0U[1] WKPU[10] SUL DSP_0 DSP_0 ems_0 WKPU M/S Tristate 48 56 R2 DocD17478 Rev 9 21/123 122

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PB[6] PR[22] GP[22] AD0_P[2] AD1_P[2] SUL AD_0 AD_1 Tristate 92 108 N14 PB[7] PR[23] GP[23] AD0_P[3] AD1_P[3] SUL AD_0 AD_1 Tristate 93 109 R16 PB[8] PR[24] GP[24] AD0_S[0] AD1_S[4] WKPU[25] S32k_XTAL (4) SUL AD_0 AD_1 WKPU SXS 61 77 T11 PB[9] (5) PR[25] GP[25] AD0_S[1] AD1_S[5] WKPU[26] S32k_EXTAL ( 4) SUL AD_0 AD_1 WKPU SXS 60 76 T10 PB[10] PR[26] GP[26] SUT_1 AN3TX AD0_S[2] AD1_S[6] WKPU[8] SUL DSP_1 FlexAN_3 AD_0 AD_1 WKPU S Tristate 62 78 N7 DocD17478 Rev 9 23/123 122

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 P[2] PR[34] GP[34] SK_1 AN4TX ERQ[5] SUL DSP_1 FlexAN_4 SUL M/S Tristate 145 169 B11 P[3] PR[35] GP[35] S0_1 MA[0] AN1RX AN4RX ERQ[6] SUL DSP_1 AD_0 FlexAN_1 FlexAN_4 SUL S Tristate 144 168 11 P[4] PR[36] ALT4 GP[36] E1U[31] FR_B_TX_EN SN_1 AN3RX ERQ[18] SUL ems_1 Flexray DSP_1 FlexAN_3 SUL M/S Tristate 159 183 A9 P[5] PR[37] ALT4 GP[37] SUT_1 AN3TX FR_A_TX ERQ[7] SUL DSP_1 FlexAN_3 Flexray SUL M/S Tristate 158 182 B9 P[6] PR[38] GP[38] LN1TX E1U[28] SUL LNFlexD_1 ems_1 S Tristate 44 52 N3 P[7] PR[39] GP[39] E1U[29] LN1RX WKPU[12] SUL ems_1 LNFlexD_1 WKPU S Tristate 45 53 N4 DocD17478 Rev 9 25/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 P[8] PR[40] GP[40] LN2TX E0U[3] SUL LNFlexD_2 ems_0 S Tristate 175 207 B3 P[9] PR[41] GP[41] E0U[7] LN2RX WKPU[13] SUL ems_0 LNFlexD_2 WKPU S Tristate 2 2 3 P[10] PR[42] GP[42] AN1TX AN4TX MA[1] SUL FlexAN_1 FlexAN_4 AD_0 M/S Tristate 36 36 L1 P[11] PR[43] GP[43] MA[2] AN1RX AN4RX WKPU[5] SUL AD_0 FlexAN_1 FlexAN_4 WKPU S Tristate 35 35 K4 P[12] PR[44] ALT4 GP[44] E0U[12] FR_DBG[0] SN_2 ERQ[19] SUL ems_0 Flexray DSP_2 SUL M/S Tristate 173 205 B4 P[13] PR[45] ALT4 GP[45] E0U[13] SUT_2 FR_DBG[1] SUL ems_0 DSP_2 Flexray M/S Tristate 174 206 A3 26/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 P[14] PR[46] ALT4 GP[46] E0U[14] SK_2 FR_DBG[2] ERQ[8] SUL ems_0 DSP_2 Flexray SUL M/S Tristate 3 3 B2 P[15] PR[47] ALT4 GP[47] E0U[15] S0_2 FR_DBG[3] ERQ[20] SUL ems_0 DSP_2 Flexray SUL M/S Tristate 4 4 A1 PD[0] PR[48] GP[48] AD0_P[4] AD1_P[4] WKPU[27] SUL AD_0 AD_1 WKPU Tristate 77 93 R12 PD[1] PR[49] GP[49] AD0_P[5] AD1_P[5] WKPU[28] SUL AD_0 AD_1 WKPU Tristate 78 94 T13 PD[2] PR[50] GP[50] AD0_P[6] AD1_P[6] SUL AD_0 AD_1 Tristate 79 95 N11 DocD17478 Rev 9 27/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PD[3] PR[51] GP[51] AD0_P[7] AD1_P[7] SUL AD_0 AD_1 Tristate 80 96 R13 PD[4] PR[52] GP[52] AD0_P[8] AD1_P[8] SUL AD_0 AD_1 Tristate 81 97 P12 PD[5] PR[53] GP[53] AD0_P[9] AD1_P[9] SUL AD_0 AD_1 Tristate 82 98 T14 PD[6] PR[54] GP[54] AD0_P[10] AD1_P[10] SUL AD_0 AD_1 Tristate 83 99 R14 PD[7] PR[55] GP[55] AD0_P[11] AD1_P[11] SUL AD_0 AD_1 Tristate 84 100 P13 PD[8] PR[56] GP[56] AD0_P[12] AD1_P[12] SUL AD_0 AD_1 Tristate 87 103 P14 28/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PD[9] PR[57] GP[57] AD0_P[13] AD1_P[13] SUL AD_0 AD_1 Tristate 94 114 N16 PD[10] PR[58] GP[58] AD0_P[14] AD1_P[14] SUL AD_0 AD_1 Tristate 95 115 M14 PD[11] PR[59] GP[59] AD0_P[15] AD1_P[15] SUL AD_0 AD_1 Tristate 96 116 M15 PD[12] PR[60] GP[60] S5_0 E0U[24] AD0_S[4] SUL DSP_0 ems_0 AD_0 S Tristate 100 120 L13 PD[13] PR[61] GP[61] S0_1 E0U[25] AD0_S[5] SUL DSP_1 ems_0 AD_0 S Tristate 102 124 K14 PD[14] PR[62] ALT4 GP[62] S1_1 E0U[26] FR_DBG[0] AD0_S[6] SUL DSP_1 ems_0 Flexray AD_0 S Tristate 104 126 K13 DocD17478 Rev 9 29/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PD[15] PR[63] ALT4 GP[63] S2_1 E0U[27] FR_DBG[1] AD0_S[7] SUL DSP_1 ems_0 Flexray AD_0 S Tristate 106 128 J13 PE[0] PR[64] GP[64] E0U[16] AN5RX WKPU[6] SUL ems_0 FlexAN_5 WKPU S Tristate 18 18 G2 PE[1] PR[65] GP[65] E0U[17] AN5TX SUL ems_0 FlexAN_5 M/S Tristate 20 20 F4 PE[2] PR[66] ALT4 GP[66] E0U[18] FR_A_TX_EN SN_1 ERQ[21] SUL ems_0 Flexray DSP_1 SUL M/S Tristate 156 180 A7 PE[3] PR[67] GP[67] E0U[19] SUT_1 FR_A_RX WKPU[29] SUL ems_0 DSP_1 Flexray WKPU M/S Tristate 157 181 A10 PE[4] PR[68] ALT4 GP[68] E0U[20] SK_1 FR_B_TX ERQ[9] SUL ems_0 DSP_1 Flexray SUL M/S Tristate 160 184 A8 30/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PE[5] PR[69] GP[69] E0U[21] S0_1 MA[2] FR_B_RX WKPU[30] SUL ems_0 DSP_1 AD_0 Flexray WKPU M/S Tristate 161 185 B8 PE[6] PR[70] GP[70] E0U[22] S3_0 MA[1] ERQ[22] SUL ems_0 DSP_0 AD_0 SUL M/S Tristate 167 191 B6 PE[7] PR[71] GP[71] E0U[23] S2_0 MA[0] ERQ[23] SUL ems_0 DSP_0 AD_0 SUL M/S Tristate 168 192 A5 PE[8] PR[72] GP[72] AN2TX E0U[22] AN3TX SUL FlexAN_2 ems_0 FlexAN_3 M/S Tristate 21 21 G1 PE[9] PR[73] GP[73] E0U[23] WKPU[7] AN2RX AN3RX SUL ems_0 WKPU FlexAN_2 FlexAN_3 S Tristate 22 22 H1 PE[10] PR[74] GP[74] LN3TX S3_1 E1U[30] ERQ[10] SUL LNFlexD_3 DSP_1 ems_1 SUL S Tristate 23 23 G3 DocD17478 Rev 9 31/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PE[11] PR[75] GP[75] E0U[24] S4_1 LN3RX WKPU[14] SUL ems_0 DSP_1 LNFlexD_3 WKPU S Tristate 25 25 H3 PE[12] PR[76] GP[76] E1U[19] RS SN_2 ERQ[11] AD1_S[7] SUL ems_1 FE DSP_2 SUL AD_1 M/S Tristate 133 157 14 PE[13] PR[77] GP[77] SUT_2 E1U[20] RXD[3] SUL DSP_2 ems_1 FE M/S Tristate 127 151 16 PE[14] PR[78] GP[78] SK_2 E1U[21] ERQ[12] SUL DSP_2 ems_1 SUL M/S Tristate 136 160 A14 PE[15] PR[79] GP[79] S0_2 E1U[22] SK_6 SUL DSP_2 ems_1 DSP_6 M/S Tristate 137 161 12 PF[0] PR[80] GP[80] E0U[10] S3_1 AD0_S[8] SUL ems_0 DSP_1 AD_0 S Tristate 63 79 P7 32/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PF[1] PR[81] GP[81] E0U[11] S4_1 AD0_S[9] SUL ems_0 DSP_1 AD_0 S Tristate 64 80 T6 PF[2] PR[82] GP[82] E0U[12] S0_2 AD0_S[10] SUL ems_0 DSP_2 AD_0 S Tristate 65 81 R6 PF[3] PR[83] GP[83] E0U[13] S1_2 AD0_S[11] SUL ems_0 DSP_2 AD_0 S Tristate 66 82 R7 PF[4] PR[84] GP[84] E0U[14] S2_2 AD0_S[12] SUL ems_0 DSP_2 AD_0 S Tristate 67 83 R8 PF[5] PR[85] GP[85] E0U[22] S3_2 AD0_S[13] SUL ems_0 DSP_2 AD_0 S Tristate 68 84 P8 PF[6] PR[86] GP[86] E0U[23] S1_1 AD0_S[14] SUL ems_0 DSP_1 AD_0 S Tristate 69 85 N8 PF[7] PR[87] GP[87] S2_1 AD0_S[15] SUL DSP_1 AD_0 S Tristate 70 86 P9 DocD17478 Rev 9 33/123 122

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PF[14] PR[94] ALT4 GP[94] AN4TX E1U[27] AN1TX MD SUL FlexAN_4 ems_1 FlexAN_1 FE M/S Tristate 126 150 D14 PF[15] PR[95] GP[95] E1U[4] RX_DV AN1RX AN4RX ERQ[13] SUL ems_1 FE FlexAN_1 FlexAN_4 SUL M/S Tristate 125 149 D15 PG[0] PR[96] ALT4 GP[96] AN5TX E1U[23] MD SUL FlexAN_5 ems_1 FE F Tristate 122 146 E13 PG[1] PR[97] GP[97] E1U[24] TX_LK AN5RX ERQ[14] SUL ems_1 FE FlexAN_5 SUL M Tristate 121 145 E14 PG[2] PR[98] GP[98] E1U[11] SUT_3 SUL ems_1 DSP_3 M/S Tristate 16 16 E4 PG[3] PR[99] GP[99] E1U[12] S0_3 WKPU[17] SUL ems_1 DSP_3 WKPU S Tristate 15 15 E1 DocD17478 Rev 9 35/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PG[4] PR[100] GP[100] E1U[13] SK_3 SUL ems_1 DSP_3 M/S Tristate 14 14 F2 PG[5] PR[101] GP[101] E1U[14] WKPU[18] SN_3 SUL ems_1 WKPU DSP_3 S Tristate 13 13 D1 PG[6] PR[102] GP[102] E1U[15] LN6TX SUL ems_1 LNFlexD_6 M/S Tristate 38 38 M1 PG[7] PR[103] GP[103] E1U[16] E1U[30] LN6RX WKPU[20] SUL ems_1 ems_1 LNFlexD_6 WKPU S Tristate 37 37 L2 PG[8] PR[104] GP[104] E1U[17] LN7TX S0_2 ERQ[15] SUL ems_1 LNFlexD_7 DSP_2 SUL S Tristate 34 34 K3 PG[9] PR[105] GP[105] E1U[18] SK_2 LN7RX WKPU[21] SUL ems_1 DSP_2 LNFlexD_7 WKPU S Tristate 33 33 J4 36/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PG[10] PR[106] GP[106] E0U[24] E1U[31] SN_4 SUL ems_0 ems_1 DSP_4 S Tristate 138 162 B13 PG[11] PR[107] GP[107] E0U[25] S0_4 S0_6 SUL ems_0 DSP_4 DSP_6 M/S Tristate 139 163 A16 PG[12] PR[108] ALT4 GP[108] E0U[26] SUT_4 TXD[2] SUL ems_0 DSP_4 FE M/S Tristate 116 140 F15 PG[13] PR[109] ALT4 GP[109] E0U[27] SK_4 TXD[3] SUL ems_0 DSP_4 FE M/S Tristate 115 139 F16 PG[14] PR[110] GP[110] E1U[0] LN8TX SN_6 SUL ems_1 LNFlexD_8 DSP_6 S Tristate 134 158 13 PG[15] PR[111] GP[111] E1U[1] SUT_6 LN8RX SUL ems_1 DSP_6 LNFlexD_8 M/S Tristate 135 159 D13 PH[0] PR[112] ALT4 GP[112] E1U[2] TXD[1] SN_1 SUL ems_1 FE DSP_1 M/S Tristate 117 141 E15 DocD17478 Rev 9 37/123 122

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PH[8] PR[120] GP[120] E1U[10] S2_2 MA[0] SUL ems_1 DSP_2 AD_0 M/S Tristate 166 190 A6 PH[9] (6) PR[121] GP[121] TK SUL JTAG S nput, weak pull-up 155 179 A11 PH[10] (6) PR[122] GP[122] TMS SUL JTAG M/S nput, weak pull-up 148 172 D10 PH[11] PR[123] GP[123] SUT_3 S0_4 E1U[5] SUL DSP_3 DSP_4 ems_1 M/S Tristate 140 164 A13 PH[12] PR[124] GP[124] SK_3 S1_4 E1U[25] SUL DSP_3 DSP_4 ems_1 M/S Tristate 141 165 B12 PH[13] PR[125] GP[125] SUT_4 S0_3 E1U[26] SUL DSP_4 DSP_3 ems_1 M/S Tristate 9 9 B1 PH[14] PR[126] GP[126] SK_4 S1_3 E1U[27] SUL DSP_4 DSP_3 ems_1 M/S Tristate 10 10 1 PH[15] PR[127] GP[127] SUT_5 E1U[17] SUL DSP_5 ems_1 M/S Tristate 8 8 E3 DocD17478 Rev 9 39/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 P[0] PR[128] GP[128] E0U[28] LN8TX SUL ems_0 LNFlexD_8 S Tristate 172 196 5 P[1] PR[129] GP[129] E0U[29] WKPU[24] LN8RX SUL ems_0 WKPU LNFlexD_8 S Tristate 171 195 A4 P[2] PR[130] GP[130] E0U[30] LN9TX SUL ems_0 LNFlexD_9 S Tristate 170 194 D6 P[3] PR[131] GP[131] E0U[31] WKPU[23] LN9RX SUL ems_0 WKPU LNFlexD_9 S Tristate 169 193 B5 P[4] PR[132] GP[132] E1U[28] SUT_4 SUL ems_1 DSP_4 M/S Tristate 143 167 A12 P[5] PR[133] ALT4 GP[133] E1U[29] SK_4 S2_5 S2_6 SUL ems_1 DSP_4 DSP_5 DSP_6 M/S Tristate 142 166 D12 P[6] PR[134] ALT4 GP[134] E1U[30] S0_4 S0_5 S0_6 SUL ems_1 DSP_4 DSP_5 DSP_6 S Tristate 11 11 D2 40/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 P[7] PR[135] ALT4 GP[135] E1U[31] S1_4 S1_5 S1_6 SUL ems_1 DSP_4 DSP_5 DSP_6 S Tristate 12 12 E2 P[8] PR[136] GP[136] AD0_S[16] SUL AD_0 S Tristate 108 130 J14 P[9] PR[137] GP[137] AD0_S[17] SUL AD_0 S Tristate 131 J15 P[10] PR[138] GP[138] AD0_S[18] SUL AD_0 S Tristate 134 J16 P[11] PR[139] GP[139] AD0_S[19] SN_3 SUL AD_0 DSP_3 S Tristate 111 135 H16 P[12] PR[140] GP[140] S0_3 S0_2 AD0_S[20] SUL DSP_3 DSP_2 AD_0 S Tristate 112 136 G15 DocD17478 Rev 9 41/123 122

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PJ[3] PR[147] GP[147] S1_5 S1_6 S1_7 AD0_S[27] SUL DSP_5 DSP_6 DSP_7 AD_0 S Tristate 71 87 P10 PJ[4] PR[148] GP[148] SK_5 E1U[18] SUL DSP_5 ems_1 M/S Tristate 5 5 D3 PJ[5] PR[149] GP[149] AD0_S[28] SUL AD_0 S Tristate 113 N12 PJ[6] PR[150] GP[150] AD0_S[29] SUL AD_0 S Tristate 112 N15 PJ[7] PR[151] GP[151] AD0_S[30] SUL AD_0 S Tristate 111 P16 PJ[8] PR[152] GP[152] AD0_S[31] SUL AD_0 S Tristate 110 P15 PJ[9] PR[153] GP[153] AD1_S[8] SUL AD_1 S Tristate 68 P5 DocD17478 Rev 9 43/123 122

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PK[0] PR[160] GP[160] AN1TX S2_6 SUL FlexAN_1 DSP_6 M/S Tristate 62 T3 PK[1] PR[161] GP[161] S3_6 AN4RX SUL DSP_6 FlexAN_4 M/S Tristate 41 H4 PK[2] PR[162] GP[162] AN4TX SUL FlexAN_4 M/S Tristate 42 L4 PK[3] PR[163] GP[163] E1U[0] AN5RX LN8RX SUL ems_1 FlexAN_5 LNFlexD_8 M/S Tristate 43 N1 PK[4] PR[164] GP[164] LN8TX AN5TX E1U[1] SUL LNFlexD_8 FlexAN_5 ems_1 M/S Tristate 44 M3 PK[5] PR[165] GP[165] AN2RX LN2RX SUL FlexAN_2 LNFlexD_2 M/S Tristate 45 M5 PK[6] PR[166] GP[166] AN2TX LN2TX SUL FlexAN_2 LNFlexD_2 M/S Tristate 46 M6 DocD17478 Rev 9 45/123 122

SP564Bxx-SP56Exx Package pinouts and signal descriptions Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PK[14] PR[174] GP[174] AN3TX S3_7 S0_1 SUL FlexAN_3 DSP_7 DSP_1 M/S Tristate 202 J12 PK[15] PR[175] GP[175] SN_1 SN_7 SUL DSP_1 DSP_7 M/S Tristate 203 D5 PL[0] PR[176] GP[176] SUT_1 SUT_7 SUL DSP_1 DSP_7 M/S Tristate 204 4 PL[1] PR[177] GP[177] SUL M/S Tristate F7 PL[2] PR[178] (7) GP[178] MD0 (8) SUL Nexus M/S Tristate F5 PL[3] PR[179] GP[179] MD1 SUL Nexus M/S Tristate G5 PL[4] PR[180] GP[180] MD2 SUL Nexus M/S Tristate H5 PL[5] PR[181] GP[181] MD3 SUL Nexus M/S Tristate J5 DocD17478 Rev 9 47/123 122

Package pinouts and signal descriptions SP564Bxx-SP56Exx Table 5. Functional port pin descriptions (continued) Pin number Port pin PR Alternate function (1) Function Peripheral direction (2) Pad type RESET config. LQFP 176 LQFP 208 LBGA256 PM[5] PR[197] GP[197] SUL M/S Tristate F9 PM[6] PR[198] GP[198] SUL M/S Tristate F6 1. Alternate functions are chosen by setting the values of the PR.PA bitfields inside the SUL module. PR.PA = 000 ; PR.PA = 001 ; PR.PA = 010 ; PR.PA = 011 ; PR.PA = 100 ALT4. This is intended to select the output functions; to use one of the input functions, the PR.BE bit must be written to 1, regardless of the values selected in the PR.PA bitfields. For this reason, the value corresponding to an input only function is reported as. 2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSM.PADSELx bitfields inside the SUL module. 3. NM[0] and NM[1] have a higher priority than alternate functions. When NM is selected, the PR.PA field is ignored. 4. SXS s S32k_XTAL and S32k_EXTAL pins are shared with GP functionality. When used as crystal pins, other functionality of the pin cannot be used and it should be ensured that application never programs BE and PUE bit of the corresponding PR to "1". 5. f you want to use S32K functionality through PB[8] and PB[9], you must ensure that PB[10] is static in nature as PB[10] can induce coupling on PB[9] and disturb oscillator frequency. 6. ut of reset all the functional pins except P[0:1] and PH[9:10] are available to the user as GP. P[0:1] are available as JTAG pins (TD and TD respectively). PH[9:10] are available as JTAG pins (TK and TMS respectively). t is up to the user to configure these pins as GP when needed. 7. When MBST is enabled to run (STU Enable = 1), the application must not drive or tie PAD[178) (MD[0]) to 0 V before the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate MBST operation. When MBST is not enabled (STU Enable = 0), there are no restriction as the device does not internally drive the pad. 8. These pins can be configured as Nexus pins during reset by the debugger writing to the Nexus Development nterface "Port ontrol Register" rather than the SUL. Specifically, the debugger can enable the MD[7:0], MSE, and MK ports by programming ND (PR[MK_EN] or PR[PSTAT_EN]). MD[8:11] ports can be enabled by programming ND ((PR[MK_EN] and PR[FPM]) or PR[PSTAT_EN]). 50/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3 Electrical haracteristics This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V DD or V SS_HV ). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. n the tables where the device logic provides signals with their respective timing characteristics, the symbol for ontroller haracteristics is included in the Symbol column. n the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol SR for System Requirement is included in the Symbol column. 3.1 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 6 are used and the parameters are tagged accordingly in the tables where appropriate. Table 6. Parameter classifications lassification tag P T D Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. Note: The classification is shown in the column labeled in the parameter tables where appropriate. 3.2 NVUSR register Portions of the device configuration, such as high voltage supply is controlled via bit values in the Non-Volatile User ptions Register (NVUSR). For a detailed description of the NVUSR register, see SP564Bxx and SP56Exx Reference Manual. DocD17478 Rev 9 51/123 122

Electrical haracteristics SP564Bxx-SP56Exx 3.2.1 NVUSR [PAD3V5V(0)] field description Table 7 shows how NVUSR [PAD3V5V(0)] controls the device configuration for V DD_HV_A domain. Value (1) Table 7. PAD3V5V(0) field description Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1. '1' is delivery value. t is part of shadow flash memory, thus programmable by customer. The D electrical characteristics are dependent on the PAD3V5V(0,1) bit value. 3.2.2 NVUSR [PAD3V5V(1)] field description Table 8 shows how NVUSR [PAD3V5V(1)] controls the device configuration the device configuration for V DD_HV_B domain. Value (1) Table 8. PAD3V5V(1) field description Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1. '1' is delivery value. t is part of shadow flash memory, thus programmable by customer. The D electrical characteristics are dependent on the PAD3V5V(0,1) bit value. 3.3 Absolute maximum ratings Table 9. Absolute maximum ratings Symbol Parameter onditions Min Value Max Unit V SS_HV S R Digital ground on VSS_HV pins 0 0 V V DD_HV_A S R Voltage on VDD_HV_A pins with respect to ground (V SS_HV ) 0.3 6.0 V V DD_HV_B (1) S R Voltage on VDD_HV_B pins with respect to common ground (V SS_HV ) 0.3 6.0 V V SS_LV S R Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (V SS_HV ) V SS_HV 0.1 V SS_HV 0.1 V 52/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 9. Absolute maximum ratings (continued) Symbol Parameter onditions Min Value Max Unit V R_TRL (2) V SS_AD V DD_HV_AD0 V DD_HV_AD1 (4) V N NJPAD NJSUM AVGSEG (5) T STRAGE S R S R S R S R S R S R S R Base control voltage for external BP68 NPN device Voltage on VSS_HV_AD0, VSS_HV_AD1 (AD reference) pin with respect to ground (V SS_HV ) Voltage on VDD_HV_AD0 with respect to ground (V SS_HV ) Voltage on VDD_HV_AD1 with respect to ground (V SS_HV ) Voltage on any GP pin with respect to ground (V SS_HV ) njected input current on any pin during overload condition Absolute sum of all injected input currents during overload condition Sum of all the static current within a supply segment (V DD_HV_A or V DD_HV_B ) Relative to V DD_LV 0 V DD_LV + 1 V V SS_HV 0.1 V SS_HV + 0.1 V 0.3 6.0 Relative to V DD_HV_A (3) V DD_HV_A 0.3 V DD_HV_A +0.3 0.3 6.0 Relative to V DD_HV_A 2 V DD_HV_A 0.3 V DD_HV_A +0.3 Relative to V DD_HV_A/HV_B V DD_HV_A/HV_B 0.3 V DD_HV_A/HV_B + 0.3 10 10 50 50 V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 S R Storage temperature 55(6) 150 70 64 V V V ma ma 1. V DD_HV_B can be independently controlled from V DD_HV_A. These can ramp up or ramp down in any order. Design is robust against any supply order. 2. This voltage is internally generated by the device and no external voltage should be supplied. 3. Both the relative and the fixed conditions must be met. For instance: f V DD_HV_A is 5.9 V, V DD_HV_AD0 maximum value is 6.0 V then, despite the relative condition, the max value is V DD_HV_A + 0.3 = 6.2 V. 4. PA3, PA7, PA10, PA11 and PE12 AD_1 channels are coming from V DD_HV_B domain hence V DD_HV_AD1 should be within ±300 mv of V DD_HV_B when these channels are used for AD_1. 5. Any temperature beyond 125 should limit the current to 50 ma (max). 6. This is the storage temperature for the flash memory. Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (V N > V DD_HV_A/HV_B or V N < V SS_HV ), the voltage on pins with respect to ground (V SS_HV ) must not exceed the recommended values. DocD17478 Rev 9 53/123 122

Electrical haracteristics SP564Bxx-SP56Exx 3.4 Recommended operating conditions Table 10. Recommended operating conditions (3.3 V) Symbol Parameter onditions Min Value Max Unit V SS_HV SR V DD_HV_A (1) V DD_HV_B (1) V SS_LV (2) V R_TRL (3) V SS_AD SR SR SR SR V DD_HV_AD0 (4) SR V DD_HV_AD1 (7) SR V N NJPAD NJSUM SR SR SR Digital ground on VSS_HV pins Voltage on V DD_HV_A pins with respect to ground (V SS_HV ) Voltage on V DD_HV_B pins with respect to ground (V SS_HV ) Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (V SS_HV ) Base control voltage for external BP68 NPN device Voltage on VSS_HV_AD0, VSS_HV_AD1 (AD reference) pin with respect to ground (V SS_HV ) Voltage on VDD_HV_AD0 with respect to ground (V SS_HV ) Voltage on VDD_HV_AD1 with respect to ground (V SS_HV ) Voltage on any GP pin with respect to ground (V SS_HV ) njected input current on any pin during overload condition Absolute sum of all injected input currents during overload condition 0 0 V 3.0 3.6 V 3.0 3.6 V V SS_HV 0.1 V SS_HV + 0.1 V Relative to V DD_LV 0 V DD_LV + 1 V V SS_HV 0.1 V SS_HV + 0.1 V 3.0 (5) 3.6 Relative to V DD_HV_A (6) V DD_HV_A 0.1 V DD_HV_A + 0.1 3.0 3.6 Relative to V DD_HV_A (6) V DD_HV_A 0.1 V DD_HV_A + 0.1 V SS_HV 0.1 Relative to V DD_HV_A/HV_B V DD_HV_A/HV_B + 0.1 5 5 50 50 TV DD SR V DD_HV_A slope to ensure correct power up (8) 0.5 V/µs 0.5 V/min V V V ma 54/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 10. Recommended operating conditions (3.3 V) (continued) Symbol Parameter onditions Min Value Max Unit T A SR T J SR Ambient temperature under bias Junction temperature under bias f PU up to 120 MHz 2% 40 125 40 150 1. 100 nf EM capacitance need to be provided between each VDD/VSS_HV pair. 2. 100 nf EM capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µf bulk capacitance needs to be provided as REG on each VDD_LV pin. For details refer to the Power Management chapter of the MP5646 Reference Manual. 3. This voltage is internally generated by the device and no external voltage should be supplied. 4. 100 nf capacitance needs to be provided between V DD_AD /V SS_AD pair. 5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. n particular, AD electrical characteristics and s D electrical specification may not be guaranteed. When voltage drops below V LVDHVL, device is reset. 6. Both the relative and the fixed conditions must be met. For instance: f V DD_HV_A is 5.9 V, V DD_HV_AD0 maximum value is 6.0 V then, despite the relative condition, the max value is V DD_HV_A + 0.3 = 6.2 V. 7. PA3, PA7, PA10, PA11 and PE12 AD_1 channels are coming from V DD_HV_B domain hence V DD_HV_AD1 should be within ±100 mv of V DD_HV_B when these channels are used for AD_1. 8. Guaranteed by the device validation. Table 11. Recommended operating conditions (5.0 V) Symbol Parameter onditions Min Value Max Unit V SS_HV V (1) DD_HV_A V DD_HV_B V (3) SS_LV V (4) R_TRL V SS_AD S R S R S R S R S R Digital ground on VSS_HV pins 0 0 V Voltage on VDD_HV_A pins with respect to ground (V SS_HV ) 4.5 5.5 Voltage drop (2) 3.0 5.5 Generic GP functionality 3.0 5.5 V Ethernet/3.3 V functionality (See the notes in all figures in Section 2: Package pinouts and signal descriptions for the list of channels operating in V DD_HV_B domain) Voltage on VSS_LV (Low voltage digital supply) pins with respect to ground (V SS_HV ) Base control voltage for external BP68 NPN device Voltage on VSS_HV_AD0, VSS_HV_AD1 (AD reference) pin with respect to ground (V SS_HV ) 3.0 3.6 V V SS_HV 0.1 V SS_HV + 0.1 V Relative to V DD_LV 0 V DD_LV + 1 V V SS_HV 0.1 V SS_HV + 0.1 V V DocD17478 Rev 9 55/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 11. Recommended operating conditions (5.0 V) (continued) Symbol Parameter onditions Min Value Max Unit V DD_HV_AD0 (5) V DD_HV_AD1 (7) V N NJPAD NJSUM TV DD T A -Grade Part T J -Grade Part T A V-Grade Part T J V-Grade Part T A M-Grade Part T J M-Grade Part S R S R S R S R S R S R S R S R S R S R S R S R Voltage on VDD_HV_AD0 with respect to ground (V SS_HV ) Voltage on VDD_HV_AD1 with respect to ground (V SS_HV ) Voltage on any GP pin with respect to ground (V SS_HV ) njected input current on any pin during overload condition Absolute sum of all injected input currents during overload condition 4.5 5.5 Voltage drop (2) 3.0 5.5 Relative to V DD_HV_A (6) V DD_HV_A 0.1 V DD_HV_A + 0.1 4.5 5.5 Voltage drop (2) 3.0 5.5 Relative to V DD_HV_A (6) V DD_HV_A 0.1 V DD_HV_A + 0.1 V SS_HV 0.1 Relative to V DD_HV_A/HV_B V DD_HV_A/HV_B + 0.1 5 5 50 50 V DD_HV_A slope to ensure correct 0.5 V/µs power up (8) 0.5 V/min Ambient temperature under bias 40 85 Junction temperature under bias 40 110 Ambient temperature under bias 40 105 Junction temperature under bias 40 130 Ambient temperature under bias 40 125 Junction temperature under bias 40 150 V V V ma 1. 100 nf EM capacitance need to be provided between each VDD/VSS_HV pair. 2. Full device operation is guaranteed by design from 3.0 V 5.5 V. S functionality is guaranteed from the entire range 3.0V 5.5 V, the parametrics measured are at 3.0V and 5.5V (extreme voltage ranges to cover the range of operation). The parametrics might have some variation in the intermediate voltage range, but there is no impact to functionality. 3. 100 nf EM capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µf bulk capacitance needs to be provided as REG on each VDD_LV pin. 4. This voltage is internally generated by the device and no external voltage should be supplied. 5. 100 nf capacitance needs to be provided between V DD_HV_(AD0/AD1) /V SS_HV_(AD0/AD1) pair. 6. Both the relative and the fixed conditions must be met. For instance: f V DD_HV_A is 5.9 V, V DD_HV_AD0 maximum value is 6.0 V then, despite the relative condition, the max value is V DD_HV_A + 0.3 = 6.2 V. 7. PA3, PA7, PA10, PA11 and PE12 AD_1 channels are coming from V DD_HV_B domain hence VDD_HV_AD1 should be within ±100 mv of V DD_HV_B when these channels are used for AD_1. 56/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 8. Guaranteed by device validation. Note: SRAM retention guaranteed to LVD levels. 3.5 Thermal characteristics 3.5.1 Package thermal characteristics Table 12. LQFP thermal characteristics (1) Symbol Parameter onditions (2) Pin count Value (3) Min Typ Max Unit R JA D Thermal resistance, junction-to-ambient natural convection Single-layer board1s 176 44.4 (4) /W 208 43 /W R JA D Thermal resistance, junction-to-ambient natural convection board2s2p (5) 208 33.9 /W Four-layer 176 36.1 /W 1. Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125. 3. All values need to be confirmed during device validation. 4. 1s board as per standard JEDE (JESD51-7) in natural convection. 5. 2s2p board as per standard JEDE (JESD51-7) in natural convection. Table 13. LBGA256 thermal characteristics (1) Symbol Parameter onditions Value Unit R JA Thermal resistance, junction-to-ambient natural convection Single-layer board1s 44.3 Four-layer board2s2p 31 /W 1. Thermal characteristics are targets based on simulation that are subject to change per device characterization. DocD17478 Rev 9 57/123 122

Electrical haracteristics SP564Bxx-SP56Exx 3.5.2 Power considerations The average chip-junction temperature, T J, in degrees elsius, may be calculated using Equation 1: Equation 1 T J = T A + (P D R JA ) Where: T A is the ambient temperature in. R JA is the package junction-to-ambient thermal resistance, in /W. P D is the sum of P NT and P (P D = P NT + P ). P NT is the product of DD and V DD, expressed in watts. This is the chip internal power. P represents the power dissipation on input and output pins; user determined. Most of the time for the applications, P < P NT and may be neglected. n the other hand, P may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between P D and T J (if P is neglected) is given by: Equation 2 P D = K / (T J + 273 ) Therefore, solving equations Equation 1 and Equation 2: Equation 3 K = P D (T A + 273 ) + R JA P D 2 Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring P D (at equilibrium) for a known T A. Using this value of K, the values of P D and T J may be obtained by solving equations Equation 1 and Equation 2 iteratively for any value of T A. 3.6 pad electrical characteristics 3.6.1 pad types The device provides four main pad types depending on the associated alternate functions: Slow padsthese pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium padsthese pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast padsthese pads provide maximum speed. These are used for improved Nexus debugging capability. nput only padsthese pads are associated to AD channels and 32 khz low power external crystal oscillator providing low input leakage. Low power padsthese pads are active in standby mode for wakeup source. Also, medium/slow and fast/medium pads are available in design which can be configured to behave like a slow/medium and medium/fast pads depending upon the slew-rate control. 58/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Medium and fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing A performance. 3.6.2 input D characteristics Table 14 provides input D electrical characteristics as described in Figure 5. Figure 5. input D electrical characteristics definition V DD V N V H V HYS V L PDx = 1 (GPD register of SUL) PDx = 0 Table 14. input D electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max V H V L V HYS LKG W F W NF nput high level MS (Schmitt SR P Trigger) 0.65 V DD V DD + 0.4 nput low level MS (Schmitt SR P Trigger) 0.3 0.35V DD nput hysteresis MS (Schmitt Trigger) 0.1V DD P T A = 40 2 P No injection T A = 25 2 Digital input leakage on adjacent D pin T A = 105 12 500 P T A = 125 70 1000 SR P SR P Width of input pulse rejected by analog filter (3) 40 (4) ns Width of input pulse accepted by analog filter (3) 1000 (4) ns V na 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. All values need to be confirmed during device validation. 3. Analog filters are available on all wakeup lines. DocD17478 Rev 9 59/123 122

Electrical haracteristics SP564Bxx-SP56Exx 4. The width of input pulse in between 40 ns to 1000 ns is indeterminate. t may pass the noise or may not depending on silicon sample to sample variation. 3.6.3 output D characteristics The following tables provide D characteristics for bidirectional pads: Table 15 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 16 provides output driver characteristics for pads when in SLW configuration. Table 17 provides output driver characteristics for pads when in MEDUM configuration. Table 18 provides output driver characteristics for pads when in FAST configuration. Table 15. pull-up/pull-down D electrical characteristics Symbol Parameter onditions (1),(2) Value Min Typ Max Unit WPU WPD P V N = V L, V DD = PAD3V5V = 0 10 150 Weak pull-up 5.0 V ± 10% PAD3V5V = 1 (3) 10 250 current absolute value V P N = V L, V DD = PAD3V5V = 1 10 150 3.3 V ± 10% P V N = V H, V DD = PAD3V5V = 0 10 150 Weak pull-down 5.0 V ± 10% PAD3V5V = 1 10 250 current absolute value V P N = V H, V DD = PAD3V5V = 1 10 150 3.3 V ± 10% µa µa 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. 3. The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDx, EVT, MK) are configured in input or in high impedance state. Table 16. SLW configuration output buffer electrical characteristics Symbol Parameter onditions (1),(2) Value Min Typ Max Unit V H P P utput high level SLW configuration Push Pull H = 3 ma, V DD = 5.0 V ± 10%, PAD3V5V = 0 0.8V DD H = 3 ma, V DD = 5.0 V ± 10%, PAD3V5V = 1 (3) 0.8V DD H = 1.5 ma, V DD = 3.3 V ± 10%, PAD3V5V = 1 V DD 0.8 V 60/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 16. SLW configuration output buffer electrical characteristics (continued) Symbol Parameter onditions (1),(2) Value Min Typ Max Unit V L P P utput low level SLW configuration Push Pull L = 3 ma, V DD = 5.0 V ± 10%, PAD3V5V = 0 0.1V DD L = 3 ma, V DD = 5.0 V ± 10%, PAD3V5V = 1 (3) 0.1V DD L = 1.5 ma, V DD = 3.3 V ± 10%, PAD3V5V = 1 0.5 V 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. 3. The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDx, EVT, MK) are configured in input or in high impedance state. Table 17. MEDUM configuration output buffer electrical characteristics Symbol Parameter onditions (1), (2) Value Min Typ Max Unit H = 3 ma, V DD = 5.0 V ± 10%, PAD3V5V = 0 0.8V DD V H utput high level MEDUM configuration Push Pull H = 1.5 ma, V DD = 5.0 V ± 10%, 0.8V DD PAD3V5V = 1 (3) V H = 2 ma, V DD = 3.3 V ± 10%, PAD3V5V = 1 V DD 0.8 L = 3 ma, V DD = 5.0 V ± 10%, PAD3V5V = 0 0.2V DD V L utput low level MEDUM configuration Push Pull L = 1.5 ma, V DD = 5.0 V ± 10%, 0.1V DD PAD3V5V = 1 (3) V L = 2 ma, V DD = 3.3 V ± 10%, PAD3V5V = 1 0.5 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. 3. The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDx, EVT, MK) are configured in input or in high impedance state. DocD17478 Rev 9 61/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 18. FAST configuration output buffer electrical characteristics Symbol Parameter onditions (1),(2) Value Min Typ Max Unit V H P utput high level FAST configuration Push Pull H = 14 ma, V DD = 5.0 V ± 10%, PAD3V5V = 0 0.8V DD H = 7 ma, V DD = 5.0 V ± 10%, 0.8V DD PAD3V5V = 1 (3) H = 11 ma, V DD = 3.3 V ± 10%, PAD3V5V = 1 V DD 0.8 V P L = 14 ma, V DD = 5.0 V ± 10%, PAD3V5V = 0 0.1V DD V L utput low level FAST configuration Push Pull L = 7 ma, V DD = 5.0 V ± 10%, 0.1V DD PAD3V5V = 1 (3) V L = 11 ma, V DD = 3.3 V ± 10%, PAD3V5V = 1 0.5 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. 3. The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus outputs (MDx, EVT, MK) are configured in input or in high impedance state. 3.6.4 utput pin transition times Table 19. utput pin transition times Symbol Parameter onditions (1),(2) Value (3) Unit Min Typ Max T tr D L = 25 pf 50 V DD = 5.0 V ± 10 %, T L = 50 pf 100 PAD3V5V = 0 D utput transition time output pin (4) L = 100 pf 125 D SLW configuration L = 25 pf 40 V DD = 3.3 V ± 10 %, T L = 50 pf 50 PAD3V5V = 1 D L = 100 pf 75 ns T tr D L = 25 pf V DD = 5.0 V ± 10 %, 10 T L = 50 pf PAD3V5V = 0 20 utput transition D time output pin (4) SUL.PRx.SR = 1 L = 100 pf 40 D MEDUM L = 25 pf V configuration DD = 3.3 V ± 10 %, 12 T L = 50 pf PAD3V5V = 1 25 D SUL.PRx.SR = 1 L = 100 pf 40 ns 62/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 19. utput pin transition times (continued) Symbol Parameter onditions (1),(2) Value (3) Unit Min Typ Max T tr D utput transition time output pin (4) FAST configuration L = 25 pf 4 L = 50 pf V DD = 5.0 V ± 10%, PAD3V5V = 0 6 L = 100 pf 12 L = 25 pf 4 L = 50 pf V DD = 3.3 V ± 10%, PAD3V5V = 1 7 L = 100 pf 12 ns 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. 3. All values need to be confirmed during device validation. 4. L includes device and package capacitances ( PKG < 5 pf). 3.6.5 pad current specification The pads are distributed across the supply segment. Each supply is associated to a V DD /V SS_HV supply pair as described in Table 20. Table 21 provides consumption figures. n order to ensure device reliability, the average current of the on a single segment should remain below the AVGSEG maximum value. n order to ensure device functionality, the sum of the dynamic and static current of the on a single segment should remain below the DYNSEG maximum value. Table 20. supplies Package LBGA256 (1) LQFP208 LQFP176 pin6 (V DD_HV_A ) pin7 (V SS_HV ) pin6 (V DD_HV_A ) pin7 (V SS_HV ) Supplies Equivalent to 208-pin LQFP segment pad distribution + G6, G11, H11, J11 pin27 (V DD_HV_A )pi n28 (V SS_HV ) pin27 (V DD_HV_A )pi n28 (V SS_HV ) pin73 (V SS_HV ) pin75 (V DD_HV_A ) pin57 (V SS_HV ) pin59 (V DD_HV_A ) pin101 (V DD_HV_A ) pin102 (V SS_HV ) pin85 (V DD_HV_A ) pin86 (V SS_HV ) pin132 (V SS_HV ) pin133 (V DD_HV_A ) pin123 (V SS_HV ) pin124 (V DD_HV_B ) pin147 (V SS_HV ) pin148 (V DD_HV_B ) pin150 (V SS_HV ) pin151 (V DD_HV_A ) pin174 (V SS_HV ) pin175 (V DD_HV_A ) 1. VDD_HV_B supplies the voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. DocD17478 Rev 9 63/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 21. consumption Symbol Parameter onditions (1),(2) Value (3) Unit Min Typ Max SWTSLW (4) Peak current for D SLW configuration L = 25 pf V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 19.9 15.5 ma SWTMED (4) Peak current for D MEDUM configuration L = 25 pf V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 28.8 16.3 ma SWTFST (4) Peak current for D FAST configuration L = 25 pf V DD = 5.0 V ± 10%, PAD3V5V = 0 V DD = 3.3 V ± 10%, PAD3V5V = 1 113.5 52.1 ma RMSSLW Root mean square D current for SLW configuration L = 25 pf, 2 MHz 2.22 L = 25 pf, 4 MHz V DD = 5.0 V ± 10%, PAD3V5V = 0 3.13 L = 100 pf, 2 MHz 6.54 L = 25 pf, 2 MHz 1.51 L = 25 pf, 4 MHz V DD = 3.3 V ± 10%, PAD3V5V = 1 2.14 L = 100 pf, 2 MHz 4.33 ma RMSMED D Root mean square current for MEDUM configuration L = 25 pf, 13 MHz 6.5 L = 25 pf, 40 MHz V DD = 5.0 V ± 10%, PAD3V5V = 0 13.32 L = 100 pf, 13 MHz 18.26 L = 25 pf, 13 MHz 4.91 L = 25 pf, 40 MHz V DD = 3.3 V ± 10%, PAD3V5V = 1 8.47 L = 100 pf, 13 MHz 10.94 ma RMSFST D Root mean square current for FAST configuration L = 25 pf, 40 MHz 21.05 L = 25 pf, 64 MHz V DD = 5.0 V ± 10%, PAD3V5V = 0 33 L = 100 pf, 40 MHz 55.77 L = 25 pf, 40 MHz 14 L = 25 pf, 64 MHz V DD = 3.3 V ± 10%, PAD3V5V = 1 20 L = 100 pf, 40 MHz 34.89 ma AVGSEG S R Sum of all the static D current within a supply segment V DD = 5.0 V ± 10%, PAD3V5V = 0 70 V DD = 3.3 V ± 10%, PAD3V5V = 1 65 (4) ma 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. 3. All values need to be confirmed during device validation. 4. Stated maximum values represent peak consumption that lasts only a few ns during transition. 64/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.7 RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. Figure 6. Start-up reset requirements V DD_HV_A V DDMN RESET V H V L device reset forced by RESET device start-up phase Figure 7. Noise filtering on reset signal V RESET hw_rst V DD 1 V H V L filtered by hysteresis filtered by lowpass filter filtered by lowpass filter unknown reset state device under hardware reset 0 W FRST W FRST W NFRST DocD17478 Rev 9 65/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 22. Reset electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max V H S R nput High Level MS P (Schmitt Trigger) 0.65V DD V DD + 0.4 V V L S R nput low Level MS P (Schmitt Trigger) 0.3 0.35V DD V V HYS nput hysteresis MS (Schmitt Trigger) 0.1V DD V Push Pull, L = 2 ma, V DD = 5.0 V ± 10 %, PAD3V5V = 0 (recommended) 0.1V DD V L P utput low level Push Pull, L = 1 ma, V DD = 5.0 V ± 10%, PAD3V5V = 1 (3) 0.1V DD V Push Pull, L = 1 ma, V DD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) 0.5 L = 25 pf, V DD = 5.0 V ± 10%, PAD3V5V = 0 10 L = 50 pf, V DD = 5.0 V ± 10%, PAD3V5V = 0 20 T tr utput transition time D output pin (4) MEDUM configuration L = 100 pf, V DD = 5.0 V ± 10%, PAD3V5V = 0 L = 25 pf, V DD = 3.3 V ± 10%, PAD3V5V = 1 40 12 ns L = 50 pf, V DD = 3.3 V ± 10%, PAD3V5V = 1 25 L = 100 pf, V DD = 3.3 V ± 10%, PAD3V5V = 1 40 W FRST S R Reset input filtered P pulse 40 ns W NFRS T S R Reset input not filtered P pulse 1000 ns WPU Weak pull-up current P absolute value V DD = 3.3 V ± 10%, PAD3V5V = 1 10 150 V DD = 5.0 V ± 10%, PAD3V5V = 0 10 150 V DD = 5.0 V ± 10%, PAD3V5V = 1 (5) 10 250 µa 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. V DD as mentioned in the table is V DD_HV_A /V DD_HV_B. All values need to be confirmed during device validation. 3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the RGM module section of the device Reference Manual). 4. L includes device and package capacitance ( PKG < 5 pf). 5. The configuration PAD3V5 = 1 when V DD = 5 V is only transient configuration during power-up. All pads but RESET and Nexus output (MDx, EVT, MK) are configured in input or in high impedance state. 66/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.8 Power management electrical characteristics 3.8.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply V DD_LV from the high voltage supply V DD_HV_A. The following supplies are involved: HV: High voltage external power supply for voltage regulator module. This must be provided externally through V DD_HV_A power pin. LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the on-chip VREG with an external ballast (BP68 NPN device). t is further split into four main domains to ensure noise isolation between critical LV modules within the device: LV_R: Low voltage supply for the core. t is also used to provide supply for FMPLL through double bonding. LV_FLA0/FLA1: Low voltage supply for the two code Flash modules. t is shorted with LV_R through double bonding. LV_DFLA: Low voltage supply for data Flash module. t is shorted with LV_R through double bonding. LV_PLL: Low voltage supply for FMPLL. t is shorted to LV_R through double bonding. Figure 8. Voltage regulator capacitance connection 100 nf 100 nf 100 nf VDD_LV VSS_LV VDD_LV VSS_LV VDD_LV VSS_LV 40 f (4 10 f) ( REGn ) PD1 Switchable Domain (FMPLL, Flash) PD0 (always on domain) PD0 Logic 32 KB 56 KB Split Split TRL TRL 8KB Split TRL VDD_LV ff chip BP68 NPN driver VSS_LV VR_TRL HPREG HPVDD LPVDD sw1 (<0.1 ) 10 f LPREG ( DE2 ) hip Boundary VDD_BV VDD_HV_A VSS_HV HPVDD LPVDD 100 nf 1) All VSS_LV pins must be grounded, as shown for VSS_HV pin. DocD17478 Rev 9 67/123 122

Electrical haracteristics SP564Bxx-SP56Exx The internal voltage regulator requires external bulk capacitance ( REGn ) to be connected to the device to provide a stable low voltage digital supply to the device. Also required for stability is the DE2 capacitor at ballast collector. This is needed to minimize sharp injection current when ballast is turning N. Apart from the bulk capacitance, user should connect EM/decoupling cap ( REGP ) at each V DD_LV /V SS_LV pin pair. 3.8.1.1 Recommendations The external NPN driver must be BP68 type. V DD_LV should be implemented as a power plane from the emitter of the ballast transistor. 10 F capacitors should be connected to the 4 pins closest to the outside of the package and should be evenly distributed around the package. For BGA packages, the balls should be used are D8, H14, R9, J3 one cap on each side of package. There should be a track direct from the capacitor to this pin (pin also connects to V DD_LV plane). The tracks ESR should be less than 100 m. The remaining V DD_LV pins (exact number will vary with package) should be decoupled with 0.1 F caps, connected to the pin as per 10 F. (see Section 3.4: Recommended operating conditions). 3.8.2 V DD_BV options ption 1: V DD_BV shared with V DD_HV_A V DD_BV must be star routed from V DD_HV_A from the common source. This is to eliminate ballast noise injection on the MU. ption 2: V DD_BV independent of the MU supply V DD_BV > 2.6 V for correct functionality. The device is not monitoring this supply hence the external component must meet the 2.6 V criteria through external monitoring if required. Table 23. Voltage regulator electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max REGn S R External ballast stability capacitance 40 60 F R REG S R Stability capacitor equivalent serial resistance 0.2 W REGP S R Decoupling capacitance (lose to the pin) V DD_HV_A/HV_B /V SS_HV pair 100 nf V DD_LV /V SS_LV pair 100 nf DE2 S R Stability capacitance regulator supply (lose to the ballast collector) V DD_BV /V SS_HV 10 40 F V MREG P Main regulator output voltage After trimming T A = 25 1.20 1.28 1.32 V 68/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 23. Voltage regulator electrical characteristics (continued) Symbol Parameter onditions (1) Value (2) Unit Min Typ Max MREG S R Main regulator current provided to V DD_LV domain 350 ma MREGNT Main regulator module current D consumption MREG = 200 ma 2 MREG = 0 ma 1 ma V LPREG Low power regulator output P voltage After trimming T A = 25 1.17 1.27 1.32 V LPREG S R Low power regulator current provided to V DD_LV domain 50 ma LPREGNT D Low power regulator module current consumption LPREG = 15 ma; T A = 55 LPREG = 0 ma; T A = 55 600 20 A VREGREF D Main LVDs and reference current consumption (low power and main regulator switched off) T A = 55 2 A VREDLVD12 Main LVD current consumption D (switch-off during standby) T A = 55 1 A DD_HV_A D n-rush current on V DD_BV during power-up 600 (3) ma 1. V DD_HV_A = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. nrush current is seen more like steps of 600 ma peak. The startup of the regulator happens in steps of 50 mv in ~25 steps to reach ~1.2 V V DD_LV. Each step peak current is within 600 ma 3.8.3 Voltage monitor electrical characteristics Note: The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the V DD_HV_A and the V DD_LV voltage while device is supplied: PR monitors V DD_HV_A during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors V DD_HV_A to ensure device is reset below minimum functional supply LVDHV5 monitors V DD_HV_A when application uses device in the 5.0 V±10 % range LVDLVR monitors power domain No. 1 (PD1) LVDLVBKP monitors power domain No. 0 (PD0). VDD_LV is same as PD0 supply. When enabled, PD2 (RAM retention) is monitored through LVD_DGBKP. DocD17478 Rev 9 69/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 9. Low voltage monitor vs. Reset V DDHV/LV V LVDHVxH/LVxH V LVDHVxL/LVxL RESET Table 24. Low voltage monitor electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max V PRUP V PRH V LVDHV3H V LVDHV3L V LVDHV5H V LVDHV5L V LVDLVRL V LVDLVBKPL S R P Supply for functional PR module 1.0 5.5 P Power-on reset threshold 1.5 2.6 T LVDHV3 low voltage detector high threshold 2.7 2.85 T LVDHV3 low voltage detector low threshold 2.6 2.74 T LVDHV5 low voltage detector high threshold 4.3 4.5 T LVDHV5 low voltage detector low threshold 4.2 4.4 P LVDLVR low voltage detector low threshold T A = 25, 1.08 1.17 after trimming P LVDLVBKP low voltage detector low threshold 1.08 1.17 V 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3.9 Low voltage domain power consumption Table 25 provides D electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. 70/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 25. Low voltage power domain electrical characteristics (1) Symbol Parameter onditions (2) Value DDMAX (5) DDRUN DDHALT DDSTP DDSTDBY3 (96 KB RAM retained) DDSTDBY2 (64 KB RAM retained) DDSTDBY1 (8 KB RAM retained) Adders in LP mode RUN mode maximum D average current Min Typ (3) Max (4) 210 Unit 300 (6), (7) ma P at 120 MHz T A = 25 150 208 (9) ma D RUN mode typical average current (8) at 80 MHz T A = 25 110 (8) 150 (10) ma at 120 MHz T A = 125 180 280 ma P HALT mode current (11) at 120 MHz T A = 25 20 27 ma at 120 MHz T A = 125 35 100 ma P STP mode current (12) No clocks active T A = 25 0.4 5 ma T A = 125 16 72 ma P T A = 25 50 96 µa STANDBY3 mode current (13) No clocks active T A = 125 630 2400 µa T A = 25 40 92 µa STANDBY2 mode current (14) No clocks active T A = 125 500 2000 µa T STANDBY1 mode A = 25 25 85 µa current (15) No clocks active T A = 125 230 1100 µa T 32 KHz S T A = 25 5 µa 4 40 MHz S T A = 25 3 ma 16 MHz R T A = 25 500 µa 128 KHz R T A = 25 5 µa 1. Except for DDMAX, all the current values are total current drawn from V DD_HV_A. 2. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified All temperatures are based on an ambient temperature. 3. Target typical current consumption for the following typical operating conditions and configuration. Process = typical, Voltage = 1.2 V. 4. Target maximum current consumption for mode observed under typical operating conditions. Process = Fast, Voltage = 1.32 V. 5. Running consumption is given on voltage regulator supply (V DDREG ). t does not include consumption linked to s toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all cores and peripherals running, and code fetched from code flash while modify operation on-going on data flash. t is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 6. Higher current may sunk by device during power-up and standby exit. Please refer to in rush current in Table 23. 7. Maximum allowed current is package dependent. 8. nly for the P classification: ode fetched from RAM: Serial Ps AN and LN in loop back mode, DSP as Master, PLL as system lock (4 x Multiplier) peripherals on (ems/tu/ad) and running at max frequency, periodic SW/WDG timer reset enabled. RUN current measured with typical application with accesses on both code flash and RAM. DocD17478 Rev 9 71/123 122

Electrical haracteristics SP564Bxx-SP56Exx 9. Subject to change, onfiguration: 1 e200z4d + 4 kbit/s ache, 1 e200z0h (1/2 system frequency), SE, 1 edma (10 ch.), 6 FlexAN (4 500 kbit/s, 2 125 kbit/s), 4 LNFlexD (20 kbit/s), 6 DSP (2 2 Mbit/s, 3 4 Mbit/s, 1 10 Mbit/s), 16 Timed, 16 AD nput, 1 FlexRay (2 ch., 10 Mbit/s), 1 FE (100 Mbit/s), 1 RT, 4 PT channels, 1 SWT, 1 STM. For lower pin count packages reduce the amount of timed s and AD channels. RUN current measured with typical application with accesses on both code flash and RAM. 10. This value is obtained from limited sample set. 11. Data Flash Power Down. ode Flash in Low Power. SR 128 khz and FR 16 MHz N. 16 MHz XTAL clock. FlexAN: instances: 0, 1, 2 N (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LNFlex: instances: 0, 1, 2 N (clocked but no reception or transmission), instance: 3-9 clocks gated. ems: instance: 0 N (16 channels on PA[0]- PA[11] and P[12]-P[15]) with PWM 20 khz, instance: 1 clock gated. DSP: instance: 0 (clocked but no communication, instance: 1-7 clocks gated). RT/AP N. PT N. STM N. AD N but no conversion except 2 analog watchdogs. 12. nly for the P classification: No clock, FR 16 MHz FF, SR128 khz N, PLL FF, HPvreg FF, LPVreg N. All possible peripherals off and clock gated. Flash in power down mode. 13. nly for the P classification: LPreg N, HPVreg FF, 96 KB RAM N, device configured for minimum consumption, all possible modules switched-off. Measurement condition assumes T j = Ta. 14. LPreg N, HPVreg FF, 64 KB RAM N, device configured for minimum consumption, all possible modules switched-off. Measurement condition assumes T j = Ta. 15. LPreg N, HPVreg FF, 8 KB RAM N, device configured for minimum consumption, all possible modules switched FF. Measurement condition assumes T j = Ta. 3.10 Flash memory electrical characteristics 3.10.1 Program/Erase characteristics Table 26 shows the code flash memory program and erase characteristics. Table 26. ode flash memoryprogram and erase specifications Symbol Parameter Value Min Typ (1) nitial max (2) Max (3) Unit T dwprogram Double word (64 bits) program time (4) 18 50 500 µs T 16Kpperase 16 KB block pre-program and erase time 200 500 5000 ms T 32Kpperase 32 KB block pre-program and erase time 300 600 5000 ms T 128Kpperase 128 KB block pre-program and erase time 600 1300 5000 ms T eslat D Erase Suspend Latency 30 30 µs (5) t ESRT Erase Suspend Request Rate 20 ms t PABT D Program Abort Latency 10 10 µs t EAPT D Erase Abort Latency 30 30 µs 1. Typical program and erase times assume nominal supply values and operation at 25. All times are subject to change pending device characterization. 2. nitial factory condition: < 100 program/erase cycles, 25, typical supply voltage. 3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4. Actual hardware programming times. This does not include software overhead. 5. t is Time between erase suspend resume and the next erase suspend request. Table 27 shows the data flash memory program and erase characteristics. 72/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 27. Data flash memoryprogram and erase specifications Symbol Parameter Value Min Typ (1) nitial max (2) Max (3) Unit T wprogram Word (32 bits) program time (4) 30 70 500 µs T 16Kpperase 16 KB block pre-program and erase time 700 800 5000 ms T eslat D Erase Suspend Latency 30 30 µs (5) t ESRT Erase Suspend Request Rate 10 ms t PABT D Program Abort Latency 12 12 µs t EAPT D Erase Abort Latency 30 30 µs 1. Typical program and erase times assume nominal supply values and operation at 25. All times are subject to change pending device characterization. 2. nitial factory condition: < 100 program/erase cycles, 25, typical supply voltage. 3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4. Actual hardware programming times. This does not include software overhead. 5. t is time between erase suspend resume and next erase suspend. Table 28. Flash memory module life Symbol Parameter onditions Min Value Typ Unit P/E Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (T J ) Number of program/erase cycles per block for 32 Kbyte blocks over the operating temperature range (T J ) Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (T J ) 100000 100000 cycles 10000 100000 cycles 1000 100000 cycles Blocks with 0 1000 P/E cycles 20 years Retention Minimum data retention at 85 average ambient temperature (1) Blocks with 10000 P/E cycles 10 years Blocks with 100000 P/E cycles 5 years 1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. DocD17478 Rev 9 73/123 122

Electrical haracteristics SP564Bxx-SP56Exx E circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Symbol Parameter Table 29. Flash memory read access timing (1) ode flash memory onditions (2) Data flash memory Frequency range Unit P 5 wait states 13 wait states 120 100 4 wait states 11 wait states 10080 f READ D Maximum frequency for Flash 3 wait states 9 wait states 8064 reading 2 wait states 7 wait states 6440 MHz 1 wait states 4 wait states 4020 0 wait states 2 wait states 200 1. Max speed is the maximum speed allowed including PLL frequency modulation (FM). 2. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 3.10.2 Flash memory power supply D characteristics Table 30 shows the flash memory power supply D characteristics on external supply. Table 30. Flash memory power supply D electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max (3) FREAD (3) DFREAD Sum of the current consumption on V DD_HV_A on read access Flash memory module read f PU = 120 MHz 2% (4) ode flash memory Data flash memory 33 13 ma (3) FMD (3) DFMD Sum of the current consumption on V DD_HV_A (program/erase) Program/Erase on-going while reading flash memory registers f PU = 120 MHz 2% (4) ode flash memory Data flash memory 52 13 ma FLPW (3) Sum of the current consumption on V DD_HV_A during flash memory low power mode ode flash memory 1.1 ma (3) FPWD (3) DFPWD Sum of the current consumption on V DD_HV_A during flash memory power down mode ode flash memory Data flash memory 150 150 µa 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. Data based on characterization results, not tested in production. 4. f PU 120 MHz 2 % can be achieved over full temperature 125 ambient, 150 junction temperature. 74/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.10.3 Flash memory start-up/switch-off timings Table 31. Start-up time/switch-off time Symbol Parameter onditions (1) Value Min Typ Max Unit T FLARSTEXT Delay for flash memory module to exit D reset mode ode flash memory Data flash memory 125 T FLALPEXT T FLAPDEXT Delay for flash memory module to exit T low-power mode Delay for flash memory module to exit T power-down mode ode flash memory ode flash memory Data flash memory 0.5 30 µs T FLALPENTR Y Delay for flash memory module to T enter low-power mode ode flash memory 0.5 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 3.11 Electromagnetic compatibility (EM) characteristics Susceptibility tests are performed on a sample basis during product characterization. 3.11.1 Designing hardened software to avoid noise problems EM characterization and optimization are performed at component level with a typical application environment and simplified MU software. t should be noted that good EM performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EM software optimization and prequalification tests in relation with the EM level requested for the application. Software recommendations The software flowchart must include the management of runaway conditions such as: orrupted program counter Unexpected reset ritical data corruption (control registers) Pre-qualification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note Software Techniques For mproving Microcontroller EM Performance (AN1015)). DocD17478 Rev 9 75/123 122

Electrical haracteristics SP564Bxx-SP56Exx 3.11.2 Electromagnetic interference (EM) The product is monitored in terms of emission based on a typical application. This emission test conforms to the E61967-1 standard, which specifies the general conditions for EM measurements. Table 32. EM radiated emission measurement (1)(2) Symbol Parameter onditions Value Min Typ Max Unit f PU V DD_LV S EM S R Scan range 0.150 1000 MHz S R perating frequency S R LV operating voltages T Peak level V DD = 5 V, T A = 25, LQFP176 package Test conforming to E 61967-2, f S = 40 MHz/f PU = 120 MHz 120 MHz 1.28 V No PLL frequency modulation ± 2% PLL frequency modulation 18 dbµv 14 (3) dbµv 1. EM testing and port waveforms per E 61967-1, -2, -4. 2. For information on conducted emission and susceptibility measurement (norm E 61967-4), please contact your local marketing representative. 3. All values need to be confirmed during device validation. 3.11.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 3.11.3.1 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts (n+1) supply pin). This test conforms to the AE-Q100-002/-003/-011 standard. For more details, refer to the application note Electrostatic Discharge Sensitivity Measurement (AN1181). Table 33. ESD absolute maximum ratings (1)(2) Symbol Ratings onditions lass Max value (3) Unit V ESD(HBM) Electrostatic discharge voltage (Human Body Model) T A = 25 conforming to AE-Q100-002 H1 2000 V ESD(MM) V ESD(DM) Electrostatic discharge voltage (Machine Model) Electrostatic discharge voltage (harged Device Model) T A = 25 conforming to AE-Q100-003 T A = 25 conforming to AE-Q100-011 M2 200 3A 500 750 (corners) V 76/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 1. All ESD testing is in conformity with DF-AE-Q100 Stress Test Qualification for Automotive Grade ntegrated ircuits. 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. omplete D parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3. Data based on characterization results, not tested in production. 3.11.3.2 Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: A supply over-voltage is applied to each power supply pin. A current injection is applied to each input, output and configurable pin. These tests are compliant with the EA/JESD 78 latch-up standard. Table 34. Latch-up results Symbol Parameter onditions lass LU Static latch-up class T A = 125 conforming to JESD 78 level A 3.12 Fast external crystal oscillator (4 40 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 10 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 35 provides the parameter description of 4 MHz to 40 MHz crystals used for the design simulations. DocD17478 Rev 9 77/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 10. rystal oscillator and resonator connection scheme EXTAL 1 XTAL rystal XTAL DEVE R D 2 V DD R DEVE EXTAL EXTAL Resonator XTAL DEVE Note: XTAL/EXTAL must not be directly used to drive external circuits. Table 35. rystal description Nominal frequency (MHz) NDK crystal reference rystal equivalent series resistance ESR rystal motional capacitance ( m ) ff rystal motional inductance (L m ) mh Load on xtalin/xtalout 1 = 2 (pf) (1) Shunt capacitance between xtalout and xtalin 0 (2) (pf) 4 NX8045GB 300 2.68 591.0 21 2.93 8 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 NX5032GA 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 40 NX5032GA 50 6.18 2.56 8 3.49 1. The values specified for 1 and 2 are the same as used in simulations. t should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the A / transient behavior depends upon them. 2. The value of 0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). 78/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics S_MTRANS bit (ME_GS register) 1 0 V XTAL 1/f MXS V FXS 90% V FXSP 10% T MXSSU valid internal clock Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max f FXS SR Fast external crystal oscillator frequency 4.0 40.0 MHz g mfxs Fast external crystal oscillator transconductance DD ma/v V DD = 5.0 V ± 10% 6.5 (3) 25 (3) V FXS T scillation amplitude at EXTAL V FXSP P scillation operating point FXS (4) T T FXSSU T Fast external crystal oscillator consumption Fast external crystal oscillator start-up time f S = 40 MHz For both V DD = 3.3 V ± 10%, V DD = 5.0 V ± 10% V DD = 3.3 V ± 10%, f S = 40 MHz V DD = 5.0 V ± 10%, f S = 40 MHz V DD = 3.3 V ± 10%, f S = 16 MHz V DD = 5.0 V ± 10%, f S = 16 MHz 0.95 V 1.8 V f S = 40 MHz For both V DD = 3.3 V ± 10%, V DD = 5.0 V ± 10% 2 2.2 2.3 2.5 1.3 1.5 1.6 1.8 ma 5 ms DocD17478 Rev 9 79/123 122

l Electrical haracteristics SP564Bxx-SP56Exx Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics (continued) Symbol Parameter onditions (1) Value (2) Unit Min Typ Max V H SR P nput high level MS (Schmitt Trigger) scillator bypass mode 0.65V DD_ HV_A V DD_HV_A + 0.4 V V L SR P nput low level MS (Schmitt Trigger) scillator bypass mode 0.3 0.35V DD_HV_A V 1. V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. Based on ATE z 4. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals). 3.13 Slow external crystal oscillator (32 khz) electrical characteristics The device provides a low power oscillator/resonator driver. Figure 12. rystal oscillator and resonator connection scheme S32K_EXTAL S32K_EXTAL 1 rystal R P Resonator S32K_XTAL DEVE 2 S32K_XTAL DEVE Note: S32K_XTAL/S32K_EXTAL must not be directly used to drive external circuits. 80/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Figure 13. Equivalent circuit of a quartz crystal 0 1 rystal 2 1 m R m L m 2 Table 37. rystal motional characteristics (1) Symbol Parameter onditions Value Min Typ Max Unit L m Motional inductance 11.796 KH m Motional capacitance 2 ff 1/2 Load capacitance at S32K_XTAL and S32K_EXTAL with respect to 18 28 pf ground (2) A coupled @ 0 = 2.85 pf (4) 65 R m (3) Motional resistance A coupled @ 0 = 4.9 pf (4) 50 A coupled @ 0 = 7.0 pf (4) 35 kw A coupled @ 0 = 9.0 pf (4) 30 1. The crystal used is Epson Toyocom M306. 2. This is the recommended range of load capacitance at S32K_XTAL and S32K_EXTAL with respect to ground. t includes all the parasitics due to board traces, crystal and package. 3. Maximum ESR (R m ) of the crystal is 50 k 4. 0 ncludes a parasitic capacitance of 2.0 pf between S32K_XTAL and S32K_EXTAL pins. DocD17478 Rev 9 81/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 14. Slow external crystal oscillator (32 khz) electrical characteristics SN bit (S_TL register) 1 0 V S32K_XTAL 1/f LPXS32K V LPXS32K 90% 10% T LPXS32KSU valid internal clock Table 38. Slow external crystal oscillator (32 khz) electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max f SXS S R Slow external crystal oscillator frequency 32 32.76 8 40 khz g msxs V SXS SXSBAS SXS T SXSSU Slow external crystal oscillator transconductance V DD = 3.3 V ± 10%, 13 (3) 33 (3) µa/v V DD = 5.0 V ± 10% 15 (3) 35 (3) T scillation amplitude 1.2 1.4 1.7 V T scillation bias current 1.2 4.4 µa T Slow external crystal oscillator consumption T Slow external crystal oscillator start-up time 7 µa 2 (4) s 1. V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. Based on ATE Z 4. Start-up time has been measured with EPSN TYM M306 crystal. Variation may be seen with other crystal. 82/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.14 FMPLL electrical characteristics The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 39. FMPLL electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max f PLLN PLLN f PLLUT f PU f FREE t LK t LTJT PLL S R FMPLL reference clock(3) 4 64 MHz S R FMPLL reference clock duty cycle (3) 40 60 % FMPLL output clock P frequency 16 120 MHz S R System clock frequency 120 + 2%(4) MHz P Free-running frequency 20 150 MHz P FMPLL lock time Stable oscillator (f PLLN = 16 MHz) 40 100 µs FMPLL long term jitter f PLLN = 40 MHz (resonator), f PLLLK @ 120 MHz, 4000 cycles 6 (for < 1ppm) FMPLL consumption T A = 25 3 ma ns 1. V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. PLLN clock retrieved directly from 4-40 MHz XS or 16 MR. nput characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify f PLLN and PLLN. 4. f PU 120 + 2% MHz can be achieved at 125. 3.15 Fast internal R oscillator (16 MHz) electrical characteristics The device provides a 16 MHz main internal R oscillator. This is used as the default clock at the power-up of the device and can also be used as input to PLL. Table 40. Fast internal R oscillator (16 MHz) electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max f FR S R P Fast internal R oscillator high T A = 25, trimmed 16 frequency 12 20 MHz DocD17478 Rev 9 83/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 40. Fast internal R oscillator (16 MHz) electrical characteristics (continued) Symbol Parameter onditions (1) Value (2) Unit Min Typ Max (3) FRRUN FRPWD FRSTP T FRSU FRPRE FRTRM FRVAR Fast internal R oscillator high T frequency current in running mode T A = 25, trimmed 200 µa D Fast internal R oscillator high T A = 25 100 na D frequency current in power T A = 55 200 na D down mode T A = 125 1 µa Fast internal R oscillator high T frequency and system clock current in stop mode Fast internal R oscillator start-up time T A = 25 T A = 55 T A = 125 sysclk = off 500 sysclk = 2 MHz 600 sysclk = 4 MHz 700 sysclk = 8 MHz 900 sysclk = 16 MHz 1250 V DD = 5.0 V ± 10% V DD = 3.3 V ± 10% V DD = 5.0 V ± 10% V DD = 3.3 V ± 10% 2.0 5 2.0 5 Fast internal R oscillator precision after software T A = 25 1 +1 % trimming of f FR Fast internal R oscillator trimming step Fast internal R oscillator variation over temperature and supply with respect to f FR at T A = 25 in high-frequency configuration T A = 25 1.6 % µa 5 +5 % µs 1. V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. This does not include consumption linked to clock tree toggling and peripherals consumption when R oscillator is N. 84/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.16 Slow internal R oscillator (128 khz) electrical characteristics The device provides a 128 khz low power internal R oscillator. This can be used as the reference clock for the RT module. Table 41. Slow internal R oscillator (128 khz) electrical characteristics Symbol Parameter onditions (1) Value (2) Unit Min Typ Max f SR (3) SR T SRSU SRPRE SRTRM SRVAR P T A = 25, trimmed 128 Slow internal R oscillator low S frequency R untrimmed, across 84 205 temperatures Slow internal R oscillator low frequency current Slow internal R oscillator startup P time khz T A = 25, trimmed 5 µa T A = 25, V DD = 5.0 V ± 10% 8 12 µs Slow internal R oscillator precision after software trimming T A = 25 2 +2 of f SR Slow internal R oscillator trimming step Variation in f SR across temperature and fluctuation in supply voltage, post trimming 2.7 10 +10 % % 1. V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125, unless otherwise specified. 2. All values need to be confirmed during device validation. 3. This does not include consumption linked to clock tree toggling and peripherals consumption when R oscillator is N. 3.17 AD electrical characteristics 3.17.1 ntroduction Note: The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit). Due to AD limitations, the two ADs cannot sample a shared channel at the same time i.e., their sampling windows cannot overlap if a shared channel is selected. f this is done, neither of the ADs can guarantee their conversion accuracies. DocD17478 Rev 9 85/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 15. AD_0 characteristic and error definitions ffset Error SE Gain Error GE 1023 1022 1021 1020 1019 1018 1 LSB ideal = VDD_AD / 1024 (2) code out 7 6 (1) 5 4 3 (4) (5) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) ntegral non-linearity error (NL) (5) enter of a step of the actual transfer curve 2 (3) 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 ffset Error SE V in(a) (LSB ideal ) 3.17.1.1 nput impedance and AD accuracy To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low A impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device, can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple R Filter). The R filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the AD itself. 86/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics n fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being S and p 2 substantially two switched capacitances, with a frequency equal to the conversion rate of the AD, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1MHz, with S+p 2 equal to 3pF, a resistance of 330K is obtained (Reqiv = 1 / (fc*(s+p 2 )), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on S+p 2 ) and the sum of R S + R F, the external circuit must be designed to respect the following relation Equation 4 R S + R F V -------------------- 1 A --LSB R EQ 2 The formula above provides a constraint for external network design, in particular on resistive path. Figure 16. nput equivalent circuit (precise channels) EXTERNAL RUT NTERNAL RUT SHEME Source Filter urrent Limiter V DD hannel Selection Sampling R S R F R L R SW R AD V A F P1 P2 S R S Source mpedance R F Filter Resistance F Filter apacitance R L urrent Limiter Resistance R SW hannel Selection Switch mpedance R AD Sampling Switch mpedance P Pin apacitance (two contributions, P1 and P2 ) S Sampling apacitance DocD17478 Rev 9 87/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 17. nput equivalent circuit (extended channels) EXTERNAL RUT NTERNAL RUT SHEME Source Filter urrent Limiter V DD hannel Selection Extended Switch Sampling R S R F R L R SW1 R SW2 R AD V A F P1 P3 P2 S R S Source mpedance R F Filter Resistance F Filter apacitance R L urrent Limiter Resistance R SW hannel Selection Switch mpedance (two contributions R SW1 and R SW2 ) R AD Sampling Switch mpedance P Pin apacitance (three contributions, P1, P2 and P3 ) S Sampling apacitance A second aspect involving the capacitance network shall be considered. Assuming the three capacitances F, P1 and P2 initially charged at the source voltage V A (refer to the equivalent circuit reported in Figure 16): when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed. Figure 18. Transient behavior during sampling phase V S Voltage Transient on S V A V A2 V < 0.5 LSB 1 2 1 < (R SW + R AD ) S << T S V A1 2 = R L ( S + P1 + P2 ) T S t n particular two different transient periods can be distinguished: A first and quick charge transfer from the internal capacitance P1 and P2 to the sampling capacitance S occurs ( S is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which P2 is reported in parallel to P1 (call P = P1 + P2 ), the two capacitances P and S are in series, and the time constant is Equation 5 P S 1 = R SW + R AD -------------------- P + S 88/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics This relation can again be simplified considering S as an additional worst condition. n reality, transient is faster, but the A/D converter circuitry has been designed to be robust also in very worst case: the sampling time T s is always much longer than the internal time constant. Equation 6 1 R SW + R AD S «T S The charge of P1 and P2 is redistributed on S,determining a new value of the voltage V A1 on the capacitance according to the following equation Equation 7 V A1 S + P1 + P2 = V A P1 + P2 A second charge transfer involves also F (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which P2 and S were in parallel to P1 (since the time constant in reality would be faster), the time constant is: Equation 8 2 R L S + P1 + P2 n this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time T S, a constraints on R L sizing is obtained: Equation 9 8.5 2 = 8.5 R L S + P1 + P2 T S f course, R L shall be sized also according to the current limitation constraints, in combination with R S (source impedance) and R F (filter resistance). Being F definitively bigger than P1, P2 and S, then the final voltage V A2 (at the end of the charge transfer transient) will be much higher than V A1. The following equation must be respected (charge balance assuming now S already charged at V A1 ): Equation 10 V A2 S + P1 + P2 + F = V A F + V A1 P1 + P2 + S The two transients above are not influenced by the voltage source that, due to the presence of the R F F filter, is not able to provide the extra charge to compensate the voltage drop on S with respect to the ideal source V A ; the time constant R F F of the filter is very high with respect to the sampling time (T S ). The filter is typically designed to act as anti-aliasing DocD17478 Rev 9 89/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 19. Spectral representation of input signal Analog Source Bandwidth (V A ) Noise T 2 R F F (onversion Rate vs. Filter Pole) f F f 0 (Anti-aliasing Filtering ondition) 2 f 0 f (Nyquist) f 0 Anti-Aliasing Filter (f F = R Filter pole) f Sampled Signal Spectrum (f = conversion Rate) f F f f 0 f f alling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f F ), according to the Nyquist theorem the conversion rate f must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T S, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter R F F is definitively much higher than the sampling time T S, so the charge level on S cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on S ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on S : Equation 11 V A2 ----------- V A = P1 + P2 + F ------------------------------------------------------- P1 + P2 + F + S From this formula, in the worst case (when V A is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on F value: Equation 12 AD_0 (10-bit) F 2048 S Equation 13 AD_1 (12-bit) F 8192 S 90/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.17.1.2 AD electrical characteristics Table 42. AD input leakage current Symbol Parameter onditions Value Min Typ Max Unit LKG T A = 40 1 T A = 25 1 nput leakage current No current injection on adjacent pin T A = 105 8 200 P T A = 125 45 400 na Table 43. AD conversion characteristics (10-bit AD_0) Symbol Parameter onditions (1) Value Min Typ Max Unit V SS_AD0 S R Voltage on VSS_HV_AD0 (AD_0 reference) pin with respect to ground (V SS_HV ) (2) 0.1 0.1 V V DD_AD0 S R Voltage on VDD_HV_AD0 pin (AD_0 reference) with respect to ground (V SS_HV ) V DD_HV_A 0.1 V DD_HV_A + 0.1 V V ANx f AD0 t AD0_PU t AD0_S t AD0_ S P1 P2 P3 R SW1 S R S R S R Analog input voltage (3) V SS_AD0 0.1 V DD_AD0 + 0.1 V AD_0 analog frequency AD_0 power up delay 6 32 + 2% MHz 1.5 µs T Sample time (4) f AD = 32 MHz 500 ns P onversion time (5),(6) f AD = 32 MHz 0.625 f AD = 30 MHz 0.700 D AD_0 input sampling capacitance D AD_0 input pin capacitance 1 D AD_0 input pin capacitance 2 D AD_0 input pin capacitance 3 D nternal resistance of analog source 3 pf 3 pf 1 pf 1 pf 3 k µs DocD17478 Rev 9 91/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 43. AD conversion characteristics (10-bit AD_0) (continued) Symbol Parameter onditions (1) Value Min Typ Max Unit R SW2 R AD (7) NJ NL DNL FS GNE TUEP TUEX S R D nternal resistance of analog source D nternal resistance of analog source nput current njection T T Absolute value for integral non-linearity Absolute differential non-linearity urrent injectio n on one AD_0 input, differen t from the convert ed one 2 k 2 k V DD = 3.3 V ± 10% V DD = 5.0 V ± 10% 5 5 5 5 No overload 0.5 1.5 LSB No overload 0.5 1.0 LSB T Absolute offset error 0.5 LSB T Absolute gain error 0.6 LSB P Total unadjusted error (8) for precise channels, input only pins Without current injection 2 0.6 2 T With current injection 3 3 T Total unadjusted error (8) for extended channel Without current injection 3 1 3 T With current injection 4 4 ma LSB LSB 1. V DD = 3.3 V ± 10% / 5.0 V ± 10%, T A = 40 to 125, unless otherwise specified. 2. Analog and digital V SS_HV must be common (to be tied together externally). 3. V ANx may exceed V SS_AD0 and V DD_AD0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. 4. During the sample time the input capacitance S can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t AD0_S. After the end of the sample time t AD0_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t AD0_S depend on programming. 5. This parameter does not include the sample time t AD0_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. 6. Refer to AD conversion table for detailed calculations. 7. PB10 should not have any current injected. t can disturb accuracy on other AD_0 pins. 8. Total Unadjusted Error: The maximum error that occurs without adjusting ffset and Gain errors. This error is a combination of ffset, Gain and ntegral Linearity errors. 92/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Figure 20. AD_1 characteristic and error definitions ffset Error SE Gain Error GE 4095 4094 4093 4092 4091 4090 1 LSB ideal = AVDD / 4096 (2) code out 7 6 (1) 5 4 3 (4) (5) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) ntegral non-linearity error (NL) (5) enter of a step of the actual transfer curve 2 (3) 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 ffset Error SE V in(a) (LSB ideal ) DocD17478 Rev 9 93/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 44. onversion characteristics (12-bit AD_1) Symbol Parameter onditions (1) Value Min Typ Max Unit V SS_AD1 SR Voltage on VSS_HV_AD1 (AD_1 reference) pin with respect to ground (V SS_HV ) (2) 0.1 0.1 V V DD_AD1 3 SR V ANx (3), (4) SR f AD1 SR t AD1_PU SR t AD1_S T t AD1_ P S D P1 D P2 D Voltage on VDD_HV_AD1 pin (AD_1 reference) with respect to ground (V SS_HV ) Analog input voltage (5) AD_1 analog frequency AD_1 power up delay Sample time (6) VDD=5.0 V Sample time (6) VDD=3.3 V onversion time (7), (8) VDD=5.0 V onversion time (7), (6) VDD =5.0 V onversion time (7), (6) VDD=3.3 V onversion (7), (6) time VDD =3.3 V AD_1 input sampling capacitance AD_1 input pin capacitance 1 AD_1 input pin capacitance 2 V DD_HV_A 0.1 V SS_AD1 0.1 V DD_HV_A + 0.1 V DD_AD1 + 0.1 8 + 2% 32 + 2% MHz 1.5 µs 440 530 f AD1 = 32 MHz 2 f AD 1 = 30 MHz 2.1 f AD 1 = 20 MHz 3 f AD1 = 15 MHz 3.01 5 pf 3 pf 1 pf V V ns µs 94/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 44. onversion characteristics (12-bit AD_1) (continued) Symbol Parameter onditions (1) Value Min Typ Max Unit P3 D R SW1 D R SW2 D R AD D NJ SR NLP T NLS T DNL T FS T GNE T P TUEP (9) T T TUES (9) T AD_1 input pin capacitance 3 nternal resistance of analog source nternal resistance of analog source nternal resistance of analog source nput current njection Absolute ntegral non-linearity- Precise channels Absolute ntegral non-linearity- Standard channels Absolute Differential nonlinearity Absolute ffset error Absolute Gain error Total Unadjusted Error for precise channels, input only pins Total Unadjusted Error for standard channel 1.5 pf 1 k 2 k 0.3 k urrent injection on one AD_1 input, different from the converte d one V DD = 3.3 V ± 10% V DD = 5.0 V ± 10% 5 5 5 5 ma No overload 1 3 LSB No overload 1.5 5 LSB No overload 0.5 1 LSB 2 LSB 2 LSB Without current injection With current injection Without current injection With current injection 6 6 LSB 8 8 LSB 10 10 LSB 12 12 LSB 1. V DD = 3.3 V ± 10 % / 5.0 V ± 10 %, T A = 40 to 125, unless otherwise specified. 2. Analog and digital V SS_HV must be common (to be tied together externally). DocD17478 Rev 9 95/123 122

Electrical haracteristics SP564Bxx-SP56Exx 3. PA3, PA7, PA10, PA11 and PE12 AD_1 channels are coming from V DD_HV_B domain hence VDD_HV_AD1 should be within ±100 mv of VDD_HV_B when these channels are used for AD_1. 4. VDD_HV_AD1 can operate at 5V condition while V DD_HV_B can operate at 3.3V provided that AD_1 channels coming from V DD_HV_B domain are limited in max swing as V DD_HV_B. 5. V ANx may exceed V SS_AD1 and V DD_AD1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xFFF. 6. During the sample time the input capacitance S can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t AD1_S. After the end of the sample time t AD1_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t AD1_S depend on programming. 7. onversion time = Bit evaluation time + Sampling time + 1 lock cycle delay. 8. Refer to AD conversion table for detailed calculations. 9. Total Unadjusted Error: The maximum error that occurs without adjusting ffset and Gain errors. This error is a combination of ffset, Gain and ntegral Linearity errors. 3.18 Fast Ethernet ontroller M signals use MS signal levels compatible with devices operating at 3.3 V. Signals are not TTL compatible. They follow the MS electrical characteristics. 3.18.1 M Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_LK) The receiver functions correctly up to a RX_LK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. n addition, the system clock frequency must exceed four times the RX_LK frequency in 2:1 mode and two times the RX_LK frequency in 1:1 mode. Table 45. M Receive Signal Timing Spec haracteristic Min Max Unit M1 RXD[3:0], RX_DV, RX_ER to RX_LK setup 5 ns M2 RX_LK to RXD[3:0], RX_DV, RX_ER hold 5 ns M3 RX_LK pulse width high 35% 65% RX_LK period M4 RX_LK pulse width low 35% 65% RX_LK period Figure 21. M receive signal timing diagram M3 RX_LK (input) RXD[3:0] (inputs) RX_DV RX_ER M1 M2 M4 96/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.18.2 M Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_LK) The transmitter functions correctly up to a TX_LK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. n addition, the system clock frequency must exceed four times the TX_LK frequency in 2:1 mode and two times the TX_LK frequency in 1:1 mode. The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_LK, and the timing is the same in either case. This options allows the use of non-compliant M PHYs. Refer to the Fast Ethernet ontroller (FE) chapter of the SP564B74 and SP56E74 Reference Manual for details of this option and how to enable it. Table 46. M transmit signal timing (1) Spec haracteristic Min Max Unit M5 TX_LK to TXD[3:0], TX_EN, TX_ER invalid 5 ns M6 TX_LK to TXD[3:0], TX_EN, TX_ER valid 25 ns M7 TX_LK pulse width high 35% 65% TX_LK period M8 TX_LK pulse width low 35% 65% TX_LK period 1. utput pads configured with SRE = 0b11. Figure 22. M transmit signal timing diagram M7 TX_LK (input) M5 TXD[3:0] (outputs) TX_EN TX_ER M8 M6 3.18.3 M Async nputs Signal Timing (RS and L) Table 47. M Async nputs Signal Timing (1) Spec haracteristic Min Max Unit M9 RS, L minimum pulse width 1.5 TX_LK period 1. utput pads configured with SRE = 0b11. DocD17478 Rev 9 97/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 23. M async inputs timing diagram RS, L M9 3.18.4 M Serial Management hannel Timing (MD and MD) The FE functions correctly with a maximum MD frequency of 2.5 MHz. Table 48. M serial management channel timing (1) Spec haracteristic Min Max Unit M10 MD falling edge to MD output invalid (minimum propagation delay) 0 ns M11 MD falling edge to MD output valid (max prop delay) 25 ns M12 MD (input) to MD rising edge setup 28 ns M13 MD (input) to MD rising edge hold 0 ns M14 MD pulse width high 40% 60% MD period M15 MD pulse width low 40% 60% MD period 1. utput pads configured with SRE = 0b11. Figure 24. M serial management channel timing diagram M14 M15 MD (output) M10 MD (output) M11 MD (input) M12 M13 98/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics 3.19 n-chip peripherals 3.19.1 urrent consumption Table 49. n-chip peripherals current consumption (1) Value (2) Symbol Parameter onditions Typ Unit DD_HV_A(AN) D AN (FlexAN) supply current on V DD_HV_A 500 Kbps 125 Kbps Total (static + dynamic) consumption: FlexAN in loop-back mode XTAL@8 MHz used as AN engine clock source Message sending period is 580 µs 7.652 f periph + 84.73 8.0743 f periph + 26.757 DD_HV_A(eMS) D ems supply current on V DD_HV_A Static consumption: ems channel FF Global prescaler enabled Dynamic consumption: t does not change varying the frequency (0.003 ma) 28.7 f periph 3 µa DD_HV_A(S) D S (LNFlex) supply current on V DD_HV_A Total (static + dynamic) consumption: LN mode Baudrate: 20 Kbps 4.7804 f periph + 30.946 DD_HV_A(SP) D SP (DSP) supply current on V DD_HV_A Ballast static consumption (only clocked) Ballast dynamic consumption (continuous communication): Baudrate: 2 Mbit Transmission every 8 µs Frame: 16 bits 1 16.3 f periph DD_HV_A(AD) D AD supply current on V DD_HV_A V DD = 5.5 V V DD = 5.5 V Ballast static consumption (no conversion) Ballast dynamic consumption (continuous conversion) 0.0409 f periph 0.0049 f periph ma DocD17478 Rev 9 99/123 122

Electrical haracteristics SP564Bxx-SP56Exx Table 49. n-chip peripherals current consumption (1) Value (2) Symbol Parameter onditions Typ Unit DD_HV_AD0 D DD_HV_AD1 D DD_HV(FLASH) D DD_HV(PLL) D AD_0 supply current on V DD_HV_AD0 AD_1 supply current on V DD_HV_AD1 Flash + DFlash supply current on V DD_HV_AD V DD = 5.5 V V DD = 5.5 V V DD = 5.5 V Analog static consumption (no conversion) Analog dynamic consumption (continuous conversion) Analog static consumption (no conversion) Analog dynamic consumption (continuous conversion) V DD = 5.5 V 13.25 PLL supply current on V DD = 5.5 V 0.0031 f periph V DD_HV 200 µa 4 ma 300 µa 6 ma ma 1. perating conditions: T A = 25, f periph = 8 MHz to 120 MHz. 2. f periph is in absolute value. 3.19.2 DSP characteristics Table 50. DSP timing Spec haracteristic Symbol Min Value Max Unit 1 DSP ycle Time t SK Refer note (1) ns nternal delay between pad associated to SK and pad associated to Sn in master mode for Sn1->0 t S 115 ns nternal delay between pad associated to SK and pad associated to Sn in master mode for Sn1->1 t AS 15 ns 2 S to SK Delay (2) t S 7 ns 3 After SK Delay (3) t AS 15 ns 4 SK Duty ycle t SD 0.4 t SK 0.6 t SK ns 100/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 50. DSP timing (continued) Spec haracteristic Symbol Min Value Max Unit 5 Slave Setup Time (SS active to SK setup time) Slave Hold Time (SS active to SK hold time) t SUSS 5 ns t HSS 10 ns Slave Access Time (SS active to SUT valid) (4) t A 42 ns 6 Slave SUT Disable Time (SS inactive to SUT High-Z or invalid) t DS 25 ns 7 Sx to PSS time t PS 0 ns 8 PSS to PSx time t PAS 0 ns 9 10 11 12 Data Setup Time for nputs Master (MTFE = 0) Slave Master (MTFE = 1, PHA = 0) (5) Master (MTFE = 1, PHA = 1) Data Hold Time for nputs Master (MTFE = 0) Slave Master (MTFE = 1, PHA = 0) (5) Master (MTFE = 1, PHA = 1) Data Valid (after SK edge) Master (MTFE = 0) Slave Master (MTFE = 1, PHA = 0) Master (MTFE = 1, PHA = 1) Data Hold Time for utputs Master (MTFE = 0) Slave Master (MTFE = 1, PHA = 0) Master (MTFE = 1, PHA = 1) t SU 36 5 36 36 t H 0 4 0 0 t SU 0 (6) t H 9.5 0 (7) 0 (8) 1. This value of this parameter is dependent upon the external device delays and the other parameters mentioned in this table. 2. The maximum value is programmable in DSP_TARn [PSSK] and DSP_TARn [SSK]. For SP564B74 and SP56E74, the spec value of t S will be attained only if T DSP x PSSK x SSK > t S. 3. The maximum value is programmable in DSP_TARn [PAS] and DSP_TARn [AS]. For SP564B74 and SP56E74, the spec value of t AS will be attained only if T DSP x PAS x AS > t AS. 4. The parameter value is obtained from t SUSS and t SU for slave. 5. This number is calculated assuming the SMPL_PT bitfield in DSP_MR is set to 0b00. 6. For DSP1, the Data Hold Time for utputs in Master (MTFE = 0) is 2 ns. 7. For DSP1, the Data Hold Time for utputs in Master (MTFE = 1, PHA = 0) is 2 n. 8. For DSP1, the Data Hold Time for utputs in Master (MTFE = 1, PHA = 1) is 2 ns. 12 37 12 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DocD17478 Rev 9 101/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 25. DSP classic SP timing master, PHA = 0 2 3 Sx 4 1 SK utput (PL = 0) 4 SK utput (PL = 1) 9 10 SN First Data Data Last Data 12 11 SUT First Data Data Last Data Note: Numbers shown reference Table 50. Figure 26. DSP classic SP timing master, PHA = 1 Sx SK utput (PL = 0) 10 SK utput (PL = 1) 9 SN First Data Data Last Data 12 11 SUT First Data Data Last Data Note: Numbers shown reference Table 50. 102/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Figure 27. DSP classic SP timing slave, PHA = 0 SS 2 3 SK nput (PL = 0) 4 1 4 SK nput (PL = 1) 5 12 11 6 SUT First Data Data Last Data 9 10 SN First Data Data Last Data Note: Numbers shown reference Table 50. Figure 28. DSP classic SP timing slave, PHA = 1 SS SK nput (PL = 0) SK nput (PL = 1) 11 5 12 6 SUT First Data Data Last Data 9 10 SN First Data Data Last Data Note: Numbers shown reference Table 50. DocD17478 Rev 9 103/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 29. DSP modified transfer format timing master, PHA = 0 Sx 3 2 4 1 SK utput (PL = 0) SK utput (PL = 1) 4 9 10 SN First Data Data Last Data 12 11 SUT First Data Data Last Data Note: Numbers shown reference Table 50. Figure 30. DSP modified transfer format timing master, PHA = 1 Sx SK utput (PL = 0) SK utput (PL = 1) 9 10 SN First Data Data Last Data 12 11 SUT First Data Data Last Data Note: Numbers shown reference Table 50. 104/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Figure 31. DSP modified transfer format timing slave, PHA = 0 SS 2 3 1 SK nput (PL = 0) 4 4 SK nput (PL = 1) 5 11 12 6 SUT First Data Data Last Data 9 10 SN First Data Data Last Data Note: Numbers shown reference Table 50. Figure 32. DSP modified transfer format timing slave, PHA = 1 SS SK nput (PL = 0) SK nput (PL = 1) 11 5 12 6 SUT First Data Data Last Data 9 10 SN First Data Data Last Data Note: Numbers shown reference Table 50. DocD17478 Rev 9 105/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 33. DSP PS strobe (PSS) timing 7 8 PSS Sx Note: Numbers shown reference Table 50. 3.19.3 Nexus characteristics Table 51. Nexus debug port timing (1) Spec haracteristic Symbol Min Max Unit 1 MK ycle Time (2) t MY 16.3 ns 2 MK Duty ycle t MD 40 60 % 3 MK Low to MD, MSE, EVT Data Valid (3) t MDV 0.1 0.25 t MY 4 EVT Pulse Width t EVTPW 4.0 t TY 5 EVT Pulse Width t EVTPW 1 t MY 6 TK ycle Time (4) t TY 40 ns 7 TK Duty ycle t TD 40 60 % 8 TD, TMS Data Setup Time t NTDS, t NTMSS 8 ns 9 TD, TMS Data Hold Time t NTDH, t NTMSH 5 ns 10 TK Low to TD Data Valid t JV 0 25 ns 1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MK is measured from 50% of MK and 50% of the respective signal. Nexus timing specified at V DDE = 4.0 5.5 V, T A = T L to T H, and L = 30 pf with SR = 0b11. 2. MK can run up to 1/2 of full system frequency. t can also run at system frequency when it is <60 MHz. 3. MD, MSE, and EVT data is held valid until next MK low cycle. 4. The system clock frequency needs to be three times faster than the TK frequency. 106/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Figure 34. Nexus output timing 1 2 MK MD MSE EVT 3 utput Data Valid 5 EVT 4 DocD17478 Rev 9 107/123 122

Electrical haracteristics SP564Bxx-SP56Exx Figure 35. Nexus TD, TMS, TD timing 6 7 TK 8 9 TMS, TD 10 TD 3.19.4 JTAG characteristics Table 52. JTAG characteristics No. Symbol Parameter Value Min Typ Max Unit 1 t JY D TK cycle time 64 ns 2 t TDS D TD setup time 10 ns 3 t TDH D TD hold time 5 ns 4 t TMSS D TMS setup time 10 ns 5 t TMSH D TMS hold time 5 ns 6 t TDV D TK low to TD valid 33 ns 108/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Electrical haracteristics Table 52. JTAG characteristics (continued) No. Symbol Parameter Value Min Typ Max Unit 7 t TD D TK low to TD invalid 6 ns t TD D TK Duty ycle 40 60 % t TKRSE D TK Rise and Fall Times 3 ns Figure 36. Timing diagram - JTAG boundary scan TK 2/4 3/5 DATA NPUTS NPUT DATA VALD 6 DATA UTPUTS UTPUT DATA VALD 7 DATA UTPUTS Note: Numbers shown reference Table 52. DocD17478 Rev 9 109/123 122

Package characteristics SP564Bxx-SP56Exx 4 Package characteristics 4.1 EPAK n order to meet environmental requirements, ST offers these devices in different grades of EPAK packages, depending on their level of environmental compliance. EPAK specifications, grade definitions and product status are available at: www.st.com. EPAK is an ST trademark. 4.2 Package mechanical data 4.2.1 LQFP176 package mechanical drawing Figure 37. LQFP176 package mechanical drawing Seating plane A A2 0.25 mm gauge plane A1 ccc HD c A1 L k D L1 ZD ZE 132 89 133 88 b E HE 176 45 Pin 1 identification 1 e 44 1T_ME 110/123 DocD17478 Rev 9

SP564Bxx-SP56Exx Package characteristics Symbol Table 53. LQFP176 mechanical data (1) mm inches (2) Min Typ Max Min Typ Max A 1.400 1.600 0.063 A1 0.050 0.150 0.002 A2 1.350 1.450 0.053 0.057 b 0.170 0.270 0.007 0.011 0.090 0.200 0.004 0.008 D 23.900 24.100 0.941 0.949 E 23.900 24.100 0.941 0.949 e 0.500 0.020 HD 25.900 26.100 1.020 1.028 HE 25.900 26.100 1.020 1.028 L (3) 0.450 0.750 0.018 0.030 L1 1.000 0.039 ZD 1.250 0.049 ZE 1.250 0.049 q 0 7 0 7 Tolerance mm inches ccc 0.080 0.0031 1. ontrolling dimension: millimeter. 2. Values in inches are converted from mm and rounded to 4 decimal digits. 3. L dimension is measured at gauge plane at 0.25 mm above the seating plane. DocD17478 Rev 9 111/123 122

Package characteristics SP564Bxx-SP56Exx 4.2.2 LQFP208 package mechanical drawing Figure 38. LQFP208 mechanical drawing Note: Exact shape of each corner is optional. 112/123 DocD17478 Rev 9