LT Software-Selectable able Terminator FETRES Software-Selectable able Termination for: RS (V.) RS (V.) RS (V.) RS RS EI0 EI0- V. V. X. Outputs Won t Load the Line with Power Off PPLITIO S Data Networking S and DS Data Routers DESRIPTIO The LT features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS (V.) 0Ω minimum differential load, V. T-network load or an open circuit for use with RS (V.) or RS (V.) transceivers that provide their own termination. When combined with the LT, the LT forms a complete software-selectable multiprotocol serial port. data bus latch feature allows sharing of the select lines between multiple interface ports. The LT is available in a -lead SSOP., LT and LT are registered trademarks of Linear Technology orporation. TYPIL PPLITI TS DSR DD DTR RTS RL TM RXD RX TX STE TXD LL Daisy-hained ontrol Outputs LT LT R D D D D R D D D D LT 0 LL () TXD () TXD STE () STE TX () TX RX () RX RXD () RXD TM () SGND () SHIELD () RL (0) RTS () RTS DTR () DTR DD () DD DSR () DSR TS () TS D- NETOR T0
LT SOLTE MXIMM RTINGS W W W (Note ) Positive Supply Voltage ( )... V Negative Supply Voltage (V EE )....V Input Voltage (Logic Inputs)... V EE 0.V to + 0.V Input Voltage (Load Inputs)... ±V Operating Temperature Range LT... 0 to 0 LTI... 0 to Storage Temperature Range... to Lead Temperature (Soldering, sec)... 00 PKGE/ORDER I FOR V EE GND TOP VIEW M DE/DTE LTH 0 R R R R R R GND W TIO ORDER PRT NMER LTG LTIG G PKGE -LED PLSTI SSOP T JMX =, θ J = 0 /W onsult factory for Military grade parts. ELETRIL HRTERISTIS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T =. = V ±%, V EE = V ±%, T = T MIN to T MX (Notes, ) unless otherwise noted. SYMOL PRMETER DITIS MIN TYP MX NITS Supplies I Supply urrent ll Digital Pins = GND or 00 00 µ Terminator Pins R V. Differential Mode Impedance ll Loads (Figure ), V V M V (ommercial) 0 0 Ω ommon Mode Impedance ll Loads (Figure ), V V M V (ommercial) Ω ll Loads (Figure ), V V M V (Industrial) 0 Ω ll Loads (Figure ), V V M V (Industrial) 0 0 Ω R V. Differential Mode Impedance ll Loads (Figure ), V V M V (ommercial) 0 Ω ll Loads (Figure ), V M = 0V (ommercial) 0 0 Ω ll Loads (Figure ), V M = 0V (Industrial) Ω I LEK High Impedance Leakage urrent ll Loads, V V M V (ommercial) ± ±0 µ Logic Inputs V IH Input High Voltage ll Logic Input Pins V V IL Input Low Voltage ll Logic Input Pins 0. V I IN Input urrent ll Logic Input Pins ± µ Note : bsolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : ll currents into device pins are positive; all currents out of device pins are negative. ll voltages are reference to ground unless otherwise specified. Note : ll typicals are given at = V, V EE = V, T =.
LT TYPIL PERFORMNE HRTERISTIS W V. or V. Differential Mode Impedance vs Temperature V. or V. Differential Mode Impedance vs ommon Mode Voltage V. or V. Differential Mode Impedance vs Supply Voltage ( ) DIFFERENTIL MODE IMPEDNE (Ω) 0 V M = V V M = V V M = 0V V M = V DIFFERENTIL MODE IMPEDNE (Ω) DIFFERENTIL MODE IMPEDNE (Ω) 0 0 0 0 0 0 0 0 0 TEMPERTRE ( ) 0 0 OMM MODE VOLTGE (V)...0.. VOLTGE (V) G0 G0 G0 V. or V. Differential Mode Impedance vs Negative Supply Voltage (V EE ) V. ommon Mode Impedance vs Temperature V. ommon Mode Impedance vs ommon Mode Voltage DIFFERENTIL MODE IMPEDNE (Ω) OMM MODE IMPEDNE (Ω) V M = V V M = V V M = 0V OMM MODE IMPEDNE (Ω)...0.. V EE VOLTGE (V) 0 0 0 0 0 0 0 0 TEMPERTRE ( ) 0 OMM MODE VOLTGE (V) G0 G0 G0 V. ommon Mode Impedance vs Supply Voltage ( ) V. ommon Mode Inpedance vs Negative Supply Voltage (V EE ) Supply urrent vs Temperature OMM MODE IMPEDNE (Ω) OMM MODE IMPEDNE (Ω) SPPLY RRENT (µ) 0 0 0 0 0...0.. VOLTGE (V)...0. V EE VOLTGE (V). 0 0 0 0 0 TEMPERTRE ( ) G0 G0 G0
LT PIN FNTIS (Pin ): TTL Level Mode Select Input. The data on is latched when LTH is high. V EE (Pin ): Negative Supply Voltage Input. an connect directly to the LT V EE pin. (Pin ): Load enter Tap. (Pin ): Load Node. (Pin ): Load Node. (Pin ): Load Node. (Pin ): Load Node. (Pin ): Load enter Tap. (Pin ): Load Node. (Pin ): Load Node. (Pin ): Load enter Tap. GND (Pin ): Ground onnection for Load to Load. GND (Pin ): Ground onnection for Load to Load. (Pin ): Positive Supply Input..V.V. R (Pin ): Load Node. R (Pin ): Load Node. R (Pin ): Load Node. R (Pin ): Load Node. R (Pin ): Load Node. R (Pin 0): Load Node. LTH (Pin ): TTL Level Logic Signal Latch Input. When it is low the input buffers on,, M and DE/DTE are transparent. When it is high the logic pins are latched into their respective input buffers. The data latch allows the select lines to be shared between multiple I/O ports. DE/DTE (Pin ): TTL Level Mode Select Input. The DE mode is selected when it is high and DTE mode when low. The data on DE/DTE is latched when LTH is high. M (Pin ): TTL Level Mode Select Input. The data on M is latched when LTH is high. (Pin ): TTL Level Mode Select Input. The data on is latched when LTH is high. TEST IRITS Ω V S ±V OR ±V Ω, Ω V ±V S Ω F0 F0 Figure. Differential V. or V. Impedance Measurement Figure. V. ommon Mode Impedance Measurement
LT W ODE SELETIO LT MODE NME DE/DTE M R R R V./RS X 0 0 0 RS0 0 0 0 V. V. V. 0 0 V. V. Reserved 0 0 0 V. V. V. 0 0 V. V. V. X. 0 0 V. V. V. 0 V. V. V. 0 0 0 V. V. V. V. V. 0 0 V. V. V. V. V. RS0/RS/V. 0 0 V. V. V. 0 V. V. V./RS X 0 No able X V. V. V. V. V. V. X = don t care, 0 = logic low, = logic high S Ω S Ω S Ω V. Mode V. Mode Hi- Mode F0 Figure. LT Modes
LT PPLITIS INFORMTI Multiprotocol able Termination W One of the most difficult problems facing the designer of a multiprotocol serial interface is how to allow the transmitters and receivers for different electrical standards to share connector pins. In some cases the transmitters and receivers for each interface standard can be simply tied together and the appropriate circuitry enabled. ut the biggest problem still remains: how to switch the various cable terminations required by the different standards. Traditional implementations have included switching resistors with expensive relays or requiring the user to change termination modules every time the interface standard has changed. ustom cables have been used with the termination in the cable head or separate terminations are built on the board, and a custom cable routes the signals to the appropriate termination. Switching the terminations using FETs is difficult because the FETs must remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off. The LT solves the cable termination switching problem via software control. The LT provides termination for the V. (RS), V. (RS), V. (RS) and V. electrical protocols. V. (RS) Termination typical V. unbalanced interface is shown in Figure. V. single-ended generator output with ground is connected to a differential receiver with inputs ' connected to and input ' connected to the signal return ground. The receiver s ground ' is separate from the signal return. sually no cable termination is required for V. interfaces but the receiver inputs must be compliant with the impedance curve shown in Figure. In V. mode, both switches and S are turned off so the only cable termination is the input impedance of the V. receiver. GENERTOR LNED INTERNETING LE LOD LE TERMINTI ' ' ' Figure. Typical V. Interface.m S V Ω REEIVER LT V. REEIVER V Figure. V. Interface sing the LT F0 V. (RS) Termination typical V. balanced interface is shown in Figure. V. differential generator with outputs and with ground is connected to a differential receiver with ground ', inputs ' connected to, ' connected to. The V. interface requires a different termination at the receiver end that has a minimum value of 0Ω. The receiver inputs must also be compliant with the impedance curve shown in Figure. In V. mode, switch is turned on and S is turned off so the cable is terminated with a Ω impedance. I V V V.m F0
PPLITIS INFORMTI GENERTOR W LNED INTERNETING LE ' ' LOD LE TERMINTI 0Ω MIN REEIVER GENERTOR LNED INTERNETING LE ' LT LOD LE TERMINTI REEIVER Figure. Typical V. Interface ' F0 ' F0 Figure. Typical V. Interface LT V. REEIVER LT V. REEIVER S Ω S Ω k F0 I.m Figure. V. Interface sing the LT.m V V V V V Figure. V. Interface sing the LT F0 V. (RS) Termination typical V. unbalanced interface is shown in Figure. V. single-ended generator output with ground is connected to a single-ended receiver with inputs ' connected to, ground ' connected via the signal return ground to. The V. standard requires a k terminating resistor to ground which is included in almost all compliant receivers as shown in Figure. ecause the termination is included in the receiver, both switches and S in the LT are turned off. V. Termination typical V. balanced interface is shown in Figure. V. differential generator with outputs and with ground is connected to a differential receiver with ground ', inputs ' connected to, ' connected to. The V. interface requires a T-network termination at the receiver end and the generator end. In V. mode both switches and S in the LT are turned on as shown in Figure. The differential impedance measured at the connector must be 0Ω ±Ω and the impedance between shorted terminals ' and ' to ground ' must be Ω ±Ω. The input impedance of the V. receiver is connected in parallel with the T-network inside the LT, which can cause the overall impedance to fail the specification on the
LT PPLITIS INFORMTI W GENERTOR LNED INTERNETING LE ' LOD LE TERMINTI REEIVER V. DRIVER LT Ω S 0Ω Ω Ω 0Ω 0Ω ' ' 0Ω F F Figure. Typical V. Interface Figure. V. Driver sing the LT S V LT V. REEIVER Ω V I V m V V and to ground must be Ω ±Ω. For the generator termination, switches and S are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in Figure. ny mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground causing a high frequency common mode spike on the and terminals. The common mode spike can cause EMI problems that are reduced by capacitor which shunts much of the common mode energy to ground rather than down the cable. 0.m Figure. V. Receiver sing the LT F low side. However, all of Linear Technology s V. receivers meet the RS input impedance specification as shown in Figure, which insures compliance with the V. specification when used with the LT. The generator differential impedance must be 0Ω to Ω and the impedance between shorted terminals The LTH Pin The LTH pin () allows the select lines (,, M and DE/DTE) to be shared with multiple LTs, each with its own LTH signal. When the LTH pin is held low the select line input buffers are transparent. When the LTH pin is pulled high, the select line input buffers latch the state of the Select pins so that changes on the select lines are ignored until LTH is pulled low again. If the latch feature is not used, the LTH pin should be tied to ground.
LT TYPIL PPLITIS N Figure shows a typical application for the LT using the LT mixed mode transceiver chip to generate the clock and data signals for a serial interface. The LT V EE supply is generated from the LT charge pump and the select lines,, M, DE and LTH are shared by both chips. Each driver output and receiver input is connected to one of the LT termination ports. Each electrical protocol can then be chosen using the digital select lines. M M LT DE/DTE DE/DTE LTH LTH VEE V 0 +.µf LT M DE/DTE LTH 0 DTE DE TXD + RXD + TXD RXD STE + TX + STE TX N RX + N RX RX + N RX N TX + STE + TX STE RXD + TXD + RXD TXD F Figure. Typical pplication sing the LT
LT TYPIL PPLITIS N ontroller Selectable Multiprotocol DTE Port with D- onnector DTE_LL/DE_TM DTE_TXD/DE_RXD DTE_ST/DE_RX DTE_TX/DE_TX DTE_RX/DE_STE DTE_RXD/DE_TXD DTE_TM/DE_LL V 0k 0 0 LT TRL LTH INVERT SET GND L HRGE PMP D D D D R DE M 0 E +.µf V EE DE/ DTE M LT LTH 0 DTE LL D- NETOR TXD TXD STE STE TX TX RX RX RXD RXD TM SGND DE TM RXD RXD RX RX TX TX STE STE TXD TXD LL DTE_RL/DE_RL DTE_RTS/DE_TS DTE_DTR/DE_DSR DTE_DD/DE_DD DTE_DSR/DE_DTR DTE_TS/DE_RTS LTH L 0k 0 0 LT TRL LTH INVERT SET GND L HRGE PMP D D D D R DE M 0 E +.µf RL 0 SHIELD RTS RTS DTR DTR DD DD DSR DSR TS TS RL TS TS DSR DSR DD DD DTR DTR RTS RTS T0 DE/DTE M
LT TYPIL PPLITIS N able Selectable Multiprotocol DTE Port with D- onnector DTE_TXD/DE_RXD DTE_STE/DE_RX DTE_TX/DE_TX DTE_RX/DE_STE DTE_RXD/DE_TXD V 0k 0 0 LT TRL LTH INVERT SET GND L HRGE PMP D D D D R DE M 0 E +.µf V EE DE/ DTE M LT 0 LTH D- NETOR DTE TXD TXD STE STE TX TX RX RX RXD RXD SGND SHIELD DE RXD RXD RX RX TX TX STE STE TXD TXD DTE_RTS/DE_TS DTE_DTR/DE_DSR DTE_DD/DE_DD DTE_DSR/DE_DTR DTE_TS/ DE_RTS L 0k 0 0 LT TRL LTH INVERT SET GND L HRGE PMP D D D D R DE M 0 E +.µf k R k R k LE WIRING FOR MODE SELETI MODE PIN PIN V. PIN PIN EI-0, RS, N PIN V., X. RS PIN N DE/DTE 0 LE WIRING FOR DTE/DE SELETI MODE PIN DTE PIN DE N RTS RTS DTR DTR DD DD DSR DSR TS TS TS TS DSR DSR DD DD DTR DTR RTS RTS T0 Information furnished by Linear Technology orporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology orporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT PKGE DESRIPTI Dimensions in inches (millimeters) unless otherwise noted. G Package -Lead Plastic SSOP (0.0) (LT DWG # 0-0-0).0.* (0. 0.) 0..0 (0.0 0.).0.** (0.0 0.).. (0.0 0.0) 0 0. 0. (0.00 0.00) 0. 0. (0.0 0.0) NOTE: DIMENSIS RE IN MILLIMETERS * DIMENSIS DO NOT INLDE MOLD FLSH. MOLD FLSH SHLL NOT EXEED 0.mm (0.00") PER SIDE ** DIMENSIS DO NOT INLDE INTERLED FLSH. INTERLED FLSH SHLL NOT EXEED 0.mm (0.0") PER SIDE 0. (0.0) S 0. 0. (0.0 0.0) 0.0 0. (0.00 0.00) G SSOP RELTED PRTS PRT NMER DESRIPTI OMMENTS LT Single Supply RS/RS Transceiver RS Dr/Rx or RS Dr/Rx Pairs LT Multiprotocol Serial Transceiver Software Selectable Mulitprotocol Interface LT Single Supply V. Transceiver Dr/ Rx for Data and LK Signals LT Dual Supply V. Transceiver Dr/ Rx for Data and LK Signals LT Multiprotocol able Terminator, Pin ompatible to LT llows Separate RS Mode LT Multiprotocol Serial Transceiver Dr/ Rx for Data and LK Signals LT Multiprotocol Serial Transceiver Dr/ Rx for ontrol Signals and LL LT Multiprotocol Serial Transceiver Dr/ Rx for ontrol Signals, LL, RL amd TM Linear Technology orporation 0 Mcarthy lvd., Milpitas, 0- (0) -0 FX: (0) -00 www.linear-tech.com fa LT/TP 000 K REV PRINTED IN S LINER TEHNOLOGY ORPORTI