HI-HS Data Sheet September 4 FN.4 High Speed, Quad SPST, CMOS Analog Switch The HI-HS is a monolithic CMOS Analog Switch featuring very fast switching speeds and low ON resistance. The integrated circuit consists of four independently selectable SPST switches and is pin compatible with the industry standard HI- switch. Fabricated using silicon-gate technology and the Intersil Dielectric Isolation process, this TTL compatible device offers improved performance over previously available CMOS analog switches. Featuring maximum switching times of ns, low ON resistance of Ω maximum, and a wide analog signal range, the HI-HS is designed for any application where improved switching performance, particularly switching speed, is required. (A more detailed discussion on the design and application of the HI-HS can be found in Application Note AN4.) Ordering Information PART NUMBER TEMP. RANGE ( C) PACKAGE PKG. DWG. # HI-HS- - to 6 Ld CERDIP F6. HI-HS-4 - to 8 6 Ld CERDIP F6. HI-HS- to 7 6 Ld CERDIP F6. HI-HS- to 7 6 Ld PDIP E6. HI-HS-Z (See Note) to 7 6 Ld PDIP (Pb-free) E6. Features Pb-free Available as an Option Fast Switching Times -.................................... ns - t OFF................................... 4ns Low ON Resistance........................ Ω Pin Compatible with Standard HI- Wide Analog Voltage Range (±V Supplies)....... ±V Low Charge Injection (±V Supplies).......... pc TTL Compatible Symmetrical Switching Analog Current Range..... 8mA Applications High Speed Multiplexing High Frequency Analog Switching Sample and Hold Circuits Digital Filters Operational Amplifier Gain Switching Networks Integrator Reset Circuits Pinout (Switches Shown For Logic Input) HI-HS (CERDIP, PDIP, SOIC) TOP VIEW HI9PHS- to 7 6 Ld SOIC M6. A 6 A HI9PHS-Z (See Note) to 7 6 Ld SOIC (Pb-free) M6. OUT IN 4 OUT IN HI9PHS-9-4 to 8 6 Ld SOIC M6. V- 4 V+ HI9PHS-9Z (See Note) -4 to 8 6 Ld SOIC (Pb-free) M6. GND IN4 6 NC IN NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-C. OUT4 A 4 7 8 9 OUT A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or -74-74 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc., 4. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HI-HS Functional Diagram V+ LOGIC TRUTH TABLE SWITCH TTL LOGIC INPUT LEVEL SHIFTER AND DRIVER GATE SWITCH CELL SOURCE DRAIN GATE INPUT ON OFF OUTPUT V- Schematic Diagrams TTL/CMOS REFERENCE CIRCUIT SWITCH CELL V+ P4 MP4 MP4 MP44 MP4 V+ Q QN4 QN4 D4 V R4 R4 QN4 C48 QP44 QN44 QN4 V R ANALOG IN MP MN MN MP MN ANALOG OUT C49 D4.6V MP QP4 QP4 Q V- MN4 MN44 MN4 V-
HI-HS Schematic Diagrams (Continued) DIGITAL INPUT BUFFER AND LEVEL SHIFTER M N46 M P M P M P4 M P8 Q N6 Q N8 I Q I X I X4 I X Q N7 VR IX Q N9 M P M P7 M P M P6 M P9 M P M P M P Q N C R I Q M N V EE M N Q VA Q P Q P4 Q N4 Q N Q N V R Q P R R C V CC M P M P4 Q I X IX I X C FF Q P7 Q P6 Q P9 M N Q P M N M N4 M N6 M N7 M N9 M N8 M N M N M N4 Q P8 M N M N REPEAT FOR EACH LEVEL SHIFTER
HI-HS Absolute Maximum Ratings Supply Voltage (V+ to V-).............................. 6V Digital Input Voltage...................... (V+) +4V to (V-) -4V Analog Input Voltage (One Switch)....... (V+) +.V to (V-) -.V Peak Current, S or D (Pulse ms, % Duty Cycle Max).... ma Continuous Current Any Terminal (Except S or D)......... ma Operating Conditions Temperature Ranges HI-HS-............................. - o C to o C HI-HS-4.............................. - o C to 8 o C HI-HS-................................ o C to 7 o C HI-HS-9.............................. -4 o C to 8 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) CERDIP Package................. 8 PDIP Package................... 9 N/A SOIC Package................... N/A Maximum Junction Temperature Ceramic Package................................ 7 o C Plastic Package................................. o C Maximum Storage Temperature................ -6 o C to o C Maximum Lead Temperature (Soldering s)............ o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +V, -V; V AH (Logic Level High) =.4V, V AL (Logic Level Low) = +.8V, GND = V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP ( o C) - -4, -, -9 MIN TYP MAX MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Switch ON Time, (Note ) - - ns Switch OFF Time, t OFF (Note ) - 4-4 ns Switch OFF Time, t OFF (Note ) - - - - ns Output Settling Time To.% - 8 - - 8 - ns Charge Injection, Q (Note 6) - - - - pc OFF Isolation (Note 4) - 7 - - 7 - db Crosstalk (Note ) - 86 - - 86 - db Input Switch Capacitance, C S(OFF) - - - - pf Output Switch Capacitance C D(OFF) - - - - pf C D(ON) - - - - pf Digital Input Capacitance, C A - 8 - - 8 - pf Drain-To-Source Capacitance, C DS(OFF) -. - -. - pf DIGITAL INPUT CHARACTERISTICS Input Low Threshold, V AL Full - -.8 - -.8 V Input High Threshold, V AH. - -. - - V Full.4 - -.4 - - V Input Leakage Current (Low), I AL - - - - µa Full - - - - µa Input Leakage Current (High), I AH V AH = 4.V - - - - µa Full - - 4 - - 4 µa ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V S Full - - + - - + V ON Resistance, r ON (Note ) - - Ω Full - - 7 - - 7 Ω 4
HI-HS Electrical Specifications Supplies = +V, -V; V AH (Logic Level High) =.4V, V AL (Logic Level Low) = +.8V, GND = V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP ( o C) - -4, -, -9 MIN TYP MAX MIN TYP MAX UNITS r ON Match - - - - % OFF Input Leakage Current, I S(OFF) -. -. na Full - - - - na OFF Output Leakage Current, I D(OFF) -. -. na Full - - - - na ON Leakage Current, I D(ON) -. -. na Full - - - - na POWER SUPPLY CHARACTERISTICS (Note 7) Power Dissipation, P D - - - - mw Full - - 4 - - 4 mw Current, I+ (Pin ) - 4. - - 4. - ma Full - -. - -. ma Current, I- (Pin 4) -. - -. - ma Full - - 6 - - 6 ma NOTES:. V OUT = ±V, I OUT = ma.. R L = kω, C L = pf, V IN = +V, V A = +V. (See Figure ). 4. V A = V, R L = kω, C L = pf, V IN = V RMS, f = khz.. V A = V, R L = kω, V IN = V RMS, f = khz. 6. C L = nf, V IN = V, Q = C L x V O. 7. V A = V or V A = for all switches. Test Circuits and Waveforms V DIGITAL AH =.V INPUT % V AL = V % t OFF 9% 9% SWITCH OUTPUT V t OFF % TOP: Logic Input (V/Div.) BOTTOM: Output (V/Div.) HORIZONTAL: ns/div. FIGURE A. MEASUREMENT POINTS FIGURE B. WAVEFORMS
HI-HS Test Circuits and Waveforms (Continued) V+ = +V SWITCH INPUT V IN = +V SWITCH OUTPUT V O V A R L kω C L pf LOGIC INPUT 4 V- = -V V O = V IN R L R L + r ON GND C L INCLUDES C FIXTURE + C PROBE FIGURE C. TEST CIRCUIT FIGURE. SWITCH AND t OFF LOGIC INPUT (V) + + t t O O FIGURE A. LOGIC INPUT WAVEFORM FIGURE B. V IN = +V + + + t O t O FIGURE C. V IN = +V FIGURE D. V IN = V 6
HI-HS Test Circuits and Waveforms (Continued) - - - t O t O FIGURE E. V IN = -V FIGURE F. V IN = -V FIGURE. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES Application Information Logic Compatibility The HI-HS is TTL compatible. Its logic inputs (pins, 8, 9, and 6) are designed to react to digital inputs which exceed a fixed, internally generated TTL switching threshold. The HI-HS can also be driven with CMOS logic (V-V), although the switch performance with CMOS logic will be inferior to that with TTL logic (V-V). The logic input design of the HI-HS is largely responsible for its fast switching speed. It is a design which features a unique input stage consisting of complementary vertical PNP and NPN bipolar transistors. This design differs from that of the standard HI- product where the logic inputs are MOS transistors. Although the new logic design enhances the switching speed performance, it also increases the logic input leakage currents. Therefore, the HI-HS will exhibit larger digital input leakage currents in comparison to the standard HI- product. Charge Injection Charge injection is the charge transferred, through the internal gate-to-channel capacitances, from the digital logic input to the analog output. To optimize charge injection performance for the HI-HS, it is advisable to provide a TTL logic input with fast rise and fall times. If the power supplies are reduced from ±V, charge injection will become increasingly dependent upon the digital input frequency. Increased logic input frequency will result in larger output error due to charge injection. Power Supply Considerations The electrical characteristics specified in this data sheet are guaranteed for power supplies V S = ±V. Power supply voltages less than ±V will result in reduced switch performance. The following information is intended as a design aid only. POWER SUPPLY VOLTAGES ± V S ±V Minimal Variation V S < ±V V S < ±V V S > ±6V SWITCH PERFORMANCE Parametric variation becomes increasingly large (increased ON resistance, longer switching times). Not Recommended. Not Recommended. Single Supply The switch operation of the HI-HS is dependent upon an internally generated switching threshold voltage optimized for ±V power supplies. The HI-HS does not provide the necessary internal switching threshold in a single supply system. Therefore, if single supply operation is required, the HI- series of switches is recommended. The HI- series will remain operational to a minimum +V single supply. Switch performance will degrade as power supply voltage is reduced from optimum levels (±V). So it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will meet the requirements of the application. For further information see Application Notes AN, AN, AN, AN, AN4 and AN7. 7
HI-HS Typical Performance Curves 8 7 V+ = +V, V- = -V 8 7 T A = o C V+ = +8V, V- = -8V ON RESISTANCE (Ω) 6 4 o C o C - o C ON RESISTANCE (Ω) 6 4 V+ = +V, V- = -V V+ = +V, V- = -V V+ = +V, V- = -V - - - - - - FIGURE. ON RESISTANCE vs ANALOG SIGNAL LEVEL FIGURE 4. ON RESISTANCE vs ANALOG SIGNAL LEVEL.. LEAKAGE CURRENT (na)... LEAKAGE CURRENT (na).... 7 TEMPERATURE ( o C). 7 TEMPERATURE ( o C) FIGURE. I S(OFF) OR I D(OFF) vs TEMPERATURE FIGURE 6. I D(ON) vs TEMPERATURE Theoretically, leakage current will continue to decrease below o C. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. SUPPLY CURRENT (ma) 7 V+ = +V, V- = -V 6 I+ 4 I- - - - 4 6 TEMPERATURE ( o C) 8 LEAKAGE CURRENT (pa) 8 6 4 - -4-6 -8 - - -4-6 -8 - -4 - - V+ = +V, V- = -V I S(OFF) V D = V I D(OFF) V S = V -8 I DON I S(OFF) /I D(OFF) -6-4 - 4 6 8 4 FIGURE 7. SUPPLY CURRENT vs TEMPERATURE FIGURE 8. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE 8
HI-HS Typical Performance Curves (Continued) LEAKAGE CURRENT (µa) 6 4 V AL = V, V AH = V, V AH = V I AH - -4-6 -8 - - -4-6 I AH -8 - - I AL -4-6 -8 4 6 7 8 9 TEMPERATURE ( o C) LEAKAGE CURRENT (na) 9 V+ = +V, V- = -V, T A = o C 8 I 7 S(OFF) V D = V 6 I D(OFF) V S = V 4 - - - -4 - -6-7 -8-9 - -6. -. -. -4. -4. 4. 4... 6. FIGURE 9. DIGITAL INPUT LEAKAGE CURRENT vs FIGURE. LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE TEMPERATURE Theoretically, leakage current will continue to decrease below o C. But due to environmental conditions, leakage measurements below this temperature are not representative of actual switch performance. SWITCHING TIME (ns) 8 6 4 8 6 4 - - t OFF t OFF - 4 6 TEMPERATURE ( o C) 8 V+ = +V V- = -V R L = kω C L = pf SWITCHING TIME (ns) R L = kω, C L = pf, T A = o C t OFF t OFF 6 7 8 9 4 SUPPLY VOLTAGE (±V) FIGURE. SWITCHING TIME vs TEMPERATURE FIGURE. SWITCHING TIME vs SUPPLY VOLTAGE V- = -V, R L = kω C L = pf, T A = o C V+ = +V, R L = kω C L = pf, T A = o C SWITCHING TIME (ns) t OFF t OFF SWITCHING TIME (ns) t OFF t OFF 6 7 8 9 4 POSITIVE SUPPLY (V) - -6-7 -8-9 - - - - -4 - NEGATIVE SUPPLY (V) FIGURE. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 4. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE 9
HI-HS Typical Performance Curves (Continued) SWITCHING TIME (ns) V + = +V, V- = -V, R L = kω C L = pf, V AL = V, T A = o C t OFF t OFF 4 DIGITAL INPUT VOLTAGE (V) INPUT LOGIC THRESHOLD (V)....8... 6 7 8 9 4 SUPPLY VOLTAGE (±V) FIGURE. SWITCHING TIME vs INPUT LOGIC VOLTAGE FIGURE 6. INPUT SWITCHING THRESHOLD vs SUPPLY VOLTAGE CHARGE INJECTION (pc) 4 - - IN OUT V O V A Q = C L x V O C L - -4 V+ = +V, V- = -V C L = nf - - - Q CAPACITANCE (pf) 4 C D(ON) C D(OFF) OR C S(OFF) C DS(OFF) - - - FIGURE 7. CHARGE INJECTION vs ANALOG VOLTAGE FIGURE 8. CAPACITANCE vs ANALOG VOLTAGE 4 V+ = +V, V- = -V V IN = V RMS, V A = V 4 V+ = +V, V- = -V V IN = V RMS, V A = V OFF ISOLATION (db) 8 6 4 IN OUT V O V IN R L OFF ISOLATION = Log K K R L = Ω R L = kω V IN V O M FREQUENCY (Hz) M CROSSTALK (db) 8 IN OUT V O 6 V IN R L = kω 4 V O R L = kω V O CROSSTALK = Log V O K K M FREQUENCY (Hz) M FIGURE 9. OFF ISOLATION vs FREQUENCY FIGURE. CROSSTALK vs FREQUENCY
HI-HS Die Characteristics DIE DIMENSIONS 44µm x 86µm x 48µm METALLIZATION Type: CuAl Thickness: 6kÅ ±kå PASSIVATION Type: Nitride Over Silox Nitride Thickness:.kÅ ±kå Silox Thickness: kå ±kå WORST CASE CURRENT DENSITY 9. x 4 A/cm Metallization Mask Layout HI-HS A A OUT OUT IN IN V- V+ GND IN4 IN OUT4 OUT A4 A All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com