Z-PACK HS3 10 Row Vertical Plug to Right Angle Receptacle

TABLE OF CONTENTS INTRODUCTION...iii What is an EPR?...iii Why use this EPR?...iii HOW TO USE AN EPR... iv The Simulation Page... v Simulation Graphs... v Input Voltage... v Near & Far End Noise Values...vii MODEL OVERVIEW...viii The Single Line Model (SLM)...viii The Multi Line Model (MLM)...viii SIMULATION DATA... 1 Z-PACK HS3 10 Row... 1 HS3, 10 Row, Vertical Plug to Right Angle Receptacle Electrical Interconnection Performance Information... 2 MODEL WIRING PATTERNS... 3 SIMULATION LOOK-UP TABLE... 4 Specifications subject to change. Consult AMP for latest design specifications. Copyright 2000 by AMP Incorporated All Rights Reserved. AMP is a registered trademark. ii Contents Printed on Recycled Paper

INTRODUCTION The first several pages of this Electrical Performance Report (EPR) are intended to give an overview of the AMP EPR. By understanding how to apply information from an AMP EPR, system designers will be able to select the best AMP product for their application. What is an EPR? EPRs (Electrical Performance Reports) are technical documents composed of electrical simulations of connector models. Each of these simulations varies in several system parameters. EPRs are used to assist system design engineers in the selection of potential connector solutions for their particular application. While there are several non-technical issues that enter into the connector selection decision, these electrical performance criteria are becoming very important. Why use this EPR? The EPR provides system designers with fundamental data relating to the electrical performance of a connector. This data, in turn, allows the system designer to decide if the connector under analysis is the proper interconnection device for his or her application. Criteria that impact the electrical performance of a connector include wiring patterns, edge rates, system impedances and logic families. The EPR permutes these criteria one step at a time, while holding all other parameters constant. This approach reveals the effects that each change may or may not cause. If used properly, an EPR can facilitate in choosing the proper connector for an application. Furthermore, the EPR can help in selecting wiring patterns, edge rates, system impedances, and logic families within an application. iii

HOW TO USE AN EPR Following a systematic method, pertinent information can be derived from the various EPR simulations. The parametric nature of simulations can best be explained by recognizing that various factors affect coupled noise: Wiring Pattern Logic Family (excitation) System Impedance (Z o ) Signal Risetime Voltage Swing Connection Capacitance SIMULATION LOOK-UP TABLE Consolidates all simulations in the EPR to quickly find pertinent simulation(s). SIMULATION LEGEND AND NOTES Defines Simulation Look-up Table fields. Can include graphics to relate. MODEL PATTERNS Wiring patterns used for the simulations. Single-ended and differential patterns are simulated, where applicable. Select a representative model pattern that is similar to your application setup. Find the rows in the Simulation Look-Up Table that correspond to this wiring (model) pattern. In the table, you will see several parameters that vary given this model pattern. Note the simulation filename of interest, and go to that page to find graphs of electrical simulation data. iv

The Simulation Page The simulation page shows the graphical results of a simulation on a connector under defined system parameters. Referring to the figure below, it can be seen that the several parameters that effect the electro-dynamics of the connector are shown. MODEL PATTERN Shows the connections to the connector model. SIMULATION GRAPHS Provide voltage versus time information. Graphs include Input Voltage, Near and Far End Noise Voltages. MODEL PATTERN LEGEND Defines connections to the connector model. SIMULATION Defines logic family, voltage swing, and rise time used in this simulation. INTERCONNECTION Shows the simulation's system impedance, and the PAD (in the case of SMT) or plated through-hole capacitance. Simulation Graphs The value of the EPR is realized when voltage values are found on the simulation graphs. The plots of voltage versus time reveal both absolute values of voltage levels and where they occur in time. These values can help in determining the contribution or impact of the connector/connection on the system noise budget. In some occurrences, where multiple lines are monitored, a rough estimate of skew can be determined. The total noise tolerance should be determined, understanding that it is different for different logic families. Input Voltage The Input Voltage graph shows the incident and far end voltage of the connector including the connection effects (PAD or plated through hole capacitance). Overall symmetry (in the case of differential signals) can be seen. Refer to the following graph for more information: v

INPUT voltage graphs. In this case, a differential system, the INPUT voltages (VIA3 & VIA4) are plotted with the output voltages (VOA3 & VOA4) versus time. 2.4 2.2 2.0 Input Voltage [94103187] VOA4 (Output voltage, pin A4) VIA3 VIA4 VOA3 VOA4 VIA3 (Input voltage, pin A3) 1.8 VOLTAGE(mv) 1.6 1.4 1.2 1.0 0.8 VOA3 (Output voltage, pin A3) 0.6 VIA4 (Input voltage, pin A4) 0.4 0.0 0.4 0.8 1.2 1.6 2.0 TIME(ns) The voltage response (refer to the voltage swing in following figure) of the connector should approach that of the logic family as defined in the simulation area of the EPR graph pages. The propagation delay of the connector can be determined as the difference in time that the incident and far end graphs cross the same voltage level. In the case below, the propagation delay would be: propagation delay: t = t 2 t 1 2.4 2.2 2.0 Input Voltage [94103187] VIA3 VIA4 VOA3 VOA4 VIA3 (Input voltage, pin A3) 1.8 VOLTAGE(mv) 1.6 1.4 1.2 VOA3 (Output voltage, pin A3) Voltage Swing 1.0 0.8 0.6 0.4 0.0 0.4 0.8 1.2 1.6 2.0 Propagation delay of connector TIME(ns) t1 t2 vi

Near & Far End Noise Values Near and far end noise values include the effects of the return path in their determination. Simulated values are absolute and can be included in their percent contribution to the total noise budget as determined by the system designer. In the following Near End Noise Voltage figure, the effects of adjacent pairs that are out-of-phase can be seen (the +/- of two differentially driven lines). Note that similar techniques are used with the Far End Noise voltage graphs. 6 NEAR END NOISE VOLTAGE vna4b4 vnf4 5 vna4b4 Differential Voltage between pins a4 and b4 4 3 2 vnf4 Near End Noise Voltage of pin f4 1-1 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 Time(ns) To summarize, the EPR arms the system designer with simulation information from the simulation setups that closely match his or her design. This information can be effectively used to focus on follow-up simulations, and it is of great aid in selecting connector and wiring pattern candidates. vii

MODEL OVERVIEW The Single Line Model (SLM) The SLM is used to evaluate the effects of a single set of connector pins. A SLM is representative of a well referenced connector. A simulation with the SLM can show the following effects: PROPAGATION DELAY ATTENUATION REFLECTIONS DRIVE POWER TIMING IMPEDANCE Single Line Model The SLM for the connector found in this EPR is listed on the next page. Note: A SLM was NOT used to generate simulation data in this EPR. (FOR CROSSTALK, A MULTI-LINE MODEL MUST BE USED.) The Multi Line Model (MLM) The MLM (Multi-Line Model) is used in all the simulations found in this EPR. The MLM accounts for the electrostatic and electromagnetic coupling (crosstalk) as well as the common impedance noise found in a connector. Its structure couples, in three dimensions, all pins to one another. This results in a complex model that uses series resistance, inductance, coupling capacitance and inductive coupling coefficients so arranged to allow connections at both the input and output. This modeling technique effectively shows coupled noise at the expense of CPU runtime. Simulations done using the MLM will show the following information: Multi Line Model - The Fundamental Structure PROPAGATION DELAY ATTENUATION REFLECTIONS DRIVE POWER TIMING IMPEDANCE CROSSTALK COMMON MODE NOISE ELECTROSTATIC COUPLING ELECTROMAGNETIC COUPLING The fundamental MLM varies in the number of pins (rows & columns) and the number of sections. Note that faster rise times require multiple sections. To learn more about AMP Simulation capabilities, e-mail us: modeling@tycoelectronics.com URL: www.amp.com/simulation viii

FVM Footprint Via Matrix With increasing data rates, the rise-time of the signals are becoming fast enough that the footprint of a connector will significantly affect the electrical performance of an interconnect. While the structure of the connector is fixed and can be readily specified for its insertion loss characteristics in a given line environment, the connection is highly variable due to the influence of the footprint. The approach of representing the footprint with only series capacitance may no longer suffice. A challenge posed to the design engineer is how to better represent the connector footprint in a system simulation. One practical approach is to use a Footprint Via Matrix (FVM) Model. The structure of the FVM model is similar to that of the connector s matrix model; containing series Resistance and Inductance, along with inter-via mutual capacitance and inductance matrices. The inter-via matrices represent the coupling between plated through holes. In addition, the FVM model structure includes a via-to-plane capacitance matrix. The via-to-plane capacitance matrix represents the coupling between each plated through hole and its adjacent planes and traces. The FVM model values are a function of the following: (1) PCB thickness (length) (2) PCB material (Dielectric Constant and Dissipation Factor) (3) Pad and anti-pad dimensions (4) Stack-up (number of planes and spacing) (5) Trace connection location (a) a high-connected signal trace (via in full stub configuration; presenting maximum low impedance condition) (b) a mid-connected signal trace (via in half-stub, half series configuration) (c) a low-connected signal trace (via in full series configuration; presenting minimum low impedance condition) NOTE : THE FOOTPRINT VIA MATRIX MODEL IS A PRACTICAL ENGINEERING TOOL COVERING A GENERIC PCB SPECIFICATION. YOUR PARTICULAR BOARD STACKUP MAY OR MAY NOT BE FAITHFULLY MODELED BY THE EXAMPLE MODEL. Via-to-Plane Structure (Side View of VIA) Top-Connected Trace Inter-VIA Structure GND GND Mid-Connected Trace GND GND Bottom-Connected Trace ix

SIMULATION DATA Z-PACK HS3 10 Row Vertical Plug to Right Angle Receptacle 1

HS3, 10 Row, Vertical Plug to Right Angle Receptacle Electrical Interconnection Performance Information This document contains abstracts of the results of various computer simulations of electrical interconnection performance. a The HS3 10 Row connector evaluated in this report is an impedance controlled board to board connector that is ideal for high-end server, mass storage, and networking applications. The Model Pattern Orientation in this set of data represents a board to board interconnection. The simulations are run on the three column model, as shown in Section a-a, which is adequate for most wiring patterns. As shown in the Simulation Circuit Abstract figure to the right, the simulation model is a validated matrix circuit model (AMP MLM P/N MLM -1999-3681-066) which provides for the series resistance and inductance elements of each line, the electrostatic coupling between lines, and the electromagnetic coupling between lines. The model for this connector has multiple sections and is useful for digital signals with edge rates as fast as 125 ps. RS RC driven line(s) LC VS CP CP RT near end ref CP quiet line(s) RC CONNECTOR MODEL RC reference line(s) C M A BC DE FG HJ K gr1 gr2 gr3 gr4 gr5 Model Pattern Orientation (Section a-a) LC L M LC Simulation Circuit Abstract a far end ref CP RT RT The model is configured so that any position in the matrix may be assigned as a driven line, a quiet line, or a reference line. Each line can be terminated (RT) as desired, pad capacitances (CP) can be assigned as desired, with driving functions (VS) and source impedances (RS) assigned as desired. The near end and far end references are isolated to allow observation of common impedance effects of the connector. The simulation model outputs include both the electrostatic (E) and magnetic (M) crosstalk and the common mode noise contributions. This sum is reported as Near End Noise Voltage and/or Far End Noise Voltage. signal Vs Vb Backward crosstalk driven line (-) (+) (-) coupled region signal i Zc noise (+) (+) (-) Common Impedance Noise Forward crosstalk Electrostatic and Electromagnetic Crosstalk Vf 2

MODEL WIRING PATTERNS Electrical Performance Report Z-PACK HS3, 10 Row, EPR 1308506 All Signal (Single Ended) K a Q a J a a a H a a a G a A a F a a a E a Q a D a a a C a a a B a a a A a Q a 2:1 Differential Vertical (Ground towards Inside) K a Q a J a I Q a I H X X X G X X X F a A a E a I A I a I D X X X C X X X B a Q a A a I Q a I All Signal (Differential Vertical) K a Q a J a I Q a I H a A a G a I A I a I F a Q a E a I Q a I D a a a C a I a I a I B a Q a A a I Q a I 4:1 Differential Vertical (Ground Towards Outside) K X X X J a Q a H a I Q a I G a a a F a I a I a I E a A a D a I A I a I C a Q a B a I Q a I A X X X 2:1 Single Ended K a Q a J X X X H a a a G X X X F a A a E X X X D a a a C X X X B a a a A a Q a LEGEND X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I A I q Q Active (Inverted) Line Monitored Active (Inverted) Line Passive Line Monitored Passive Line 3

SIMULATION LOOK-UP TABLE (Indexed by S/G Ratio, then by Logic Family, then by Tr) Cp DH DV GI GO Logic: S/G Ratio Tr Vf Vo VMM Zo: Table Legend: Pad or Plated Through Hole capacitance Differential signal (horizontal pairs) Differential signal (vertical pairs) Grounded Lines Towards Inside Rows Grounded Lines Towards Outside Rows Logic family simulated Ratio of signal lines to reference (ground) lines Rise time of source Source final voltage Source initial voltage Via Matrix Model Characteristic Impedance Multi-Line Model Used: HSC 10319.AIS (Connector) HFP32MM (Footprint) - Daughtercard FP2_LH_M (Footprint) Backplane Simulation Tool: HSPICE v99.2 Simulation Filename Page S/G Ratio Driver Type(1) Tr (ns) Vo (Volts) Vf (Volts) Zo (Ohms) Cp (pf) 2000092101 5 All Signal CMOS 0.5 0.0 3.3 65 FVM(2) 2000092102 6 All Signal CMOS 1.0 0.0 3.3 65 FVM 2000092103 7 All Signal DV PECL 0.3 1.5 2.4 50 FVM 2000092104 8 All Signal DV Fibre-channel 0.15 1.8 2.5 50 FVM 2000092105 9 2:1 CMOS 0.5 0.0 3.3 65 FVM 2000092106 10 2:1 CMOS 1.0 0.0 3.3 65 FVM 2000092107 11 2:1 DV;GI PECL 0.3 1.5 2.4 50 FVM 2000092108 12 2:1 DV;GI Fibre-channel 0.15 1.8 2.5 50 FVM 2000092109 13 4:1 DV;GO PECL 0.3 1.5 2.4 50 FVM 2000092110 14 4:1 DV;GO Fibre-channel 0.15 1.8 2.5 50 FVM (1) DRIVER TYPE: Piece-wise linear voltage sources are used to simulate the drivers. The PWL sources are developed based on voltage swing and rise time (the dv/dt values are linear between the 10%-90% or 20%-80% points, depending on the logic s specification). (2) FVM (Footprint Via Matrix reference page ix): The FVM used for all simulations herein represents vias with mid-connected traces)for a.200 thick backplane and.100 thick load card. Plane spacing was designed to maintain 50 ohm stripline traces using 8 mil trace widths in FR4 material. 0.052 diameter circular antipads were included in the modeling. 4

SIMULATION FILENAME: 2000092101 MODEL PATTERN INPUT VOLTAGE vig2 vog2 All Signal (Single Ended) Voltage (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 3.50 3.00 2.50 2.00 1.50 1.00 0.50-0.50 K a Q a J a a a H a a a G a A a F a a a E a Q a D a a a C a a a B a a a A a Q a NEAR END NOISE VOLTAGE vne2 vna2 vnk2 LEGEND 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 20 18 16 14 12 10 8 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line 6 4 DRIVER TYP CMOS 2 NEAR END NOISE VOLTAGE vfa2 vfe2 vfk2 0.0 V to 3.3 V PWL Ramp Tr (ns): 0.5 (20%-80%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 5 4 INTERCONNECTION 65 Ohm Lines FVM* used for Cp 3 2 1-1 -2-3 -4-5 * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear Page 5

MODEL PATTERN SIMULATION FILENAME: 2000092102 All Signal (Single Ended) INPUT VOLTAGE vig2 vog2 K a Q a J a a a H a a a G a A a F a a a E a Q a D a a a C a a a B a a a A a Q a Voltage (V) 3.00 2.50 2.00 1.50 1.00 0.50-0.50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.50 LEGEND NEAR END NOISE VOLTAGE vnk2 vne2 vna2 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line 10 8 6 4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 12 DRIVER TYPE: CMOS 2 D 0.0 V to 3.3 V -2 PWL Ramp Tr (ns): 1.0 (10%-90%) FAR END NOISE VOLTAGE vfa2 vfe2 vfk2 INTERCONNECTION 65 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2 15.00 1 5.00-5.00-1 -15.00-2 Page 6

SIMULATION FILENAME: INPUT VOLTAGE 2000092103 vih2 voh2 vig2 vog2 MODEL PATTERN All Signal (Differential Vertical) Voltage (V) 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 2.60 K a Q a J a I Q a I H a A a G a I A I a I F a Q a E a I Q a I D a a a C a I a I a I B a Q a A a I Q a I NEAR END NOISE VOLTAGE vnk2j2 vnf2e2 vnb2a2 LEGEND -1-2 -3-4 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line -5 DRIVER TYP PECL -6-7 FAR END NOISE VOLTAGE vfb2a2 vff2e2 vfk2j2 1.5 V to 2.4 V PWL Ramp Tr (ns): 0.3 (20%-80%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 2 15.00 1 5.00-5.00-1 INTERCONNECTION 50 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear Page 7

MODEL PATTERN SIMULATION FILENAME: 2000092104 All Signal (Differential Vertical) INPUT VOLTAGE vih2 vig2 voh2 vog2 K a Q a J a I Q a I H a A a G a I A I a I F a Q a E a I Q a I D a a a C a I a I a I B a Q a A a I Q a I Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 LEGEND NEAR END NOISE VOLTAGE vnb2a2 vnf2e2 vnk2j2 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1 a I Active (Inverted) Line -1 A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line -2-3 -4-5 DRIVER TYPE: Fibre-channel -6 1.8 V to 2.5 V PWL Ramp Tr (ns): 0.15 (10%-90%) -7-8 FAR END NOISE VOLTAGE vfb2a2 vff2e2 vfk2j2 INTERCONNECTION 50 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 35.00 3 25.00 2 15.00 1 5.00-5.00-1 -15.00-2 Page 8

SIMULATION FILENAME: 2000092105 MODEL PATTERN INPUT VOLTAGE vif2 vof2 2:1 Single Ended Voltage (V) 3.00 2.50 2.00 1.50 1.00 0.50-0.50 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 3.50 K a Q a J X X X H a a a G X X X F a A a E X X X D a a a C X X X B a a a A a Q a NEAR END NOISE VOLTAGE vna2 vnk2 LEGEND 8 6 4 2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 10 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line DRIVER TYP CMOS -2 0.0 V to 3.3 PWL Ramp V FAR END NOISE VOLTAGE vfa2 vfk2 Tr (ns): 0.5 (20%-80%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 3 2 1-1 -2-3 INTERCONNECTION 65 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear Page 9

MODEL PATTERN SIMULATION FILENAME: 2000092106 2:1 Single Ended INPUT VOLTAGE vif2 vof2 K a Q a J X X X H a a a G X X X F a A a E X X X D a a a C X X X B a a a A a Q a Voltage (V) 3.00 2.50 2.00 1.50 1.00 0.50-0.50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.50 LEGEND NEAR END NOISE VOLTAGE vnk2 vna2 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 6 5 4 3 2 DRIVER TYPE: CMOS 1 D 0.0 V to 3.3 V -1 PWL Ramp Tr (ns): 1.0 (10%-90%) FAR END NOISE VOLTAGE vfa2 vfk2 INTERCONNECTION 65 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 15.00 1 5.00-5.00-1 -15.00 Page 10

SIMULATION FILENAME: 2000092107 MODEL PATTERN INPUT VOLTAGE vif2 vie2 vof2 voe2 2:1 Differential Vertical (Ground towards Inside) Voltage (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 K a Q a J a I Q a I H X X X G X X X F a A a E a I A I a I D X X X C X X X B a Q a A a I Q a I NEAR END NOISE VOLTAGE vnb2a2 vnk2j2 LEGEND 0.0 0.2 0.4 0.6 0.8 1.0 1.2 25.00 2 15.00 1 5.00 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line DRIVER TYP PECEL -5.00 1.5 V to 2.4 PWL Ramp V FAR END NOISE VOLTAGE vfb2a2 vfk2j2 Tr (ns): 0.3 (10%-90%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 4.00 2.00-2.00 INTERCONNECTION 50 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) -4.00-6.00-8.00-1 -12.00-14.00 GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear Page 11

MODEL PATTERN SIMULATION FILENAME: 2000092108 2:1 Differential Vertical (Ground towards Inside) INPUT VOLTAGE vif2 vie2 vof2 voe2 K a Q a J a I Q a I H X X X G X X X F a A a E a I A I a I D X X X C X X X B a Q a A a I Q a I Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 LEGEND NEAR END NOISE VOLTAGE vnb2a2 vnk2j2 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line 3 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 35.00 a I Active (Inverted) Line 25.00 A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line 2 15.00 1 5.00 DRIVER TYPE: Fibre-channel -5.00 1.8 V to 2.5 V -1 PWL Ramp Tr (ns): 0.15 (10%-90%) FAR END NOISE VOLTAGE vfb2a2 vfk2j2 INTERCONNECTION 50 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 15.00 1 5.00-5.00-1 -15.00-2 -25.00-3 Page 12

SIMULATION FILENAME: 2000092109 MODEL PATTERN INPUT VOLTAGE vie2 vid2 voe2 vod2 4:1 Differential Vertical (Ground Towards Outside) Voltage (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 K X X X J a Q a H a I Q a I G a a a F a I a I a I E a A a D a I A I a I C a Q a B a I Q a I A X X X NEAR END NOISE VOLTAGE vnc2b2 vnj2h2 LEGEND -5.00-1 -15.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 5.00 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line -2 DRIVER TYP PECL -25.00 1.5 V to 2.4 PWL Ramp V FAR END NOISE VOLTAGE vfc2b2 vfj2h2 Tr (ns): 0.3 (20%-80%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 6.00 4.00 2.00 INTERCONNECTION 50 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) -2.00-4.00-6.00 Page 13 GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear

MODEL PATTERN 4:1 Differential Vertical (Ground Towards Outside) SIMULATION FILENAME: INPUT VOLTAGE 2000092110 voe2 vie2 vid2 vod2 K X X X J a Q a H a I Q a I G a a a F a I a I a I E a A a D a I A I a I C a Q a B a I Q a I A X X X Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 LEGEND NEAR END NOISE VOLTAGE vnc2b2 vnj2h2 X Ground Line a Active (Driven) Line A Monitored Active (Driven) Line a I Active (Inverted) Line A I Monitored Active (Inverted) Line q Passive Line Q Monitored Passive Line 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 5.00-5.00-1 -15.00 DRIVER TYPE: Fibre-channel -2-25.00 1.8 V to 2.5 V -3 PWL Ramp Tr (ns): 0.15 (10%-90%) FAR END NOISE VOLTAGE vfc2b2 vfj2h2 INTERCONNECTION 50 Ohm Lines FVM* used for Cp * NOTE: FVM=Footprint Via Matrix (reference page ix) GRAPH NOTES VI - Input Voltage VO - Output Voltage VN - Near End Noise Voltage VF - Far End Noise Voltage PWL - Piece Wise Linear 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 15.00 1 5.00-5.00-1 Page 14

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