AN ENERGY EFFICIENT TRANSMITTER FOR WIRELESS MEDICAL APPLICATION

International Journal of Electronics, Communication and Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol. 3, Issue 1, Mar 2013, 117-126 TJPRC Pvt. Ltd. AN ENERGY EFFICIENT TRANSMITTER FOR WIRELESS MEDICAL APPLICATION D. JACKULINE MONI 1 & ALPHONSA THOMSON 2 1 Professor, School of electrical Sciences, Karunya University, Coimbatore, India 2 PG Scholar, School of electrical Sciences, Karunya University, Coimbatore, India ABSTRACT An energy-efficient transmitter (TX) for wireless medical applications is presented in this work. It is designed for an output radio frequency of 2.2GHz. Transmitter design mainly consist of a phase-locked loop (PLL) synthesizer with a direct frequency presetting technique and a power amplifier. The Phase-locked loop synthesizer consists of a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator(vco) and a frequency divider circuit. The frequency presetting technique used in the VCO design helps to increase the data rate of communication with low power consumption. The power amplifier is used to amplify the output signal to a sufficient power level which will ensure a transmitted signal to propagate across some distance and be received at the receiver end. The proposed transmitter is designed in 180nm technology using cadence virtuoso analog design environment. From the simulation results, the lock time of the PLL is obtained as 290ns and the transmitter achieved a power output of 1.8dBm at a lower phase noise of -98 dbc/hz @ 1MHz. KEYWORDS: Phase Frequency Detection, Frequency Presetting, Phase Noise, Power Output INTRODUCTION RF transceiver plays an important role in the wireless medical system. Most important application of RF transceiver is in the field of wireless body sensor network applications. In this application particular sensor nodes are attached to the human body and these sensor nodes are used to monitor the vital signals like heart rate, blood flow rate temperature and ECG. After obtaining the required data it will be processed and stored. Then this data will be transmitted through the transmitter by the RF transceiver to the assigned base station. Finally the information received will be sent to the health centre for further diagnosis. When comparing with the normal RF transceivers, the transceiver in medical sensor nodes has more limitations in terms of power consumption and size. The transmitter should be ultra low consumption so that it can operate for a long time period with the limited supply of energy. So the main objective is to present an energy-efficient transmitter with high data rate of communication with low power consumption. Most of the developed transmitters are coming under following three categories. In first category the transmitter is realized in mixer-based frequency up conversion architecture in [2] and [5]. The energy efficiency for this architecture is usually low due to the power hungry mixer and digital-to-analog converter in [3] and [4]. In second one the voltage controlled oscillator(vco) direct modulation architecture is adopted [7]. The direct modulation topology can achieve high data rate at low power consumption [8]. But it have a disadvantage that the VCO carrier frequency is unlocked and the loop cannot suppress the close-in phase noise. Usually in the case of open-loop topology, the periodic relocking of the VCO frequency is required which make the continuous operation difficult. In the third category the transmitter is realized in the phase-locked loop (PLL)-based architecture. The PLL-based topology [9] can improve the communication quality

118 D. Jackuline Moni & Alphonsa Thomson because the VCO is always locked by the PLL. The limitation is that the data rate is limited by the loop bandwidth in this topology. So a new transmitter which combines the VCO direct modulation mode and the PLL-based mode is introduced to make good use of their advantages. It consists of following four blocks, PLL synthesizer using direct frequency presetting technique Class-C power amplifier Digital processor Nonvolatile memory (NVM) TRANSMITTER ARCHITECTURE The transmitter is an electronic device propagates an electromagnetic signal which usually with the help of an antenna. An energy efficient transmitter (TX) for medical sensor nodes is proposed in this paper. The transmitter can operate in two modes and they are PLL-based mode and VCO direct modulation mode with ON-OFF keying/frequencyshift keying modulation [15]. It is because of its low-power and low hardware complexity. They are suitable for the design of a smart low-power portable base station. It makes the medical monitoring available at anytime and anywhere. The TX combines the voltage controlled oscillator (VCO) direct modulation mode and the PLL-based mode to make good use of their advantages. Proposed architecture block diagram is shown in Fig. 1. In this architecture, the data rate of the PLL-based mode can be increased by the frequency presetting technique [1] without increasing the bandwidth of the loop. The frequency presetting technique directly preset the frequency of VCO with small initial frequency error. This helps to avoid the tradeoff between the lock-in time and the phase noise. This technique reduces the lock-in time and increase the frequency switching speed. Thus the data rate of the transmitter is increased with low power consumption. Figure 1: Proposed Transmitter Architecture The class-c power amplifier is adopted to save the energy for transmitting. A digital processor is designed to control the operation mode of transmitter. It also help to preset the phase locked loop or voltage controlled oscillator output frequency. An ultra-low- power nonvolatile memory [11] is used. From the chip testing process the control signals and the calibration data is obtained and it is stored. This avoids the redundancy in calibration process and reduces the power consumption. As a result, the transmitter can achieve modulation with a high data rate in a high energy efficiency way.

An Energy Efficient Transmitter for Wireless Medical Application 119 The operation of the transmitter can be explained as follows. When the transmitter receives the reset signal for the first time it perform frequency autocalibration. The digital processor measure the VCO output frequency and obtain the relation between output frequency and the presetting signals C and P. After completing the autocalibration the result is stored in the non volatile memory. Then the transmitter sample the information to the external station. In VCO direct modulation PLL is off and the V a is biased to VDD/2. In the PLL based mode after the frequency presetting the low pass filter accurately tunes the frequency of VCO. So the synthesizer can settle down in very short time. The ON-OFF keying modulation can be achieved by switching the control signals V SW1 and V SW2 directly by the baseband signal. The frequency shift keying can be obtained by changing the presetting signals of the VCO and the divide ratio N of the programmable divider. DESIGN AND IMPLEMENTATION OF TRANSMITTER Phase Locked Loop A phase-locked loop(pll) is a closed loop feedback system. It sets fixed phase relationship between the phase of the output clock and the reference clock s phase. The basic block diagram of the PLL is shown in the Fig. 2. In general a PLL consists of five main blocks. They are Phase Detector or Phase Frequency Detector (PD or PFD),Charge Pump (CP), Low Pass Filter (LPF),Voltage Controlled Oscillator (VCO) and Divide by N Counter. Figure 2 : PLL Component Block Diagram The Phase frequency Detector compares the phase and also the frequency difference between the reference clock given and the feedback clock from the VCO. Depending upon the phase and frequency difference, it generates two output signals UP and DOWN. The Charge Pump circuit is used to combine both the outputs of the PFD and it gives a single output. The output of the charge pump circuit is fed to a Low Pass Filter to generate a control voltage. This DC control voltage determines the phase and frequency of the voltage controlled oscillator [15]. If an UP signal is generated then the error voltage at the output of LPF increases. This results in the increase of the output frequency of the VCO. Or else if a DOWN signal is generated then the output frequency of the VCO decreases. Then the output of VCO is fed back to the phase frequency detector in order to recalculate the phase difference.this PLL design required the following equations: Gain of VCO is determined using the equation, KVCO = 2 * 3.14(F MAX F MIN )/(V IN MAX VIN MIN ) (1) F MAX = Maximum operating frequency of VCO (maximum value that the PLL will obtain at lock time) F MIN = VCO minimum operating frequency V INMAX = Maximum input voltage to VCO

120 D. Jackuline Moni & Alphonsa Thomson V INMIN = Minimum input voltage to VCO PFD gain is designed using the following equation. KPD = I PUMP /2*3.14 (2) I PUMP = Current of Charge Pump Natural frequency is determined using equation, Wn = (2*3.14*Lock Range) / 4*3.14 = ((KPD*KVCO) / (N*C1)) 1/2 (3) C1 = Value of the largest capacitor Damping factor of PLL is = (Wn /2)*R*C1 (4) Phase Frequency Detector Phase Frequency Detector is a circuit that measures the phase and frequency difference between the signal that comes from the VCO and the reference signal. UP and DOWN are the two output signals of the PFD and its values are determined according to the phase and frequency difference of the input signals Fig. 3 shows a PFD with its inputs and outputs. The output signals of the PFD are fed to the charge pump. Type II PFD is used here which is of almost zero dead zone. Figure 3 : Phase Frequency Detector Charge Pump The inputs to the charge pump are from the phase frequency detector. The charge pump converts the phase or frequency difference information obtained from the PFD into a voltage and this voltage is used for tuning the VCO. Charge pump circuit is used to combine both the outputs of the PFD and give a single output. After this it is given to the input of the filter. The output of the charge pump is a constant current value which should be insensitive to the supply voltage variation. The value of the current always remains same but the polarity changes depending on the output signals from the phase frequency detector.

An Energy Efficient Transmitter for Wireless Medical Application 121 Figure 4 : Schematic of Charge Pump The schematic diagram of the charge pump circuit with loop filter is shown in the Fig. 4. The UP and DN are the output signals from the PFD and they are passed through the CP to get single voltage output. Loop Filter The Loop Filter used in this work is a passive loop filter. It consist of two capacitors and one resistor. The output of the filter is a voltage signal that makes the VCO to either increase or decrease its output frequency. The voltage output of the loop filter is determined by the charge of the capacitors. For this case an extra capacitor is added in parallel to the original capacitor and resistor. This capacitor helps to reduce the incoming noise from the previous components and thus reduces the lock time. LC Tank VCO An oscillator is an autonomous system which generates a periodic output without any input. Voltage Controlled Oscillators is the main component that produces the necessary frequency output of the PLL. VCO creates a frequency that matches the reference signal depending on the other PLL components. The data rate of the PLL-based mode is increased using the frequency presetting technique. The frequency presetting technique directly preset the frequency of VCO with small initial frequency error. Thus it eliminate the tradeoff between the lock-in time and the phase noise. This technique reduces the lock-in time and increases the frequency switching speed so that the data rate of the transmitter is increased with low power consumption. (a)

122 D. Jackuline Moni & Alphonsa Thomson (b) Figure 5 : LC Tank VCO Using a Presetting Module (a) Architecture (b)presetting Module Used Fig. 4 shows the proposed VCO. It consists of an LC-tank VCO shown in Fig. 4(a) and a presetting module shown in Fig. 4(a) in [1].The LC-tank VCO uses the complementary PMOS and NMOS to reduce the current needed for oscillation. A large inductor L with a high Q value is used to reduce power consumption which in turn result in the increase of loop gain of VCO [12]. Two sets of digital signals C and P which are generated from the digital processor are used to control the output frequency of VCO. The signal P controls capacitance of the LC tank and increases the desired frequency tuning range and lower VCO gain. The presetting module is controlled by a digital signal C[5:0] with the low pass filter output to produce a voltage controlled oscillator control signal. Thus the control signals can accurately preset the output frequency of the VCO and it finely tunes the frequency. Frequency Divider The basic function of the Divider is to reduce the frequency from the VCO into a value that is comparable to the Reference Signal. The divider s purpose is to scale down the frequency from the output of the voltage controlled oscillator so that the system can operate at a frequency that is higher than the reference signal. Thus the VCO has to be designed such that the output of VCO is N times the reference frequency [14]. So the output of the VCO is passed through a divide by N-counter and feedback to the input. A D -flip flop based divider has been chosen for this particular application. Power Amplifier The power amplifier is the final block in the transmit path of a transceiver. Its role is to amplify a signal to a sufficient power level. The power amplifier takes a small-amplitude signal at the output RF frequency as its input and drives a high power representation of the input into a lower impedance load [14]. Generally the load is an antenna having a resistance of 50 ohms. The PA should be able to amplify the signal to transmit signals at powers high enough for the receiver to recover the desired signal. The power level, described in dbm, is given as follows: P (dbm) =10log 10 (P) /.001W (5) Class C power amplifier in fig. 6 is chosen for various reasons. The class C amplifier is biased below its turn-on voltage. The input drives the device on for a small portion, which is less than half of the input cycle. This results a pulsed current in the device. This current is filtered to extract the fundamental frequency component, which is then passed to the resistive load. The output waveform is thus at the fundamental frequency.

An Energy Efficient Transmitter for Wireless Medical Application 123 The inductor and capacitor at the output are tuned to resonate at the RF carrier frequency [16]. At the resonant frequency a purely resistive impedance is present which maximizes the current driven to the resistive load. R OPT = (V MAX ) 2 /2P RF. (6) I RF = (2P RF /R OPT ) 1/2. (7) The Fig. 6 shows a differential structure. The drain of each transistor is equally loaded. The differential configuration leads to higher efficiency. The configuration is immune to common-mode signals and prevents any noise from the power supply Figure 6 : Class C Power Amplifier MEASURED RESULTS The proposed design is simulated using 180nm CADENCE software in analog design environment. Component schematics were drawn and simulations were performed on the PFD, divide, VCO and power amplifier in order to examine their functionality. The relation between digital presetting word and the output frequency of the voltage controlled oscillator for particular value of control signal P is measured. Also the output frequency of the VCO for varying control voltage and particular control word C with P set to 0100 is measured and plotted to get the transfer characteristics of the VCO.The VCO results an output frequency of 2.2GHz at 1.8V control voltage. The operating frequency for the simulation of the design is 100MHz with 1.8V as supply voltage. Fig. 7 shows the simulation result of the PFD/CP circuitry when CLKOUT leading that of CLKREF by 2.5ns, which resulting triggering the UP signal in PFD and that will switch the UP transistor in the charge pump(cp) charging up the load capacitor. Figure 7 : Transient Analysis of PFD/CP

124 D. Jackuline Moni & Alphonsa Thomson Reference frequency is 100MHz and the VCO output is of about 2.2GHz. So a decade counter is used. Power analysis for the frequency presetting VCO is performed and is obtained as 0.92mW and it is lower when compared to the normal VCO. Transient analysis of the PLL is performed using reference frequency as 100MHz. The lock time for this simulation is obtained as 290ns. It is shown in the fig. 8. Figure 8 : Transient Analysis of PLL The phase noise analysis of the PLL is carried out in the schematic level. The phase noise is found to be - 98dBc/Hz @ 1MHz and 158dBc/Hz @ 1GHz. From the power analysis power obtained = 1.52mW. Then calculating the output power in dbm,we get output power as 1.83 dbm. Table 1 : Measured Performance Process PLL phase noise PLL lock in time PA output power VCO PA 0.18um CMOS -98dBc/Hz @ 1MHz 290ns 1.8 dbm 1mA 1.5mW CONCLUSIONS A 2.2-GHz energy-efficient transmitter for wireless medical applications is presented in this work. The transmitter mainly consist of phase locked loop, Class-C power amplifier, Digital processor and non volatile memory. Voltage controlled oscillator with frequency presetting technique is used in this work. The frequency presetting technique can accurately preset the carrier frequency of the voltage-controlled oscillator and reduce the lock-in time of the PLL synthesizer. This increases the data rate of communication with low power consumption. So a lower lock time of 290ns is obtained. The TX achieves 1.8-dBm output power with lower phase noise of -98 dbc/hz @ 1MHz. The circuits are simulated using 180nm technology in cadence. REFERENCES 1. Qi Zhang, P.Feng, Nanjian Wu, A 2.4ghz Energy Efficient Transmitter For Wireless Medical Application in IEEE Transactions On Biomedical Circuits And Systems, Vol. 5, No. 1, February 2011

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