MEDEA+ and Embedded Systems ARTEMIS Annual Conference 2005 Paris Σ! 2365 Jürgen Deutrich Vice Chaiman of the Board MEDEA+ Applications
ARTEMIS ANNUAL CONFERENCE 2005 1. About MEDEA+ 2. MEDEA+ Projects for Embedded Systems 3. Planning the Future with Embedded Systems: a MEDEA+/ ARTEMIS Vision
1. About MEDEA+
About MEDEA+ JESSI (1989-1996) helped European companies to be back in the race in Technology MEDEA (1997-2000) strengthened R&D cooperation of System suppliers and Semiconductor manufacturers MEDEA+ (2001-2008) will help Europe to become a leader in System Innovation on Silicon thus contributing to accelerate Europe s transition into an Information Society
MEDEA+: Objectives (2000)...within the EUREKA frame of national governments, driven by industry needs in a bottom-up flexible approach involving the key European actors in the microelectronics value chain from Equipment & Materials suppliers to Semiconductor manufacturers and System Houses, incl. Universities and Research Institutes with approximately 2,500 researchers per year and a forecasted cost of approximately 500 M per year, shared between participants and Public Authorities aiming at : helping Europe to become a leader in System Innovation on Silicon
MEDEA+ snapshot E! 2365 (2001-2008) over 20,000 PYs more than 340 partners from 21 countries 25 projects successfully ended until 2004, 26 ongoing, 18 just starting 2 sub-programs, 11 work areas funding shared by partners (65%) / Nat. PAs (35%) main contributors: FR=40%, DE=18%, NL=18%, IT=7%, BE=7%, AT=3%, ES=2%, SW=1% main achievements to-date: 3 European IC cies firmly in top-10, 1 European leader for lithography equipment, solid IP base for all processes (CMOS 90nm, e-memories, SiGe, SoI, analog), design tools and libraries of dedicated cells, chip sets for advanced applications (secured smart cards, broadband access, xdsl, storage, ). More to come for security and safety, user needs,...
MEDEA+ Projects Split per Work Areas (Phase1) N. projects PersonYears A1 High speed Comms.systems 9 2126 A2 ICE terminals 4 866 A3 Smart cards for secure Internet 4 807 A4 Automotive 5 1151 A5 Design methodologies 6 1808 A6 Security "APPLICATIONS" 28 6758 T1 Enabling IC techno. for Applis 6 1415 60% directly supports Applications T2 IC technology integration 4 1549 T3 Other Equipment 5 1063 T4 Lithography 8 2820 T5 Packaging 1 45 "TECHNOLOGIES" 24 6892 TOTAL 52 13650
MEDEA+ potential contributions The future of the European microelectronics industry : a pamphlet for enhancing public support to microelectronics MEDEA+ Scientific Committee reports: Benchmark of academic systems: Europe vs. USA, Heterogeneity on silicon, Multimedia interfaces, Bio-chips, Manufacturing and Science Road mapping as a tool for programme structuring and calls for project proposals: Design Automation roadmap (release 4, July 2003) and EDA Conferences (annual) Applications Technology Roadmap (release 1, November 2003)
MEDEA+ EDA Roadmap The 4th release is published. The first document was issued in 2000, to respond the need of a symmetrical treatment of EDA issues vs. the process technology (ITRS roadmap) New domains covered in the 4th release: Virtual system simulation for formal system spec definition validated through «usages» SoC front-end from System Level to RTL Hardware Dependent Software design efficiency increase SoC top-down methodology with constraint propagation down to implementation Design for Manufacturability (fast process ramp-up for early SoC design and production in 90nm/50nm) The 5th release of the Roadmap is under preparation MEMS design
Applications Technology Roadmap A new type of Roadmap Reversal of supply and demand Starting from the envisaged needs of the end-user in 2012 Identification of enabling applications technologies that are needed for the realisation of the relevant enduser needs in 2012 The MEDEA+ Applications Technology Roadmap can be ordered on-line: http://www.medeaplus.org section: publications
MEDEA+ status, phase 1&2 (PY) 69 projects, Total for 2001-2008: 19,205 PY 344* partners 21 participating countries * companies active in more than 1 country are counted once 129 3239 219 29 1640 3878 46 63 396 7167 67 1739 419 9 4 10 6 42 18 10 76
EUROPE at work for nanoelectronics EUREKA Participation in MEDEA+ projects 25% 27% 39% Universities SMEs 9% Institutes Large Groups MEDEA+ Countries (21) SMEs= 14% of all Person.Year resources Other countries in EUREKA (total 35)
2. MEDEA+ Projects for Embedded Systems
MEDEA+ Projects for Embedded Systems 1. The scope of 18 Projects out of 36 in MEDEA+ Applications is related to Embedded Systems 2. Themes of the projects are System Level Design, EDA for Systems with very high complexity, Communications, ICT-Terminals, Automotive, Smart Cards, Security 3. The following extract from the projects SpeAC and INCA are just two examples
MEDEA+Projects for Embedded Systems Specification and Algorithm/Architecture-Co Co-Design for Highly Complex Applications in Automotive and Communication SpeAC
SPeAC Overall Goal and Benefits Goal Define and test the new system-level design flow with solutions provided by the project and with real applications Y model Common approach within different domains and between partners Collect design practices from system houses (to define next generation SLD flows and tools) ; task 1.0 not covered due to funding situation Benefits Approach getting more maturity (a lot of new solutions but not mature yet) Shared directions for SLD between partners Proven on real applications Productivity increase and/or Management of new system complexity
SpeAC: The System-level Design Flow Module View Platform/Chip View Embedded System Requirements Simulink, UML, SystemC, C/C++, SDL Spec. Abstraction Level Untimed Design Entry/Modeling Techniques C/C++ SystemC Matlab Simulink abstracted timing & power models (transaction-based) Implement Models Characterize Perf. & Power Platform Function System Integration Platform Architecture Perf. & Power Analysis & Platform Conf. Communication Refinement Communication Integration and Synthesis SoC Platform Configuration Design Export Embedded Software RTL/analog Software Assembly Hardware Assembly Timed/Clocked Implementation Models Emb. SW Integration Hier. RTL Design Plan. Hardware/Software Co-Verification Synthesis, Place & Route Hierarchical Implementation
SpeAC Application: Exposure Control Unit (ECU) for Driver assistance Digital image sensor Image frames 256 x 512 Pixel 256 grey scales gain, offset integration time Histogram calculation DP-RAM Threshold calculation I 2 C Interface gain, offset integration time Control unit dark_index bright_index ECU
SpeAC-Application: Power Windows System Software Power stages Bus interface Lin/CAN C/C++ Model SystemC Model µc Gate Driver DC Motor Hall sensor ISS Model Link
MEDEA+ Projects for Embedded Systems The goal of INCA is To develop new Physical layer components and systems for advanced xdsl (Digital Suscriber Line) systems To set up a demonstrator of a xdsl platform, transmitting highspeed multiple sources data-stream over the existing copper line To bring chipsets and systems developed within INCA to the Open market To position European Industries of Semi-conductor, OEM, Telecom in the leading edge
INCA What is the key to success? Advanced DSP algorithms System Architecture Expertise SoC design methodology & tools Powerful engines DSP & MCU cores Broad range of silicon process Advanced xdsl chipsets System Integration Xdsl demonstrators Advanced Error Correction codes Modem SW expertise Optimal HW/SW partitionning Broad IP blocks portfolio World-class volume manufacturing
Major silicon realisations in INCA Line driver for ADSL- CPE0.35µm BiCMOS (real: ESAT-KU Leuven) Line driver for ADSL- COBCD5 process (real: ST Micro) 4-port ADSL-CO digital chip0.13µm CMOS (real: Alcatel Micro)
3. Planning the future with Embedded Systems a MEDEA+ / ARTEMIS Vision
The global approach: Applications domains and Enabling technologies European Leadership in Nanoelectronics Applications domains at 2015 horizon Technology modules System EDA Enabling Technologies More of Moore Enabling Technologies More than Moore
Three main domains More of Moore Compute More than Moore Interact with user and environment Embedded Systems ARTEMIS
More of Moore - one pillar of the initiative for leadership Up-side : microelectronics everywhere Health Aeronautic s Computer Consumer Telecom Data Storage Automotive
More than Moore - one pillar of the initiative for leadership interactivity interactivity computing computing awareness awareness autonomy autonomy connectivity connectivity
Candidates for European leadership Initiatives Applications Domains Ensure personal and public Safety and Security Personal Emergency Systems Information based Society Broadband Services without compromise Provide highest quality Media Entertainmen t Accessible anywhere & anytime Secure Data Access for the mobile Society Wireless Access more comfort but as easy as Wired Social and Health Solutions for the ageing Society Individual Health monitoring Towards 100% Safety on the Road Safe Driving Protection against Crime and Terrorism Next Generation Networks Content Protection Encryption for Security Real-Time Diagnostics Safe Cars Secure Home Environment Service Roaming by seamless Networks Content with best Quality (e.g. HDTV) Protected and always available Internet Bio-chips, Body- Sensors Fail-safe incar communication Enabling Technologies More of Moore More than Moore Low power Design Automation
The Technology Lifestyle of the 21st Century: is centered around Home Networks and the need for security Entertainment Home Office Kids Home control Home Gateway Internet xdsl
Social & Health Solutions : MT/LT Goals Source: IEEE Dec 2004
Solutions for the aging society Semiconductors implanted in the human body can improve quality of life Hearing aid implanted Artificial vision Pacemaker Artificial liver Identification Insulin dispenser
Auto safety: vision and challenge Accident-free road traffic Much can be done in the few moments before an impending accident Predictive safety systems supporting driver s reaction Active interaction in case of no driver s reaction EU: To halven the road toll/year within 10 years
Auto safety: the answer A car cocoon Networked Cars
R&D cooperation towards better efficiency 1 Europe 1 Agenda ETP examples: ENIAC for Nanoelectronics FP7 JTI for ETP EUREKA Artemis for Embedded systems National ETP: European Technology Platform for building-up Strategic Research Agenda JTI: Joint Technology Initiative for implementation and execution of R&D projects