Topics for Project, Diploma, Bachelor s, and Master s Theses This is only a selection of topics. Further up-to-date thesis offers are available on the following web page: http://www12.cs.fau.de/edu/dasa/
Automatic Integration of Hardware Accelerators for MPSoCs The increasing complexity of embedded systems also necessitates a rise in the level of abstraction of the design flow. To facilitate this, the SystemC language, a C++ based class library and de facto industrial standard, is used to model embedded systems at the Electronic System Level (ESL). In this thesis, you will use SystemC to model a simple fractal viewer as a test application at the electronic system level (ESL). Based on this application, you will learn how to automatically transform the SystemC description into running hardware using an OpenRISC CPU with the ecos real time operating system. To speed up the fractal computation, you are required to integrate dedicated hardware accelerators into the automatically generated software solution. The goal of this thesis is the extension of the automatic design flow tools developed at the Chair for Hardware/Software Co-Design, such that integration of the hardware accelerators can be performed automatically, hence, increasing the design productivity of the ESL design flow significantly. Prerequisites: Basic C++-knowledge required Type of Work: Theory (10%), Conception (30%), Implementation (60%) Supervisor: Joachim Falk (falk@cs.fau.de), Tobias Schwarzer (tobias.schwarzer@cs.fau.de)
Uncertainties during Reliability Analysis of MPSoCs input x Ever shrinking device structures are one of the main reasons for a gro- wing inherent unreliability of embedded system components. The small device structures are susceptible to, e.g., environmental changes like cosmic rays or to manufacturing tolerances. Besides these effects, further uncertainties are present: Varying input profiles and errors during system analysis itself. The research project CRAU at the Chair for Hardware/Software Co-Design aims at considering these uncertainties during the reliability analysis of Multi-Processor Systems-on-Chip (MP- SoCs). environment e system This work shall investigate basic technique required for modeling of uncertainties. For the various kinds of uncertainties, models shall be manufacturing derived and their impact on the system analysis evaluated. Based on these results, the employed analysis techniques are to be extended accordingly. One of the fundamental question is when and how to use, for example, upper and lower bounds, distributions, or quantiles to model the analysis results under the influence of uncertainties. m y Prerequisites: Type of Work: Supervisors: Basic JAVA-knowledge helpful The work has theoretical (formal considerations of uncertainties) as well implementation aspects (implementation of the uncertainty models and extension of the analysis techniques) and can be focussed based on personal preferences. Michael Glaß (glass@cs.fau.de)
Modeling and Evaluation of Partial Networking The electrical and electronic system architecture is in a rebuilding phase. The requirement to lower the energy consumption of the car leads to the integration of new technologies. Beside possibilities at ECU-layer, more and more cross-system approaches are used. One of these possibilities is partial networking. The specific disabling of functionality and shutdown of components leads to a reduction of the power consumption. However, it requires additional methods for coordinating the overall systems. To evaluate the expected system behavior and other parameters early in the design process, the Chair for Hardware/Software Co-Design has developed a SystemC-based framework. With its help, a virtual prototype of the E/E-architecture can be build and used for a simulation-based evaluation of the overall system. Furthermore, the framework already provides models for various system aspects. The goal of this work is to extend existing work within the virtual prototyping of automotive E/E-architectures with models for partial networking techniques. Moreover, the impact of partial networking in conjunction with different networking techniques to energy consumption and timing behavior should be evaluated. Prerequisites: Type of Work: Supervisor: Knowledge of C/C++ Theory (30%), Conception (20%), Implementation (50%) Sebastian Graf (sebastian.graf@informatik.uni-erlangen.de) Lehrstuhl fu r Informatik 12
Speeding Up Success Tree Analysis of Embedded Systems Embedded systems are an indispensable part of our every-day life. Malfunctioning in these systems have consequences ranging from annoying computer crashes, loss of data and services to financial or even human life losses. Such impacts are getting worse as systems become more complex and pervasive. So, the design of reliable systems is essential to ensure that future systems perform correctly despite rising levels of complexity and uncertainties caused by environmental changes like cosmic rays or manufacturing tolerances. The main context of this work is to analyze the reliability of embedded systems at design time by means of so-called success trees. This work is part of the CRAU project which focuses on system-level reliability analysis and design of reliable embedded systems. Currently, different techniques for reliability analysis of these systems have been proposed in the chair of Hardware/Software Co-Design. In this thesis, the student should be involved with parallelizing the evaluation of one of these techniques based on success trees to speed-up the analysis. The parallelization can be implemented using different tools, for example OpenMP. As a second part of the work, the number of required sampling points for the Monte Carlo-based success tree evaluation shall be reduced by designing and implementing an adaptive sampling algorithm. Prerequisites: Basic knowledge in Java appreciated Type of Work: Theory (30%), Conception (20%), Implementation (50%) Supervisor: Hananeh Aliee (hananeh.aliee@informatik.uni-erlangen.de)
Comparing ESL Modeling Frameworks for Mobile Communication Services. Modern electronic systems are ever more complex, with an increasing number of features and tighter constraints on power consumption. The quick evaluation of architectural choices is a very important step in the design process of such systems. To achieve this, a system specification at the Electronic System Level (ESL) is nowadays the first choice. The Chair for Hardware/Software Co-Design develops the SystemCo- Designer framework that is tailored to the ESL design of embedded systems. In this thesis, an application from the mobile communication domain given in the SystemCoDesigner framework shall be reimplemented in another ESL design framework from the literature. This aims at comparing (I) the performance and power consumption numbers of the models and (II) the design complexity and the modeling effort for each framework. This thesis contributes to an ongoing research project together with Intel Mobile Communications GmbH and the Institute for Electronics Engineering (LTE). Requirements: Programming experience in C/C++ or Java Type of Work: Theory (30%), Conception (20%), Implementation (50%) Contact: Rafael Rosales (rafael.rosales@cs.fau.de)
High-Level-Synthesis for Medical Image Processing Developing for the FPGA platform in medical applications has the advantage of easier certification, when compared to software-solutions, the time necessary for development is, however, significantly longer due to the cumbersome development flow of FPGA designs. Design tool developers have been struggling for years to close this so-called productivity gap. Xilinx, one of the major FPGA manufacturers, has recently released a C-based high-level synthesis framework, called Vivado HLS, as part of its integrated design environment for FPGA development. As opposed to the classic hardware development process, high-level synthesis (HLS) aims at closing the productivity gap between hardware and software development, as well as to make the hardware development process more accessible to those not yet familiar with the details of the FPGA platform. The goal of this thesis is to testdrive this new set of tools in order to implement algorithms from medical image processing on the FPGA and to compare the results to existing implementations on CPUs and GPGPUs. Required Skills: Good knowledge C/C++, basic knowledge of VHDL or Verilog a plus Nature of work: Theory (30%), Conception (20%), Implementation (50%) Contact: Moritz Schmid (moritz.schmid@fau.de)
Development of a FPGA-based, dynamic reconfigurable satellite radio system with a high reliability against Single-Event-Effects The design of ASIC circuits for digital signal processing applications in satellite systems is time consuming and expensive. Therefore recently the use of FPGAs is considered in order to reduce development times of modern satellite systems. The ability of reconfiguration of FPGAs allows to make lastminute changes in the circuit design during design time and to adapt to new requirements of the signal processing applications during the whole life cycle of the satellite. During operation in space the FPGA is encountered with cosmic ray showers, which may lead to Single-Event-Effects like undesired bit flippings in the configuration memory. With these occurring bit flippings the reliability of the circuit is not guaranteed. The goal of this work is to improve the reliability of these circuits by using dynamic partial reconfiguration. During the work on the thesis different CAD software tools for dynamic reconfiguration have to be analyzed and evaluated. The thesis will be jointly supervised by the chair Informatik 12 and the Fraunhofer IIS. Prerequisites: Good VHDL programming skills and experience in the FPGA design flow, knowledge of digital signal processing for data transmission is beneficial. Type of Work: Theory (20%), Conception (30%), Implementation (50%) Supervisors: Bernhard Schmidt (bernhard.schmidt@informatik.uni-erlangen.de)
Combining TMR (Triple Modular Redundancy) with partial reconfiguration for communication satellites Fraunhofer IIS is currently involved in the German Heinrich Hertz communications satellite mission (H2Sat), which is due for launch into orbit in 2017. One element of the mission s in-orbit validation (IOV) capability is a reconfigurable on-board processor (OBP) which Fraunhofer IIS has developed for communication applications. Its main components are four state-of-the-art radiation-hardened Virtex5-QV FPGAs with the most recent technology for space applications. Beam NW heavy ion, high energy p To reduce the impacts of solar particle effects Triple Modular Redundancy (TMR) is used. The goal of this work is to analyze and to evaluate the operation of TMR in combination with partial reconfiguration. caption: forward link return link Beam SW Beam SE Using both design strategies at the same time implemented with different CAD software tools is a challenging task. During the work on the thesis the dependencies among the CAD software tools have to be analyzed, to be understood and to be controlled. Prerequisites: Basic knowlegde of FPGAs, VHDL and synthesis tools Type of Work: Theory (30%), Conception (20%), Implementation (50%) Supervisors: Robért Glein (robert.glein@iis.fraunhofer.de) Bernhard Schmidt (bernhard.schmidt@informatik.uni-erlangen.de) Beam NE gamma/ x ray H2Sat
Automatic Tool Flow Creation for Performance Measurements in Embedded Systems The rising complexity of embedded systems also necessitates a rise in the level of abstraction of the design flow. To facilitate this, the SystemC language, a C++ based class library and de facto industry standard, is used to model embedded systems at the electronic system level (ESL). One of the requirements of an ESL design flow is the ability to take performance measurements at this abstraction level. The chair of Hardware/Software Co-Design has a design flow, which transforms models in a certain subset of SystemC into a virtual platform. The virtual platform consists of SystemC modules and an instruction set simulator. In this thesis, the transformation step from a SystemC ESL model into a virtual platform will be extended by an automatic generation of performance measurement infrastructure. This infrastructure should be usable to extract performance measurements for each of the components which make up the SystemC ESL model of the embedded system. Prerequisites: Basic C++-knowledge helpful Type of Work: Theory (20%), Conception (30%), Implementation (50%) Supervisor: Joachim Falk (falk@cs.fau.de)
Development of a Visualization and Debugging Environment for MPSoC Prototypes As the technology is shifting from few-core to many-core systems, designers face many challenges to ensure future advances in computer architecture and programming models that are nothing short of reinventing computing. To tackle this problem, new architectures, languages and algorithms are required. Therefore a new parallel paradigm, called Invasive Computing has been proposed that utilizes the processing resources depending on the application requirements. In order to debug and verify the functionality of such complex massively parallel systems, powerful debugging and visualization environments are needed that are capable of illustrating the system status precisely. This thesis involves the conceptual design and the development of a visualization and debugging environment for very large Multi-Processor System-on-Chip (MPSoC) architectures, consisting of hundreds to thousands of small processors, and its integration within a graphical user interface. Such an environment should aggregate different hardware monitors of a system and transfer them through a suitable communication interface to a host workstation, where the transferred data is visualized by the graphical user interface. Prerequisites: Knowledge of C/C++ and JAVA, skilled HDL languages Type of Work: Theory (20%), Conception (20%), Implementation (60%) Supervisors: Vahid Lari, Srinivas Boppu ({vahid.lari, srinivas.boppu}@cs.fau.de)
Transformation from Simulink to SystemC MATLAB/Simulink is a modeling and simulation platform, which is currently heavily used in the industry sector crossing multiple domains, such as automotive industry, telecommunication, semiconductor. It offers functional simulation and code generation directly from its graphical block diagrams. For most embedded systems, however, non-functional properties such as the timing behavior play also an essential role. To cope the non-functional properties, the chair for Hardware/Software Co- Design has developed a system-level description modeling language which is based on SystemC. The goal of this work is to develop a code generator that transforms Simulink block diagrams (consist of standard blocks, stateflow blocks and toolbox blocks ) to corresponding SystemC descriptions. An existing automotive application - Brake-by-Wire serves as the test case. Prerequistes: Programming skills in C/C++ Nature of work: Theory (30%), Conception (30%), Implementation (40%) Supervisor: Liyuan Zhang (liyuan.zhang@cs.fau.de)
Boost FPGA Performance by using High Clock Frequencies The utilization of the used FPGA resources in time is rather low compared to an ASIC due to the lower clock frequency. The efficiency of FPGA resources (lookup tables) can be increased by using designs with many pipeline stages combined with a very high clock frequency. However, designs with clock frequencies up to 500 MHz needs sophisticated placement and routing techniques to hold the timing constraints. In this work, the automatic insertion of pipeline stages in data paths after synthesis and the usage of high clock frequencies should be investigated. The overall goal is to increase the efficiency and performance of FPGAs. The data paths of critical parts of a design should be analyzed and additional pipeline stages should be automatic inserted. Moreover, the placement and routing of these pipeline stages should be investigated in order to reach a high clock frequency. Prerequisites: Good knowledge in FPGA design flow Type of Work: Theory (30%), Conception (40%), Implementation (30%) Supervisor: Daniel Ziener (daniel.ziener@cs.fau.de)
Increasing FPGA-Lifetime by Dynamical Reconfiguration Ever shrinking device structures allow on the one hand more complex systems, whereas on the other hand this trend results in an increased susceptibility of modern embedded systems to radiation and temperature-dependent aging effects. This holds also true for future FPGA devices which suffer from the heat produced from computation intensive modules. These modules accelerate the local FPGA aging. Dynamical reconfiguration could help to distribute these high-active modules in a way that the wear is equalized over the FPGA area. By using this technique, the lifetime of the FPGA can be increased significantly. Unit1 In this thesis, the local FPGA temperature dispensation should be estimated at run-time and modeled with the help of expected activities on certain modules. This temperature information can be used by a method which is developed at our chair to determine a better module placement with respect to FPGA aging. Prerequisites: Good knowledge in software programming (e.g., Java or C++) Type of Work: Theory (30%), Conception (40%), Implementation (30%) Supervisor: Daniel Ziener (daniel.ziener@cs.fau.de)