Intel Xeon E3-1230V2 CPU Ivy Bridge Tri-Gate 22 nm Process

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Intel Xeon E3-1230V2 CPU Ivy Bridge Tri-Gate 22 nm Process 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com

Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc. 2013 all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. DLF-1302-801 23545CYAN Revision 1.0 Published: February 8, 2013

Table of Contents 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Device Summary 1.5 Executive Overview 1.6 Analyzed Cells Measurement Summary 2 Device Identification 2.1 Package and Die Photographs 3 Characteristics of the Device Analyzed 3.1 Intel E3-1230V2 4 Digital Library Characteristics 4.1 Primary Functional Cells 4.2 Lower Metal Layer Samples 4.3 Area Percentage Utilization 4.4 Gross and Actual Density 4.5 Track Height 4.6 Filler Cells 5 References 6 Statement of Measurement Uncertainty and Scope Variations

Overview 1-1 1.1 List of Figures 2 Device Identification 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package X-Ray 2.1.4 Die Markings 2.1.5 Die Photograph 2.1.6 Die Photograph Metal 0 3 Characteristics of the Device Analyzed 3.1.1 Annotated Die Photograph Metal 0 3.1.2 Analyzed Area in Graphics Processor 4 Digital Library Characteristics 4.1.1 Inverter Metal 0 4.1.2 Flip-Flop Metal 0 4.1.3 2 Input NAND Gate Metal 0 4.1.4 2 Input NOR Gate Metal 0 4.2.1 Sample Area Metal 1 4.2.2 Sample Area Metal 2 and Via 2 4.2.3 Sample Area Metal 3 4.3.1 Medium Density Sample of Standard Cell Library Metal 0 4.4.1 Minimum Size 2 Input NAND Gate Metal 0 4.5.1 Standard Cell Library Track Height Sample Metal 2 4.5.2 Standard Cell Library Row Height Sample Metal 0 4.6.1 Sample Annotated Metal Fill 1 Metal 0 4.6.2 Sample Annotated Metal Fill 2 Metal 0 4.6.3 Sample Decoupling Capacitor 1 Metal 0 1.2 List of Tables 1.3.1 Device Identification 1.4.1 Device Summary 1.5.1 Executive Overview 1.6.1 Analyzed Cells Measurement Summary

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