separator IC with AFC BA0 / BA0F The BA0 and BA0F separate the synchronization signals from a video signal and output the horizontal and vertical synchronization signals (HD and VD), and the composite synchronization signal (Sync-out). The HD and VD pulse phase difference is guaranteed. Applications TVs and VCRs Features ) Built-in AFC circuit. ) HD and VD phase difference guaranteed. ) Low power dissipation. (approx. mw) Absolute maximum ratings (Ta = C) BA0 (DIP) ) Low external parts count. ) -pin DIP / SOP package. ) Horizontal free-run frequency does not require adjustment. Parameter Symbol Limits Unit Power supply voltage Max..0 V Power dissipation Pd 00 mv Operating temperature Topr 0 ~ C Storage temperature Tstg ~ C Reduced by mw for each increase in Ta of C over C. BA0F (SOP) Parameter Symbol Limits Unit Power supply voltage Power dissipation Max. Pd.0 V 0 mw Operating temperature Storage temperature Topr 0 ~ C Tstg ~ C When mounted on a 0mm 0mm PCB board, reduced by.mw for each increase in Ta of C over C. Recommended operating conditions (Ta = C) Parameter Symbol Min. Typ. Max. Unit Operating power supply voltage.. V
BA0 / BA0F Block diagrams H. OSC PHASE COMP SEPA V. SEPA Pin descriptions Pin No. Function Horizontal oscillator resistor HD output output (open collector) VD output GND Video input Power supply Phase comparator output Input / output circuits k k pin pin 00µA pin k Fig. Fig. Fig. k k k 0k pin 00 pin k pin 0µA k k k Fig. Fig. Fig.
BA0 / BA0F Electrical characteristics (unless otherwise noted Ta = C and ) Parameter Symbol Min. Typ. Max. Unit Conditions Quiescent current IQ.0.. ma pin open Minimum synchronization separation level Vsyn-Min. 0.0 0. VP-P pin terminated with Ω resistor Pulse voltage, LOW VP-L 0. 0. V pins, Pulse voltage, HIGH VP-H..9 V pins, (Horizontal) free-running frequency fh-o.9.. khz No input signal, I = open Capture range fcap ±. ±.9 khz Lock-in phase difference HD, VD phase difference HD pulse width VD pulse width THPH.0 0.0 µs pin pin THVD.0. 0.0 µs pin pin THD... µs pin TVD 90 0 0 µs pin Not designed for radiation resistance. Measurement circuit 0.0µ Video In p µ 9k µ A µ 0k II 00p 0k V T V T V T 0k Fig. Circuit operation () Synchronization separation circuit Detects the charging current to a externally-connected capacitor, and performs synchronization separation. () Horizontal oscillation circuit When a video signal is input, it is synchronized with Hsync by the PLL. The horizontal free-running frequency is determined by external resistor R..0E fh-o = [khz] R () Vertical synchronization separation circuit When a video signal is input, synchronization signal separation is done over the vertical synchronization pulse interval.
BA0 / BA0F VIN, HD and VD timing charts Vertical synchronization pulse interval / H NTSC signal Odd field (IN) NTSC signal Even field (IN) VD (OUT) HD, VD phase difference HD Odd field (OUT) HD Even field (OUT) Fig. () The rise and fall positions for VD are basically the same for both odd and even fields. () HD shifts by / H during the odd and even field interval. () Only the odd field is given for the specification.
BA0 / BA0F Application example R = V C 00p R 0k = V 0k H. OSC 0k PHASE COMP C p R 0k C µ C µ C 0.0µ HD VD V. SEPA SEPA R 0k C µ 000p C R 0 Vsig By configuring the circuit enclosed in the dotted line to that in the diagram on the right, you can decrease the lock-in time and increase the capture range. Fig.9 R 0k C p R 0k C- 0.µ C- 0.µ When SEPA output only is used. HD and VD unused. = V R 0k = V C C 0k H. OSC PHASE COMP µ 0.0µ HD SEPA R C µ 0k R 0 Vsig VD V. SEPA 000p C Fig. 0 () Connect pin to GND via a 0kΩ (approx.) resistor. Leave pins, and open. () output polarity (pin ) is positive. () The delay time for rising edge of the output (pin ) with respect to the falling edge of Sync for the Vsig input signal (pin ) is 0ns (reference value). () The delay time for falling edge of the output (pin ) with respect to the rising edge of Sync for the Vsig input signal (pin ) is 0ns (reference value). Attached components Resistor R should have a tolerance of ± %, and a temperature coefficient of 00ppm or lower.
BA0 / BA0F Electrical characteristic curves CURRENT : ICC (ma) 0.0.0.0 CURRENT : ICC (ma).0..0..0..0. 0 0 00 HORIZONTAL FREQUENCY : f (khz)...0......0. POWER SUPPLY VOLTAGE (V) POWER SUPPLY VOLTAGE (V) Fig. Quiescent current vs. power supply voltage Fig. Quiescent current vs. temperature Fig. Horizontal free-running frequency vs. power supply voltage HORIZONTAL FREQUENCY : f (khz)....0.... HD PULSE WIDTH : HD (µs).....0... NTSC VD PULSE WIDTH : VD (µs) 0 0 0 0 0 90 0 NTSC 0 0 00 0 0 00 0 0 00 Fig. Horizontal free-running frequency vs. temperature Fig. HD pulse width vs. temperature Fig. VD pulse width vs. temperature HD VD PULSE TIMING (µs) 0 0 0 0 0 0 0 NTSC FREQUENCY : f (csp. lock) (khz) 0 lock cap cap lock FREQUENCY : f (csp.lock) (khz) 0 lock cap cap lock 0 0 0 00 0..0. 0 0 0 00 POWER SUPPLY VOLTAGE (V) Fig. HD, VD phase difference vs. temperature Fig. Capture range / lock range vs. power supply voltage Fig. 9 Capture range charging / lock range vs. temperature
BA0 / BA0F SIGNAL - LOCK IN TIME (ms) 00 00 flock =.khz POWER LOCK IN TIME (ms) 00 00 00 00 00 00 flock =.khz 0 9 0 0 9 0 FREQUENCY (khz) FREQUENCY (khz) Fig. 0 Time from no signal to pull in Fig. Time from power on to pull in Operation notes Make the ground line as thick as possible. Keep power supply noise to a minimum. External dimensions (Units: mm) BA0 BA0F 9. ± 0..0 ± 0.. ± 0.. ± 0. 0.Min.. ± 0... 0. ± 0. 0 ~ 0. ± 0.. ± 0.. ± 0. 0.. ± 0.. 0. ± 0. 0.Min. 0. ± 0. 0. DIP SOP
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