Getting the FLI Lead Out Thomas J. De Bonis Assembly & Test Technology Development Technology and Manufacturing Group
Lead has been used in flip chip FLI for decades. RoHS Exemption 15 was enacted in recognition of the challenge. Traditional High-Lead Bumps Lead-Tin Solder Copper Pad Copper Bump Tin-Silver-Copper Solder Copper Pad Lead-free* Advanced Bump Metallurgy Intel has solved the technical challenge. Here is the story 2
Driving Environmental Sustainability Reduction in Hazardous Substances Lead Free Lead-frame & BGA 2003 90nm Flip Chip Lead- Free BGA & Socket 2005 65nm Flip Chip Lead-Free die bump 45nm Flip-Chip Lead-Free Process* Intel Shakes the Lead Out Sumner Lemon, PC World, May 23, 2007 Chip giant will quit using lead in CPUs, starting with the Penryn line. Intel Corp. will stop using lead in its upcoming microprocessors, eliminating one of the most toxic components used in semiconductors from its product line. 45nm Flip-Chip Lead-Free Process* No Halogenated Flame Retardants** 200,000,000 units shipped with Pb-Free* FLI 2007 2009 2011. Some EU RoHS exemptions for lead may apply to other components used in the product package **Applies only to halogenated flame retardants & PVC in components. Halogens are below 900 PPM bromine & 900 PPM chlorine. 3
Where was the Pb in Intel components? Flip-Chip Bump/FLI Pb socket Capacitor Solder Pb Pb Pin Grid Solder Pb Solder Replacements* Pins SnSb ~1998 LSCs SnSb ~1998 Balls SnAg 2003 DSCs SnAg 2004 Bumps Cu 2006 FLI Cu/SnAg 2007 Pb Flip-Chip Bump/FLI Capacitor Solder Pb Printed Circuit Board Flip-Chip Pin Grid Array (FC-PGA) Solder Balls Pb Flip-Chip Ball Grid Array (FC-BGA) 4
Flip-Chip Package First Level Interconnect FLI or Bump Flip Chip BGA Package 5
Pb-free* Flip-Chip Technology Challenges Low-K ILD Cracking Flip-Chip Bump Solder Selection Crack Under Fill Voids FLI Opens / Bridging Solder Joint Quality Many Challenges had to be overcome to remove the remaining ~5% of of Lead (Pb) 7
Pb-free* Flip-Chip Technology Challenges Keys to success: Material selection. Integrated design rules. Defect and flaw elimination. Co-optimizing die, package, process. Flip-Chip Bump 8
Pb-free* Flip-Chip Challenge: Solder Criteria: Match/Exceed Eutectic SnPb solder in yield and reliability Material requirements Low cost supplier and Intel VF manufacturability Compatible with CAM reflow Optimal for FLI stress, wetting to Cu bumps and Bump IMAX performance Good solder fatigue performance Extendible to future technologies SAC: >220 C PbSn: 183 C Cu/Sn Sn-Pb Pb-Free* Flip-Chip Bump Comparison of bump IMAX performance between Pb-free* FLI and Cu/Sn-Pb 9
Pb-free* Flip-Chip Challenge: Flux High activity FLI flux needed to reduce solder oxides/ interfacial voids Low flux out gassing at TAL: reduced solder voiding Low Residue at high Peak Temp: reduced under fill voiding Chemical compatibility with die passivation / solder resist / under fill New Flux Old Flux Under Fill Voids Flip-Chip Bump Solder Joint Quality 10
Pb-free* Flip-Chip Challenge: Opens Reduced solder wicking and collapse at chip attach lead to electrical opens Solution: High activity flux Tight substrate incoming bump height uniformity (Mean bump ht-min bump ht) must be < average collapse at Chip Attach Cu- SAC (Pb-free* solder) Flip-Chip Bump FLI Opens / Bridging Cu- SnPb 11
Pb-Free* Flip Chip Challenge: ILD ILD Strength Joules/m2 example silicon cross-section SiO 2 Low-K Flip-Chip Bump Low-K ILD Cracking SiO 2 = Silicon Dioxide ILD = Inter-Layer lectric K = dielectric constant which measures the relative permittivity of a material. 12
Pb-free* Flip-Chip Challenge: ILD Delam CTE 2.6ppm/ C2 Pb-free: Higher M.P Higher Yield Stress 20ppm/ C (shrinks more than die while cooling) Flip-Chip Bump Low-K ILD Cracking Solutions: Defect Control Design Rules Materials Process 13
Pb-free* Flip-Chip Challenge: ILD delam ends here tensile ILD delam PASSIV BUMP compressive SEM image CSAM imaging and Hammer Tests were used to identify process conditions and design features to manage the increased FLI stress CSAM images Flip-Chip Bump Low-K ILD Cracking 14
Pb-free* Flip-Chip Challenge: Edge Delam Metal Interconnects with Low-κ lectric Cracking/Delamination Higher stress from stiffer FLI leads to die edge delamination Edge Edge Stress (MPa) Stress Peel Principle Low-K ILD Edge Delam Under fill LASER ablation is used to control edge defects and flaw size 15
Summary 16
Pb-free* Flip Chip FLI Challenge: Higher chip join temperature. Stiffer First Level Interconnect joint. Keys to success: Material selection. Integrated design rules. Defect and flaw elimination. Co-optimizing die, package, and process. Over 200 Million Flip Chip units have been shipped with Pb-free* FLI 17