Institutionen för systemteknik

Institutionen för systemteknik Department of Electrical Engineering Examensarbete A Self-compensated, Bandwidth Tracking Semi-digital PLL Design in 65nm CMOS Technology Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet av Mitesh Yogesh LiTH-ISY-EX--12/4597--SE Linköping 2012 Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden Linköpings tekniska högskola Linköpings universitet 581 83 Linköping

A Self-compensated, Bandwidth Tracking Semi-digital PLL Design in 65nm CMOS Technology Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet av Mitesh Yogesh LiTH-ISY-EX--12/4597--SE Handledare: Examinator: Dr. J Jacob Wikner isy, Linköpings universitet Markus Dietl & Puneet Sareen Texas Instruments Deutschland GmbH Dr. J Jacob Wikner isy, Linköpings universitet Linköping, 21 augusti 2012

Avdelning, Institution Division, Department Elektroniksystem Department of Electrical Engineering SE-581 83 Linköping Datum Date 2012-08-21 Språk Language Svenska/Swedish Engelska/English Rapporttyp Report category Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport ISBN ISRN LiTH-ISY-EX--12/4597--SE Serietitel och serienummer Title of series, numbering ISSN URL för elektronisk version http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85143 Titel Title A Self-compensated, bandbredd spårning Semi-digital PLL Design i 65nm CMOS-teknik A Self-compensated, Bandwidth Tracking Semi-digital PLL Design in 65nm CMOS Technology Författare Author Mitesh Yogesh Sammanfattning Abstract In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specifications change with a change in the reference frequency and in most cases, requires careful re-design of some of the PLL blocks. This thesis describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-compensated, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 1.6 GHz in 65nm CMOS technology. This design can be used for a wide range of reference frequencies without redesigning any block. The bandwidth can be fixed to some fraction of the reference frequency during design time. In this thesis, the PLL is designed to make the bandwidth track 5% of the reference frequency. Since this PLL is self-compensated, the PLL performance and the bandwidth remains same over PVT corners. Nyckelord Keywords PLL, semi-digital, Bandwidth tracking, Adaptive bandwidth, Compensation, PVT, Self-Bias, charge-pump, VCO, 65nm

Abstract In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specifications change with a change in the reference frequency and in most cases, requires careful re-design of some of the PLL blocks. This thesis describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-compensated, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 1.6 GHz in 65nm CMOS technology. This design can be used for a wide range of reference frequencies without redesigning any block. The bandwidth can be fixed to some fraction of the reference frequency during design time. In this thesis, the PLL is designed to make the bandwidth track 5% of the reference frequency. Since this PLL is self-compensated, the PLL performance and the bandwidth remains same over PVT corners. iii

Acknowledgments I would not have been able to achieve what I did with this thesis without the constant support from these people, to whom I would like to convey my heartfelt gratitude. First and foremost, I would like to thank Markus Dietl and Puneet Sareen, my supervisors at Texas Instruments, for providing me with an opportunity to work with them and for their continuous mentoring, patience and constant support. I did learn a lot from them. I would also like to extend my gratitude towards my teacher, my guide, supervisor and examiner, Dr. J Jacob Wikner, Universitetslektor in the Department of electronics system at Linköpings universitet. He has been an inspiration. I would like to thank my parents, my sister and the almighty for their constant emotional support throughout. Finally, a big THANK YOU to all my friends in Bangalore, Linköping and Freising for keeping my spirits high during my stay in Germany and Sweden. Linköping, August 2012 Mitesh Yogesh v

Contents List of Figures List of Tables Notation ix xii xiii I Background 1 Introduction 3 1.1 Conventional Charge-Pump Based PLLs............... 4 1.1.1 Phase Frequency Detector................... 4 1.1.2 Charge Pump.......................... 5 1.1.3 Loop Filter............................ 6 1.1.4 Voltage Controlled Oscillator................. 6 1.1.5 Qualitative Description of Conventional PLL........ 7 1.2 Semi-Digital PLL Architecture..................... 8 1.2.1 The Storage Cells........................ 8 1.2.2 The VCO............................. 10 1.2.3 The Charge-Pump........................ 10 1.2.4 Semi-digital PLL: Working Principle............. 10 1.2.5 Qualitative Description of Semi-digital PLL......... 12 II Motivation & Solution 2 Current Design & Problem Statement 17 2.1 Current Implementation........................ 17 2.1.1 Phase Frequency Detector................... 18 2.1.2 Charge Pump.......................... 18 2.1.3 Voltage Controlled Oscillator................. 19 2.1.4 Storage Cells........................... 20 2.1.5 Top Level PLL.......................... 21 vii

viii CONTENTS 2.1.6 Shortcomings of the Current Design............. 22 2.1.7 Problem Statement....................... 25 3 Proposed New Design 27 3.1 Design Changes............................. 27 3.1.1 Proposal 1: Self-compensated Current Sources....... 27 3.1.2 Proposal 2: Voltage Tracking OPAMP based Charge-Pump 30 3.1.3 Proposal 3: Topological Matching............... 35 III Results 4 Results 53 4.1 Simulation Results of Proposal 2.................... 53 4.1.1 Locking Waveforms....................... 53 4.1.2 CP Active Pull-back Voltage.................. 54 4.1.3 I cp Compesation......................... 56 4.1.4 Period Jitter........................... 57 4.1.5 Bandwidth Tracking...................... 58 4.1.6 Power Consumption...................... 60 4.2 Simulation Results of Proposal 3.................... 61 4.2.1 Locking Waveforms....................... 61 4.2.2 VCO and CP Reference Current Co-relation......... 63 4.2.3 I cp Compensation........................ 63 4.2.4 K prop Compensation...................... 65 4.2.5 Period Jitter........................... 66 4.2.6 Bandwidth Tracking...................... 67 4.2.7 Power Consumption...................... 70 5 Conclusion 71 5.1 Conclusions............................... 71 5.2 Future Work............................... 73 IV APPENDIX Bibliography 79

List of Figures 1.1 Block diagram of a conventional PLL.................. 4 1.2 A simple PFD circuit........................... 5 1.3 A sample PFD timing diagram..................... 5 1.4 A conceptual CP circuit......................... 6 1.5 A simple loop filter circuit........................ 6 1.6 A simple 5-stage ring oscillator VCO.................. 7 1.7 A simple model of a conventional charge-pump PLL......... 7 1.8 Block diagram of a semi-digital PLL.................. 9 1.9 Block diagram of the storage cells................... 9 1.10 A conceptual block diagram of the VCO for semi-digital PLL... 10 1.11 A conceptual block diagram of the CP for semi-digital PLL..... 11 1.12 A comparison between active damping and RC damping...... 11 1.13 Illustration of storage cell dynamics.................. 12 1.14 Typical waveforms of a semi-digital PLL............... 12 1.15 A simple model of a semi-digital charge-pump PLL......... 13 2.1 PFD waveforms when (a) F sys leads F ref & (b) F ref leads F sys.... 18 2.2 Schematic of the current CP....................... 18 2.3 Schematic of the RES_BREECHING circuit.............. 19 2.4 Schematic of the current VCO circuit.................. 19 2.5 Schematic of the OSC_PROP_P circuit................. 20 2.6 Schematic of the OSC_PROP_N circuit................. 20 2.7 Schematic of the level-shifter circuit.................. 21 2.8 Schematic of the storage cell circuit................... 21 2.9 Schematic of the REFF_CURR circuit.................. 22 2.10 Schematic snapshot of the current PLL top level........... 22 2.11 Mathcad simulation of equation 1.11 for current design at F ref =500 MHz.................................... 23 2.12 Mathcad simulation of equation 1.11 for current design at F ref =1600MHz........................................ 24 2.13 Mathcad simulation of equation 1.11 showing peaking at 150 MHz and a way to solve it by increasing dt step............... 24 2.14 Mathcad simulation of equation 1.11 showing adaptive bandwidth. 25 3.1 Schematic of the modified OSC_PROP_P circuit........... 28 ix

x LIST OF FIGURES 3.2 Schematic of the modified OSC_PROP_N circuit........... 28 3.3 K prop /F ref measurement at 1.6 GHz.................. 28 3.4 K prop /F ref measurement at 600 MHz.................. 28 3.5 K prop /F ref measurement at 500 MHz.................. 29 3.6 Proposal 1: modified charge-pump schematic............. 29 3.7 Initial chip bandwidth measurements for F ref from 667 MHz to 1.6 GHz.................................. 30 3.8 Charge-pump with the voltage tracking Opamp........... 31 3.9 Schematic of the OPAMP........................ 31 3.10 Simulation waveforms showing the mismatch of the UP and DOWN currents in the present charge-pump................. 32 3.11 Simulation waveforms showing matched UP and DOWN currents of the proposal:2 charge-pump design................. 32 3.12 VCO gain curve around 200 MHz................... 33 3.13 VCO gain curve around 1600 MHz................... 33 3.14 Simulation waveforms showing the tracking of the VP and the SP nodes................................... 34 3.15 Simulation waveforms showing the scaling of I cp with F ref of 200 MHz, 800 MHz and 1600 MHz..................... 34 3.16 Closed loop response with the Proposal:2 CP at different reference frequencies................................ 35 3.17 Proposal 3: charge-pump schematic.................. 36 3.18 Proposal 3: charge-pump UP/DOWN current matching...... 37 3.19 Proposal 3: schematic of a VCO cell.................. 37 3.20 Proposal 3: schematic of a VCO TOP.................. 38 3.21 Proposal 3: VCO phase noise analysis comparison with the current VCO.................................... 38 3.22 New v/s old VCO swing at 40 MHz.................. 39 3.23 New v/s old VCO swing at 1600 MHz................. 39 3.24 Schematic of the new level shifter circuit............... 40 3.25 Comparison of current consumption by the old and new level shifter........................................ 40 3.26 Error function with a divider...................... 41 3.27 Error function without a divider.................... 41 3.28 Schematic of the Frequency Detector (FD) circuit.......... 42 3.29 Example waveforms of the Frequency Detector (FD) circuit.... 43 3.30 Schematic of the storage cell with FLL mode............. 43 3.31 dt step measurement waveforms for S1 to S5.............. 44 3.32 dt step measurement waveforms for S6 to S19............. 44 3.33 Proposal 3: K prop measured at 400 MHz................ 45 3.34 Proposal 3: K prop measured at 800 MHz................ 45 3.35 Proposal 3: K prop measured at 1600 MHz............... 46 3.36 Proposal 3: simulation waveforms showing the scaling of I cp with F ref at 400 MHz, 800 MHz and 1600 MHz.............. 47 3.37 Proposal 3: closed loop transfer function............... 47

LIST OF FIGURES xi 3.38 Sample top level waveforms illustrating the dynamics of the FLL mode................................... 48 3.39 The new PLL top level schematic snapshot.............. 49 4.1 Proposal 2: locking and static offset at 200 MHz........... 54 4.2 Proposal 2: locking and static offset at 800 MHz........... 54 4.3 Proposal 2: locking and static offset at 1600 MHz.......... 55 4.4 Proposal 2: pull-back voltage at 200 MHz, 800 MHz and 1.6 GHz. 55 4.5 Proposal 2: I cp measured at 200 MHz in different PVT corners... 56 4.6 Proposal 2: I cp measured at 800 MHz in different PVT corners... 56 4.7 Proposal 2: I cp measured at 1600 MHz in different PVT corners.. 57 4.8 Proposal 2: period jitter at 400 MHz, 800 MHz and 1600 MHz... 58 4.9 Proposal 2: loop bandwidth at 200 MHz in different PVT corners. 59 4.10 Proposal 2: loop bandwidth at 800 MHz in different PVT corners. 59 4.11 Proposal 2: loop bandwidth at 1.6 GHz in different PVT corners.. 60 4.12 Proposal 2: worst case average current consumption......... 60 4.13 Proposal 3: locking and static offset at 400 MHz........... 61 4.14 Proposal 3: locking and static offset at 800 MHz........... 62 4.15 Proposal 3: locking and static offset at 1600 MHz.......... 62 4.16 Proposal 3: VCO and Charge pump reference current tracking... 63 4.17 Proposal 3: Charge pump current measurement at 400 MHz.... 64 4.18 Proposal 3: Charge pump current measurement at 800 MHz.... 64 4.19 Proposal 3: Charge pump current measurement at 1600 MHz... 65 4.20 Proposal 3: K prop measurement in different PVT corners...... 66 4.21 Proposal 3: period jitter at 400 MHz, 800 MHz and 1600 MHz... 67 4.22 Proposal 3: Bandwidth at 400 MHz.................. 67 4.23 Proposal 3: Bandwidth at 800 MHz.................. 68 4.24 Proposal 3: Bandwidth at 1600MHz.................. 68 4.25 Proposal 3: I cp measurement for bandwidth of 10% of F ref..... 69 4.26 Proposal 3: Bandwidth measurement with double the I cp...... 69 4.27 Proposal 3: average current measurements at 400 MHz, 800 MHz and 1.6 GHz............................... 70 5.1 Proposal 2: Bandwidth tracking graph................ 72 5.2 Proposal 3: Bandwidth tracking graph................ 73 5.3 Desired OPAMP specifications..................... 77 5.4 OPAMP characteristics......................... 78

List of Tables 1.1 PFD state diagram when F ref leads F f b initially [Razavi, 2005].. 5 1.2 PFD state diagram when F ref lags F f b initially [Razavi, 2005]... 5 2.1 Simulated parameters for current design used to generate the plots in figure 2.11 at F ref =500 MHz..................... 23 2.2 Simulated parameters for current design used to generate the plots in figure 2.12 at F ref =1600 MHz.................... 24 3.1 Simulated parameters for proposal:2 design used to generate the mathcad plots in figure 3.16...................... 35 3.2 Simulated parameters for proposal:2 design used to generate the mathcad plots in figure 3.37...................... 46 4.1 Proposal 2: simulated static offset.................... 53 4.2 Proposal 2: charge pump current in different PVT corners..... 57 4.3 Proposal 2: period jitter......................... 58 4.4 Proposal 2: simulated loop bandwidth................. 58 4.5 Proposal 2: avg current consumption in strong corner........ 60 4.6 Proposal 3: static offset measured at different PVT corners..... 61 4.7 Proposal 3: charge pump current in different PVT corners..... 65 4.8 Proposal 3: K prop compensation.................... 66 4.9 Proposal 3: period jitter......................... 66 4.10 Proposal 3: Bandwidth......................... 69 4.11 Proposal 3: Bandwidth with double the I cp.............. 70 4.12 Proposal 3: worst case avg current consumption in strong corner. 70 5.1 OPAMP measured parameters..................... 78 xii

Notation Abbreviations nmos pmos cmos pll cp vco pfd I cp F sys F ref K prop K step dt step pvt fll dff fd Definition N-channel Metal Oxide Semiconductor P-channel Metal Oxide Semiconductor Complimentary Metal Oxide Semiconductor Phased Locked Loop Charge Pump Voltage Controlled Oscillator Phase Frequency Detector Charge-pump current PLL output frequency Reference frequency Proportional gain (Hz/V) Step gain (Hz/step) Storage cell time constant Process, Voltage, Temperature Frequency Locked Loop D Flip-Flop Frequency Detector xiii

Part I Background

1 Introduction Phase Locked Loops (PLLs) are one of the basic building blocks of most modern electronics systems. PLL is a closed loop control system which produces an output clock which is both frequency and phase aligned to an incoming reference clock signal. The basic blocks of a PLL consists of a phase detector (PD) and an oscillator. In simple words, the phase detector compares the instantaneous phase of the reference and the output clock signals and gives out signals which indicate whether the output clock leads or lags the reference signal in phase. These signals from the PD are then given as input to a variable oscillator whose output frequency can be controlled by a control signal (which, here will be given by the PD) to either increase or decrease the output frequency until the two signals both match in phase and frequency. Once this is achieved, the loop is said to be in lock.since real life electronic components are not ideal, there is a possibility that the output clock signal drifts out of lock eventually and hence the loop continues to compare the two signals even when in lock. PLLs are used in a wide spectrum of applications like, High quality frequency synthesizers in communication systems Clock recovery units in high speed serial data links Clock generators or clock multipliers in digital systems Clock de-skewing in digital systems Jitter and noise reduction and in clock distribution systems among others. 3

4 1 Introduction Owing to the popularity and exhaustive use-cases of the PLL, it has been a topic of constant research in the electronics design community coming up with new architectures and applications. This work uses the so called Semi-Digital architecture. 1.1 Conventional Charge-Pump Based PLLs A conventional PLL consists of a Phase/Frequency Detector (PFD), a Charge- Pump (CP), a loop filter, a Voltage Controlled Oscillator (VCO) and in most cases a Divider as shown in figure 1.1. Figure 1.1: Block diagram of a conventional PLL. The PFD is basically a digital block which compares the instantaneous phase of the reference signal (F ref ) and the feedback clock (F f b ) and generates an UP or a DOWN (dn) signal, depending on whether the F f b lags or leads F ref in phase and frequency. These UP and DOWN signals are converted to corresponding current pulses by the CP. This current will either charge or discharge a capacitor at the output of the CP depending on the UP and DOWN signals. The loop filter is a low pass filter which determines the closed loop dynamics of the loop such as the pull-in range, lock range, loop bandwidth, phase-margin (damping) etc. The output of the loop filter which is now a voltage is given to a VCO whose output frequency is directly proportional to the input voltage. In most applications, the output of the VCO is fed to a frequency divider and the output of the divider is fed back to the PFD. This way, it is possible to generate multiples of the reference frequency at the output (like in frequency multipliers). The following sections describes in brief the implementation and working of the different blocks described above. 1.1.1 Phase Frequency Detector A Phase Frequency Detector circuit can detect both phase and frequency differences between the reference and the feedback clock. The basic principle of operation can be explained using the state table 1.1 and table 1.2 below. When both the clocks are in phase and the PLL is in lock, the PFD still requires to give some output, which here will be a small pulse on both UP and DOWN on every reference clock cycle, whose width is equal to the delay in the AND logic plus the CLR to Q delay of the DFF.

1.1 Conventional Charge-Pump Based PLLs 5 F ref F f b UP DOWN 0 0 0 0 0 > 1 0 > 0 0 > 1 0 > 0 X > X 0 > 1 1 > 0 0 > 0 Table 1.1: PFD state diagram when F ref leads F f b initially [Razavi, 2005]. F ref F f b UP DOWN 0 0 0 0 0 > 0 0 > 1 0 > 0 0 > 1 0 > 1 X > X 0 > 0 1 > 0 Table 1.2: PFD state diagram when F ref lags F f b initially [Razavi, 2005]. The Circuit diagram and a sample timing diagram of a typical PFD is shown in figure 1.2 and figure 1.3 respectively. Figure 1.2: A simple PFD circuit. 1.1.2 Charge Pump Figure 1.3: A sample PFD timing diagram. A Charge Pump (CP) is a circuit which converts the digital UP and DOWN signals into corresponding analog current pulses. These current pulses are of a constant magnitude but they vary in duty cycle (or pulse width) depending on the phase error between the F ref and F f b. The current pulses are then used to charge or discharge a capacitor which eventually converts the current into corresponding control voltage for the VCO. A conceptual circuit diagram of a CP is shown in figure 1.4.

6 1 Introduction A good charge-pump design would have a good matching of both the UP and DOWN currents. The matching directly affects the performance of the PLL and also the static phase offset at the output in the locked state. 1.1.3 Loop Filter Figure 1.4: A conceptual CP circuit. The loop filter is a low pass filter used to filter out the high frequency components of the CP output. Figure 1.5 shows a simple passive R-C loop filter. Generally, the R is required in the filter to isolate the phase correction from the frequency correction. The values of R and C1 determines many of the loop dynamics such as the hold range, capture range, damping and the loop bandwidth. Alternately, an active loop filter may also be used. Figure 1.5: A simple loop filter circuit. 1.1.4 Voltage Controlled Oscillator A Voltage Controlled Oscillator (VCO) in concept is a voltage to frequency converter. The output frequency of a VCO is directly proportional to its input voltage level. A simple VCO can be a ring oscillator made up of odd number of inverter

1.1 Conventional Charge-Pump Based PLLs 7 stages. The frequency of operation will depend on the delay between each stage. This delay should be made variable and should be controllable by the voltage provided by the loop filter. A simple block diagram of a CMOS ring oscillator is shown in figure 1.6. Here the control voltage V ctrl will be given to the gate of M1, which controls the current through the delay stages and eventually the frequency of oscillation. The frequency range of the VCO can be controlled by adding load capacitors at the output of each stage. Figure 1.6: A simple 5-stage ring oscillator VCO. 1.1.5 Qualitative Description of Conventional PLL To explain the working of a PLL from a mathematical point of view, we can model [Elangovan] the different blocks of a PLL as shown in the figure 1.7. In theory, a PLL is a loop which creates a Sys Period (T sys ) every Ref Period (T ref ) and compares the resulting instantaneous Sys Time and Ref Time. The difference in the reference and the feed-back times, T, is a measure of the instantaneous phase error. The CP then charges/discharges the capacitor C with an equivalent charge Q= T I cp, during each update cycle and the resistor produces a proportional component Vr= T I cp R/T ref. Figure 1.7: A simple model of a conventional charge-pump PLL.

8 1 Introduction From the figure 1.7, the forward path gain (eqn 1.1) and the feedback path gain (eqn 1.2) are given as below, FW D(z) = 1 z I cp 1 C 1 1 1 z + R ( ) Kvco T. ref f 2 (1.1) Where, 1 FB(z) = N 1 1 z (1.2) z(s) = e s T ref (1.3) Kvco = VCO gain in Hz/V I cp = charge-pump current in A 1 z I cp H(z) = 1 + 1 z I cp ( 1 C 1 1 1 z ( 1 C 1 1 1 z ) + T R ref ) + T R ref ( ) Kvco f 2 ( ) Kvco f 2 ( ) (1.4) 1 N 1 1 z Where, H(z) is the closed loop transfer function of a conventional CP based PLL. 1.2 Semi-Digital PLL Architecture The block diagram of a Semi-digital PLL architecture [Sareen and Dietl, 2011] [Elangovan et al., 2011] is shown in figure 1.8. The major changes between the conventional PLL and the semi-digital PLL are the storage cells which replace the loop filter. The tuning information is provided by two entities, namely, the storage cell outputs and the proportional voltage provided by the charge-pump. The charge-pump is basically used for analog damping here. 1.2.1 The Storage Cells The storage cells [Sareen and Dietl, 2011] [Dietl and Sareen, 2011] are what makes this architecture semi-digital. In the Figure 1.9, S1, S2,...,Sn are the storage cells. The outputs B from each cell contains the digital tuning information for the VCO. In the current architecture, the Bs have been designed as active low, since they will be driving PMOS gates. Each cell consists of a capacitor which stores the digital information. The capacitors will charge or discharge depending on the UP and DOWN pulses from the PFD. The reference current required for charging/discharging of the cells is provided by the REFF_CURR block. The A outputs from the cells are just the complement of the B outputs.

1.2 Semi-Digital PLL Architecture 9 Figure 1.8: Block diagram of a semi-digital PLL. The REFF_CURR block, takes UP and DOWN digital signals as inputs and produces the corresponding analog currents on FAST and SLOW outputs. The magnitude of the currents flowing through FAST and SLOW can decide the charging/discharging time constant of the capacitors in the cells. This block can be regarded as a charge-pump for the storage cells. Figure 1.9: Block diagram of the storage cells.

10 1 Introduction 1.2.2 The VCO Unlike in a conventional Voltage Controlled Oscillator (VCO), there are n+1 number of inputs in a VCO for the semi-digital PLL. Where n is the number of storage cells. The frequency of oscillations is proportional to the current provided by the sub-block called VCO_CURR as shown in figure 1.10. Figure 1.10: A conceptual block diagram of the VCO for semi-digital PLL. The VCO_CURR consists of a series of transistors with each of its gates connected to one of the storage cell B outputs and one of the transistors with its gate connected to the PROP signal, which is the output from the CP. When all of the B signals are high, the VCO runs at its lowest frequency and vice versa. The transistors connected to the Bs provide a VCO gain termed as the step gain (K step ) and the one connected to the PROP provides proportional gain (K prop ). The K prop is used for analog damping of the loop. 1.2.3 The Charge-Pump Since there is no Loop Filter in this architecture, the charge-pump (CP) provides the damping. Instead of a RC damping, this CP uses the concept of active damping. The two transistors connected to V prop, pulls it back to a pre-defined level (VDD/2 in this case) at the end of every update cycle. This way, the proportional gain is seen only half of the update period. A sample waveform showing the active and RC damping is shown in the figure 1.12. This structure results in lower update jitter in the locked state. 1.2.4 Semi-digital PLL: Working Principle When the loop is activated, the startup circuit initializes all the storage cells to logic HIGH. Depending on the phase errors between the reference frequency and the feedback frequency, the PFD either puts out a series of UP or DOWN pulses. Depending on these pulses, the storage cells either start discharging or charging, one after the other. At any given point of time, only two of the storage cells will be active and will be in the analog tuning mode [Sareen and Dietl, 2011]. All the cells preceding these two cells will be completely discharged to logic LOW and

1.2 Semi-Digital PLL Architecture 11 Figure 1.11: A conceptual block diagram of the CP for semi-digital PLL. Figure 1.12: A comparison between active damping and RC damping. those succeeding them will be fully charged to logic HIGH. A particular cell B(x) starts discharging only when its LEFT input (figure 1.9) crosses the switching threshold (VDD/2 in this case). An illustration of the same principle is shown in figure 1.13 for better understanding. With every update cycle, the PFD produces an UP or DOWN pulse, whose width is proportional to the phase error. These pulses result in corresponding proportional voltage at the output of the CP. This V prop [Sareen and Dietl, 2011] along with the Bs from the storage cells tune the VCO to the required frequency and phase. During lock, the tuning information is stored digitally in the storage cells and analog tuning is done by the two active storage cells in the analog tuning mode. The proportional voltage V prop will be pulled to VDD/2 [Elangovan et al., 2011].

12 1 Introduction Figure 1.13: Illustration of storage cell dynamics. The figure 1.14 is an example set of waveforms of a semi-digital PLL showing the V prop, UP, DOWN, F ref, F sys, one storage cell each in the HIGH, LOW and two in analog tuning mode. Figure 1.14: Typical waveforms of a semi-digital PLL. 1.2.5 Qualitative Description of Semi-digital PLL Like in the conventional PLL, the PFD generates UP/DOWN pulses whose width (δ i ) depends on the phase error during each (i th ) update cycle. But, the VCO fre-

1.2 Semi-Digital PLL Architecture 13 quency here in the semi-digital architecture is not just controlled by one voltage but by both the proportional voltage from the CP and the storage cell outputs. The proportional voltage (V prop ) depends on the charge deposited on the ripple capacitor (C) connected to the output of the CP and is given by, V prop (i) = I cp. δ i (1.5) C During each update cycle, the capacitors in the active storage cells also gets a corresponding charge deposited on them, depending on the time constant (dt step ) [Sareen and Dietl, 2011] [Elangovan et al., 2011] of each storage cell which in turn depends on both the storage cell capacitance (C s ) and the reference current flowing from the REFF_CURR block and is given by, dt step = C s.v DD 2.I ref (1.6) A simple model of the semi-digital architecture [Sareen and Dietl, 2011] is shown in figure 1.15. During lock, the storage cells B[1:x] will be pulled LOW, B[x+1] Figure 1.15: A simple model of a semi-digital charge-pump PLL. & B[x+2] will be in analog tuning mode and B[x+3 : N] will be pulled HIGH. Because of the two voltages controlling the VCO frequency, it has two separate gains namely the proportional gain (K prop ) given by the CP voltage and the step gain (K step ) given by the storage cells. At any given update cycle (i), the output frequency of the VCO (F sys ) is given by, F sys (i) = K prop V prop (i) + x K step + x+2 k=x+1 K step V k (i) 2 V DD (1.7) Now, considering the model in figure 1.15, the forward gain of the loop is given

14 1 Introduction by, G(z) = [ G prop (z) + G step (z) ] N 1 1 z G prop (z) = K prop f 2 Icp 2C (1.8) (1.9) K prop G(z) = f 2 G step (z) = 1 1 1 z Icp 2C + 1 1 1 z and the closed loop transfer function is given by, H(z) = K step f 2 dt step (1.10) G(z) 1 + G(z) K step f 2 dt N step 1 1 z (1.11) (1.12) Equation 1.11 describes the open loop transfer function of the semi-digital PLL and the dependence of the loop gain and bandwidth on different block parameters. Equation 1.11 is the most important source of reference used and is the basis for the work described in this report.

Part II Motivation & Solution

2 Current Design & Problem Statement This chapter describes in brief the current implementation of the semi-digital PLL for high bandwidth applications in 65nm CMOS technology. It is followed by a discussion about the shortcomings of the current design and a qualitative analysis of how it can be improved. 2.1 Current Implementation The present implementation follows a specification of a real life application requiring a PLL locking to a wide range of frequencies from 70 MHz to 1.6 GHz, 1.2V Vdd, faster locking times of less than 5us, adaptive bandwidth, low output jitter, low power and smaller die area. The semi-digital architecture was chosen in the first place, since... it is low power and is area efficient it is flexible to design for a wide range of operating frequencies it has digital storing of tuning information of the VCO it also has analog tuning it has large degree of freedom for PVT compensation, since the operating point information is digitally stored, and is possible to use this information to achieve the wished correction of different design parameters on the fly. it has better duty cycle and, it has very small update jitter. 17

18 2 Current Design & Problem Statement Design implementation details of the present architecture follows. 2.1.1 Phase Frequency Detector The Phase Frequency Detector (PFD) used is a simple one as described in the section 1.1.1. It uses standard digital components from the library. The figure 2.1 shows a snapshot of some simulation waveforms of the PFD outputs. Figure 2.1: PFD waveforms when (a) F sys leads F ref & (b) F ref leads F sys. 2.1.2 Charge Pump The figure 2.2 shows the schematic of the current charge-pump (CP) used [Elangovan et al., 2011]. It is a structure with all NMOS switches, which provides a matched PFD load. Figure 2.2: Schematic of the current CP. From equation 1.11, it can be inferred that for achieving adaptive bandwidth, the charge-pump current I cp needs to scale with the reference frequency. This is done here using the resistive breeching circuit (RES_BREECHING) as shown in the figure 2.3. This circuit makes use of the digital tuning information to scale the values of the resistor used for generating the reference current, mirrored to the CP switches dynamically, depending on the operating frequency. The value of

2.1 Current Implementation 19 Figure 2.3: Schematic of the RES_BREECHING circuit. the charge-pump capacitor (C) required here is very low (0.1pF) and the typical magnitude of the I cp varies between 20uA to 300uA depending on the reference frequency (F ref ). 2.1.3 Voltage Controlled Oscillator The design uses a 5-stage Voltage Controlled Oscillator with differential input/outputs. The schematic of a VCO stage [Elangovan et al., 2011] is shown in figure 2.4. Figure 2.4: Schematic of the current VCO circuit.

20 2 Current Design & Problem Statement The output frequency of the VCO is controlled by two blocks namely OSC_PROP_P and OSC_PROP_N. They consist of a series of switches which are controlled by the storage cell outputs and the V prop as shown in figure 2.5 and 2.6. The size of the switches decides the step gain (K step ) and proportional gain (K prop ) of the VCO. When all the storage cells are inactive, these two blocks provides minimum Figure 2.5: Schematic of the OSC_PROP_P circuit. Figure 2.6: Schematic of the OSC_PROP_N circuit. current since all the switches are off resulting in the VCO to oscillate at its lowest frequency and vice versa. This VCO gives very good duty cycle. The transistors M5, M6, M7, M8 (in figure 2.4) are used for cross coupling of the inverter outputs OSC and OSC. The level shifters (figure 2.7) provides full swing to the inverter outputs. The transistors M9, M10, M11 and M12 (in figure 2.4) provides cross coupling for the level shifter outputs BUF and BU F. The inverter outputs OSC and OSC each are also connected to small load capacitances of the order of few hundred femto Farads (not shown in the schematic). 2.1.4 Storage Cells The storage cells use a capacitor to store the digital tuning information and is also capable of giving out an analog voltage when they are in the analog tuning mode. The storage cell outputs (B) are inherently active low here. An inverted output (A) is also available. Figure 2.8 shows the schematic of a storage cell [Sareen and Dietl, 2011]. The LEFT and the RIGHT input to the storage cells are used to decide when to start discharging the capacitor. The current required for charging/discharging

2.1 Current Implementation 21 Figure 2.7: Schematic of the level-shifter circuit. the capacitor is given through the FAST and the SLOW pins. The value of the capacitor and the reference current given by the REFF_CURR decides the time constant of C store. The cells also have the option for initializing the cells during startup. Figure 2.8: Schematic of the storage cell circuit. Figure 2.9, shows the schematic of the REFF_CURR block. The resistors R and the mirror ratios M3:M5 and M8:M6 are used to control the reference current for charging/discharging of the storage cells. 2.1.5 Top Level PLL Figure 2.10 shows a snapshot of the top level schematics of the PLL. A divider was added for both the reference clock (F ref ) and the feedback clock (F sys ) since sometimes false locking to fractional frequencies was seen during locking of the PLL. In this implementation, during initialization, five storage cells are pre-discharged

22 2 Current Design & Problem Statement Figure 2.9: Schematic of the REFF_CURR circuit. so as to aid faster locking. Figure 2.10: Schematic snapshot of the current PLL top level. 2.1.6 Shortcomings of the Current Design The shortcomings of the current design are listed below... The current design fails to achieve adaptive bandwidth (figure 2.11 & figure 2.12 ), since... there is no correlation between the VCO frequency and the chargepump current

2.1 Current Implementation 23 the proportional gain of the VCO does not scale with its frequency of oscillations. The present VCO circuit consumes a bit more current than expected because of the DC current flowing through the level shifter circuit. Mathcad simulation of equation 1.11 also shows that at lower frequencies upto around 250 MHz, the loop shows considerable peaking of upto 4db. (figure 2.13) The loop shows false locking phenomenon in the absence of a divider. It does not use the full potential of the digital information available for PVT compensation. Figure 2.11: Mathcad simulation of equation 1.11 for current design at F ref =500 MHz. Strong Nominal Weak Kstep (Hz/step) 350 10 6 275 10 6 150 10 6 Kprop (Hz/V) 275 10 6 250 10 6 205 10 6 Icp (A) 350 10 6 305 10 6 265 10 6 dt (s) 75 10 9 175 10 9 275 10 9 Table 2.1: Simulated parameters for current design used to generate the plots in figure 2.11 at F ref =500 MHz.

24 2 Current Design & Problem Statement Figure 2.12: Mathcad simulation of equation 1.11 for current design at F ref =1600MHz. Strong Nominal Weak Kstep (Hz/step) 350 10 6 275 10 6 150 10 6 Kprop (Hz/V) 950 10 6 900 10 6 860 10 6 Icp (A) 750 10 6 619 10 6 550 10 6 dt (s) 75 10 9 175 10 9 275 10 9 Table 2.2: Simulated parameters for current design used to generate the plots in figure 2.12 at F ref =1600 MHz. Figure 2.13: Mathcad simulation of equation 1.11 showing peaking at 150 MHz and a way to solve it by increasing dt step.

2.1 Current Implementation 25 2.1.7 Problem Statement The primary goal of the thesis is to overcome the shortcomings mentioned in the section 2.1.6. Mathcad simulation of equation 1.11 shows that in order to attain an adaptive bandwidth, the first term needs to be a constant. In short, if we can make the ratios K prop /f and I cp /f constant, then the loop bandwidth tracks the input reference frequency. An example of the same is shown in figure 2.14. Figure 2.14: Mathcad simulation of equation 1.11 showing adaptive bandwidth. This should also be done in such a way that the design uses the digital tuning information to self-compensate the different parameters such that the deviation in performance remains fairly small across PVT corners.

3 Proposed New Design In order to achieve the goals mentioned in sections 2.1.6 and 2.1.7, the two major blocks requiring any change are the charge-pump and the VCO. There were many experiments conducted and several proposals were evaluated. With a very short deadline, there was an opportunity to implement the first proposal in an ongoing project and the performance was measured on a taped-out chip. This chapter includes the measurement results of the chip. 3.1 Design Changes 3.1.1 Proposal 1: Self-compensated Current Sources K prop /F ref ratio With a short deadline, the first attempt was to make the proportional gain (K prop ) scale with the frequency with a fixed ratio. The gain of the VCO is controlled by the OSC_PROP_P (fig 2.5) and the OSC_PROP_N (fig 2.6) blocks. In the current design (section: 2.1.3), the transistors M11, M12... M1n of OSC_PROP_P are all sized the same (let us call their W/L=S1) and they control the step gain (K step ) and the transistor Mp (W/L=S2) controls the proportional gain (K prop ). Their sizing is independent of each other. Same is the case with OSC_PROP_N. Since the transistors connected to the storage cells ( M11, M12... M1n) have no correlation with the ones connected to the V prop (eg. Mp in OSC_PROP_P ), and because of their static sizing, it was inferred that this can be two of the reasons for the K prop not being able to scale with the VCO frequency. In the modified design of these blocks, the transistors were divided into groups as shown in figures 3.1 and 3.2. All the transistors in each group were sized the 27

28 3 Proposed New Design Figure 3.1: Schematic of the modified OSC_PROP_P circuit. Figure 3.2: Schematic of the modified OSC_PROP_N circuit. Figure 3.3: K prop /F ref measurement at 1.6 GHz. Figure 3.4: K prop /F ref measurement at 600 MHz. same and the ones in the adjacent groups were sized in geometric progression with a ratio of 2. Doing so, the effect of V prop on the gain of the VCO is now directly proportional to the number of active storage cells, which in turn is a measure of the VCO frequency. Hence in theory, K prop should linearly vary with the VCO frequency. The K prop /F ref ratio of the VCO was measured at different frequencies and it was found to be a near constant value of around 1.45. The ratio was also found to be the same across PVT corners. This approach also makes K step

3.1 Design Changes 29 Figure 3.5: K prop /F ref measurement at 500 MHz. scale with the frequency. But as can be seen in equation 1.11, that though it gives us a constant ratio of K step /F ref in the second term, it does not really contribute to the bandwidth and hence is a dont-care. I cp /F ref ratio In order to make the charge-pump current (I cp ) scale with the operating frequency with a constant ratio, it is important to have a reference current source for the CP which follows the current in the VCO. The simplest and the quickest way to do so was to get rid of the RES_BREECHING block of the CP (figure 2.2) and replace it with the new OSC_PROP_P block (figure 3.1) as shown in figure 3.6. The required I cp ratio can be obtained by appropriately sizing the transistors M2 and M3. Figure 3.6: Proposal 1: modified charge-pump schematic. Chip measurement results The bandwidth (BW) measurements (figure 3.7) of the chip shows that for different reference frequencies, the BW does not track F ref as intended. Moreover, the BW varies a lot over PVT corners. The reason behind this was inferred that though the reference current source used for the CP was OSC_PROP_P, which is same as that in the VCO, the node voltage VP of the CP (fig: 3.6) is not the same as the node SP in the VCO (fig: 2.4). Hence the currents are not correlated.

30 3 Proposed New Design Figure 3.7: Initial chip bandwidth measurements for F ref from 667 MHz to 1.6 GHz. 3.1.2 Proposal 2: Voltage Tracking OPAMP based Charge-Pump Going by the inference from the previous proposal, a way to match the node VP in the CP to the node SP in any of the VCO buffer was tried here. A tried and tested method of doing so is by using an opamp as a voltage follower and trying to make VP follow SP as shown in the figure 3.8. This works with the assumption that both the OSC_PROP_P and the OSC_PROP_N blocks in the VCO are perfectly matched. However this may not be true in most cases since the OSC_PROP_P block contains only PMOSes and OSC_PROP_N block consists of only NMOSes, and matching them requires lot of fine tuning of the sizes and also very complicated layout of the two blocks. The schematic of the OPAMP used is shown in figure 3.9. The specification and characterizations of the OPAMP are discussed in the APPENDIX. In the schematic of the CP (figure 3.8), the transistor M20 s gate is connected to the output of the voltage follower. Due to the high input impedance of the opamp, the positive input (VP) of the opamp must be same as the negative input (SP). Now M20 always tries to keep this principal true by varying its drain-source voltage in accordance to the output from the voltage follower. There were some more changes done to the CP, since in the current design (fig: 3.6) the UP and DOWN currents do not match. An example of this is shown in figure 3.10. The reason for the mismatch was analyzed to be the mismatch between the two nodes V mirr and V prop in figure 3.6. During a DOWN pulse, when M9

3.1 Design Changes 31 Figure 3.8: Charge-pump with the voltage tracking Opamp. tries to pull up the node V prop, it sees a different drain source voltage compared to M4 because of the connection to the active pull back circuit consisting of M12 and M13. Hence the mirrored current in the output node (through M9) does not match the current through M4. In order to cater for the mismatch, the design of the active pull back circuit was modified as shown in figure 3.8. With this design, the pull-back value also changes dynamically with the reference frequency (unlike in the current design, where the pull-back voltage is fixed to VDD/2), since the CP reference current is also mirrored in the active pull back circuit. The transistors M16, M17, M18, M19 were added to match with M12. This makes all the five branches in the CP, exactly the same. The figure 3.11 shows the matched UP and DOWN currents in the new design at lower and higher frequencies. Figure 3.9: Schematic of the OPAMP.

32 3 Proposed New Design Figure 3.10: Simulation waveforms showing the mismatch of the UP and DOWN currents in the present charge-pump. Figure 3.11: Simulation waveforms showing matched UP and DOWN currents of the proposal:2 charge-pump design.

3.1 Design Changes 33 This design approach needs careful design of the switches (M6, M7, M10, M11, M14) and the mirror transistors (M4, M5, M8, M9, M13), such that the pull back value remains within a certain range for all working frequencies. This is because, it is important that the proportional gain (K prop ) of the VCO remains linear during lock. A plot of the Frequency v/s K prop of the VCO at different frequency ranges, show that the K prop is only linear for couple of hundred millivolts around VDD/2 (fig: 3.12 and 3.13). The current design did not have this issue since V prop was always pulled back to VDD/2. So this approach makes the design VDD dependent. Figure 3.12: VCO gain curve around 200 MHz. Figure 3.13: VCO gain curve around 1600 MHz. The loop was simulated with the new charge-pump, and the simulated waveforms in figure 3.14 shows that the node VP in the charge-pump tracks the voltage SP in the VCO, and as a result the currents in the VCO and the CP also track each other giving a constant ratio I cp /F ref. Measurements for the charge-pump current (I cp ) at different reference frequencies were made (table 3.1), and it can be seen that the I cp scales very well with F ref and the the ratio I cp /F ref was found to be almost constant with an average

34 3 Proposed New Design value of around 280 10 15. With this ratio, the capacitance value of 360fF and a K prop /F ref ratio of 1.45, the bandwidth of the loop was estimated in MathCad at different reference frequencies and it can be seen in figure 3.16 that the bandwidth tracks the reference frequency with a ratio of F ref /22. Figure 3.14: Simulation waveforms showing the tracking of the VP and the SP nodes. Figure 3.15: Simulation waveforms showing the scaling of I cp with F ref of 200 MHz, 800 MHz and 1600 MHz.

3.1 Design Changes 35 F ref 200 MHz 800 MHz 1600 MHz dv/dt 165 10 6 638 10 6 1.193 10 9 I cp = C dv/dt 59.4 10 6 230 10 6 434 10 6 I cp /F ref 297 10 15 287 10 15 271 10 15 Table 3.1: Simulated parameters for proposal:2 design used to generate the mathcad plots in figure 3.16. Figure 3.16: Closed loop response with the Proposal:2 CP at different reference frequencies. 3.1.3 Proposal 3: Topological Matching Proposal 2, though is a good solution to the problem, has an increased complexity because of the presence of OPAMP and the need for careful sizing of the transistors in the CP. An alternative approach was proposed with changes in the architecture of the charge-pump and the VCO to achieve the same goals but with lesser overall design complexity. There were few things like the peaking at lower frequencies, better compensation and lower power consumption which were not taken care of in the proposal 2. Proposal 3 includes solutions for all of the problems stated in section 2.1.6. One of the simpler approach to get the first term in equation 1.11 to be a constant would be to have a common structure [Maneatis, 1996] for the charge-pump and the VCO such that the currents in them always match each other. The main approach behind this proposal was to find a circuit topology which can be used to build both the CP and the VCO. The charge-pump The VCO more or less has a fixed topology because we are using a ring oscillator. Since we are using a differential ring oscillator, in each stage we have two

36 3 Proposed New Design inverters with two PMOS and two NMOS, whose gates when connected to the UP, DOWN signals can work like switches for the charge-pump current. With this in mind, a CP structure ( called as the current steering CP structure) was built as shown in the figure 3.17. Figure 3.17: Proposal 3: charge-pump schematic. The core switching transistors M9, M10, M12, M13 (fig: 3.17) forms the basic structure of the CP which is same as that of the differential VCO cell. M2 and M3 are used to mirror the current from the OSC_PROP_P block and the required CP current (I cp ) is obtained by appropriately sizing the transistors M4, M8, M7 and M11. The V prop input of the OSC_PROP_P cell is tied high here, since V prop is indeed the output of this Charge-pump block. The branch with the transistors M4, M5, M6, M7 and the two switches M9 and M10 are added here, in order to keep the current through the transistors M8 and M11 always flowing, without splitting the I cp between these branches. In the absence of this branch, when either of M12 or M13 are off, the currents through M8 and M11 respectively becomes discontinuous. This is particularly not good at higher frequencies. This topology does not require a dynamic active pullback circuit for UP/DOWN current matching. The matching is obtained here by following the rule of thumb that PMOSes needs to be 1.5 or 2 times as big as the NMOSes (or other ratios depending on the process). If this rule is followed, then the transistors M14, M15, M16, M17 in the active pullback circuit always pulls back the V prop to VDD/2 during each update cycle. The same is shown in the figure 3.18. The VCO In order to make the CP and the VCO structure similar, the most important step was to completely eliminate the use of OSC_PROP_N block, and use the reference current structure simlar to that of the CP using only the OSC_PROP_P block. The figure 3.19 shows the new VCO cell which does not include the OSC_PROP_P

3.1 Design Changes 37 Figure 3.18: Proposal 3: charge-pump UP/DOWN current matching. and OSC_PROP_N blocks unlike the current VCO cell as shown in figure 2.4. The top level of the VCO consisting of all five stages and the reference current Figure 3.19: Proposal 3: schematic of a VCO cell. source is shown in the figure 3.20. As can be seen here, the reference current for the VCO comes form a structure (OSC_PROP_P, M1, M2 and M3) exactly same as that in the CP (fig: 3.17). Even the transistor sizes are same. The simplest thing about this design is that the inverter transistors M1, M2, M3, M4 of the VCO can be exactly same as the switching transistors M9, M10, M12, M13 of

38 3 Proposed New Design the charge-pump (fig: 3.18). This makes the structure even better matched. The required frequency range of the VCO and the gains K prop and K step are governed by the transistors M4, M5, M6... M11, M12 and M13. In each VCO cells, the OSC_PROP_P and OSC_PROP_N blocks are replaced by these transistors. Figure 3.20: Proposal 3: schematic of a VCO TOP. In order to make sure that the new VCO structure does not degrade in performance, in comparison to the current VCO, a phase noise analysis was done on both the VCOs and compared. The new VCO is almost similar to the old one in terms of phase noise (only 2dB down). This degradation should not be much of a concern in this particular design since at the given bandwidth and higher reference frequencies, the output noise is dominated by the input noise. The comparison plot is shown in the figure 3.21. The frequency range of the new VCO was measured and found to be between 9 MHz to 3.3 GHz. Figure 3.21: Proposal 3: VCO phase noise analysis comparison with the current VCO.

3.1 Design Changes 39 One of the other advantages of using the new structure for the VCO is that because of the absence of OSC_PROP_P and OSC_PROP_N blocks, now there is less stacking of the transistors and hence the ring oscillator can provide a full swing output. This is particularly good for low voltage designs and also results in better duty cycle control since the differential outputs of the VCO cell, OSC and OSC always cross around VDD/2 irrespective of the frequency. Plots comparing the output swings of the VCOs at 40 MHz and 1600 MHz is shown in the figures 3.22 and 3.23. Figure 3.22: New v/s old VCO swing at 40 MHz. Figure 3.23: New v/s old VCO swing at 1600 MHz. Level Shifter The old level shifter consumed excess DC power which constituted almost 50% of the total power of the loop. The level shifter here is nothing but a differential amplifier with diode connected load. The aim of the amplifier here is not to accurately amplify the input signal but to convert it to a full swing signal. It is only required to burn power during switching and it is not required to be working in

40 3 Proposed New Design the steady state. To achieve this, a simple switch is added to the diode connected loads which are switched ON only during switching of the input clock signal. This reduces the average DC power by around 50%. Figure 3.24: Schematic of the new level shifter circuit. Figure 3.25: Comparison of current consumption by the old and new level shifter. FLL mode In order to avoid the false locking phenomenon, a divider was added to both the F ref and the F sys clocks. This approach has a disadvantage that it increases the magnitude of the error function, which adversely affects the jitter performance. The error function is given by equation 3.1 where G(z) is given by the equation 1.11. 1 E(z) = (3.1) 1 + G(z)

3.1 Design Changes 41 A mathcad plot of the error function at 1600 MHz, with and without the divider is shown below. Figure 3.26: Error function with a divider. Figure 3.27: Error function without a divider. As a novel solution to this problem, an FLL (Frequency Locked Loop) mode was added to the system. In this mode, the loop does not look at the phase differences between the F ref and the F sys clocks but only compares the frequency difference. The loop will be put into the FLL mode within couple of cycles of the F ref clock and it switches back to the PLL mode when the F sys frequency is very close to the F ref frequency. Thus avoiding any chance of false locking. This is achieved by by-passing the PFD in the FLL mode and continuously charging/discharging the storage cells depending whether the F sys is higher or lower than the F ref. The schematic of the Frequency Detector (FD) circuit for generating the FLL mode signal is shown in figure 3.28. The basic principle of operation is that when the frequency difference between the two inputs is very high, the capacitor gets enough time to charge itself and when the frequencies are closer, the capacitor cannot charge completely. The charging and discharging time constants of the ca-

42 3 Proposed New Design Figure 3.28: Schematic of the Frequency Detector (FD) circuit. pacitor (C) is controlled by the resistors R. The transistors M7, M8, M9 and M10, M11, M12 form two asymmetric inverters, whose switching threshold is shifted by one vt using the diode connected M7 and M12. These inverters provide a dead zone within which the FD cannot detect the frequency difference. The FLL_DN signal, when asserted means that the F sys is higher than the F ref and FLL_UP signifies otherwise. The FLL signal is used to block the PFD. Storage Cells There were two changes done to the storage cells. One of the changes was with the intention of making them FLL mode compatible, and the second one was to decrease the peaking at lower frequencies. The figure shows the schematic of the storage cell with the FLL mode. When the FLL_UP or the FLL_DN signals are asserted, they by-pass the switches FAST and SLOW respectively and provides a much faster path for the capacitor to charge/discharge. The transistors M11 and M12 are bigger and faster than M1 and M4 and their sizes depends on how fast do we want our FLL mode to be. It was shown in the figure 2.13 that if we increase the dt step, the peaking at lower frequencies can be reduced. dt step can be decreased by one of the three ways mentioned below. Decrease the reference current from the REFF_CURR block Increase the capacitances in the storage cells Make the transistors M1 and M4 smaller

3.1 Design Changes 43 Figure 3.29: Example waveforms of the Frequency Detector (FD) circuit. Figure 3.30: Schematic of the storage cell with FLL mode. The third approach was used here since the other two approaches can increase the area a little bit. It is seen both in the mathcad plots and through simulations that only lower frequencies require higher dt step and it does not have any noticeable effects at frequencies above 200 MHz. It was also seen through simulations that if dt step is high, then the static offset increases in the locked state and also the lock time increases, even in the presence of the FLL mode. To cater for this, the storage

44 3 Proposed New Design cells were divided into two groups. The storage cells S1 to S5 were made to have higher dt step and S6 to S19 were having the normal dt step. In the second group, the W/L of M1 and M4 are S n and S p respectively, where as the same in the first group is S n /10 and S p /10. Figure 3.31: dt step measurement waveforms for S1 to S5. Figure 3.32: dt step measurement waveforms for S6 to S19. The figures 3.31 and 3.32 shows the dt step measurement waveforms. The dt step for S1 to S5 is 1us and that of S6 to S19 is 180ns. During the FLL mode, the dt step of the second group reduces to 60ns.

3.1 Design Changes 45 PLL Top Level Two of the noticeable changes that can be seen in the TOP level schematic (figure 3.39) is the absence of the divider flipflops at the input of the loop and the new block FD for FLL mode. Figure 3.38 illustrates the behavior of the loop in the FLL mode. It can be seen that the storage cells (VBs) discharge continuously with the minimum dt step possible, the V prop remains at VDD/2 and the UP/DOWN signals remain LOW since the PFD is cut off. As soon as the loop enters the PLL mode, an immediate change in the slope of the VBs can be seen since the dt step again goes back to the normal value. Figure 3.33: Proposal 3: K prop measured at 400 MHz. Figure 3.34: Proposal 3: K prop measured at 800 MHz.

46 3 Proposed New Design Since the VCO has a new structure now, the K prop /F ref ratio is bound to change. Measurements for K prop were made at different frequencies and the new ratio was found to be around 1.65. Figure 3.36 shows the near perfect scaling of the charge-pump current (I cp ) with the reference frequency. Using the measured parameters at different frequencies, the closed loop response of the PLL at different frequencies was estimated in mathcad and is illustrated in figure 3.37. It can be seen that the PLL bandwidth tracks the reference frequency with a ratio of around 1/22. Figure 3.35: Proposal 3: K prop measured at 1600 MHz. C = 500fF F ref 400 MHz 800 MHz 1600 MHz dv/dt 247 10 6 500 10 6 1.019 10 9 I cp = C dv/dt 123 10 6 250 10 6 509 10 6 I cp /F ref 310 10 15 313 10 15 320 10 15 K prop 250 10 6 450 10 6 915 10 6 K prop /F ref 1.6 1.77 1.74 Table 3.2: Simulated parameters for proposal:2 design used to generate the mathcad plots in figure 3.37.

3.1 Design Changes 47 Figure 3.36: Proposal 3: simulation waveforms showing the scaling of I cp with F ref at 400 MHz, 800 MHz and 1600 MHz. Figure 3.37: Proposal 3: closed loop transfer function.

48 3 Proposed New Design Figure 3.38: Sample top level waveforms illustrating the dynamics of the FLL mode.

3.1 Design Changes 49 Figure 3.39: The new PLL top level schematic snapshot.

Part III Results 51

4 Results This chapter contains the results and conclusions of two of the three proposals described in chapter 3. Proposal 1 is not covered in this chapter since the chip measurement data of this proposal is already shown in section 3.1.1. 4.1 Simulation Results of Proposal 2 This sections gives a brief account of the simulation results obtained for proposal 2, the one with the voltage tracking OPAMP based charge-pump. 4.1.1 Locking Waveforms The figures 4.1 to 4.3 shows the locking waveforms in the three PVT corners along with the phase difference plots at reference frequencies of 200 MHz, 800 MHz and 1600 MHz respectively. The Table 4.7 shows the final static offset values during lock at different reference frequencies and PVT corners. Static Offset F ref 200 MHz 800 MHz 1600 MHz Strong 32 ps 2 ps 4ps Nominal 48 ps 14 ps 10 ps Weak 50 ps 22 ps 18 ps Table 4.1: Proposal 2: simulated static offset. 53

54 4 Results Figure 4.1: Proposal 2: locking and static offset at 200 MHz. Figure 4.2: Proposal 2: locking and static offset at 800 MHz. 4.1.2 CP Active Pull-back Voltage As it was described in section 3.1.2, that the charge pump in figure 3.8 uses dynamic active pull-back and it requires careful sizing of the pull-back circuit and

4.1 Simulation Results of Proposal 2 55 Figure 4.3: Proposal 2: locking and static offset at 1600 MHz. Figure 4.4: Proposal 2: pull-back voltage at 200 MHz, 800 MHz and 1.6 GHz. the switches such that the pull back value of V prop always remains couple of hundred mili-volts around VDD/2. Figure 4.4 shows the pull-back values obtained for different frequencies.

56 4 Results 4.1.3 I cp Compesation The charge-pump uses the OSC_PROP_P block as reference current source and the OPAMP matches the node voltages with that of the VCO. Since the OSC_PROP_P is a self-compensated block, the current in the charge-pump (I cp ) also becomes self-compensated. Figures 4.5 to 4.7 shows the compensated currents in different PVT corners, which are summed up in Table 4.7. Figure 4.5: Proposal 2: I cp measured at 200 MHz in different PVT corners. Figure 4.6: Proposal 2: I cp measured at 800 MHz in different PVT corners.

4.1 Simulation Results of Proposal 2 57 Figure 4.7: Proposal 2: I cp measured at 1600 MHz in different PVT corners. F ref = 200 MHz, C= 360fF PVT Corner Strong Nominal Weak dv/dt 192.24 10 6 157.05 10 6 154.08 10 6 I cp = C dv/dt 69.2 10 6 56.54 10 6 55.46 10 6 F ref = 800 MHz, C= 360fF PVT Corner Strong Nominal Weak dv/dt 618.77 10 6 615.37 10 6 604.7 10 6 I cp =C dv/dt 222.75 10 6 221.5 10 6 217.7 10 6 F ref = 1600 MHz, C= 360fF PVT Corner Strong Nominal Weak dv/dt 1.14 10 9 1.04 10 9 1.09 10 9 I cp =C dv/dt 410.4 10 6 374.40 10 6 392.4 10 6 Table 4.2: Proposal 2: charge pump current in different PVT corners. 4.1.4 Period Jitter Period jitter was measured with transient noise and the worst case period jitter values are tabulated below.

58 4 Results Figure 4.8: Proposal 2: period jitter at 400 MHz, 800 MHz and 1600 MHz. F ref 200 MHz 800 MHz 1600 MHz Period Jitter 46.1 ps 23.1 ps 10 ps % of Period 0.91% 1.84% 1.6% Table 4.3: Proposal 2: period jitter. 4.1.5 Bandwidth Tracking Bandwidth simulations were done on the loop by frequency modulating the reference clock with different frequencies as estimated in figure 3.16. Bandwidth is determined when the sys clock also modulates but with 3db lesser frequency magnitude and with a 90 degrees phase shift. The results are tabulated in table 4.4. It can be seen that the BW tracks the reference frequency very well as estimated in figure 3.16. The BW also remains the same even in different PVT corners which also shows the self-compensation. Bandwidth F ref 200 MHz 800 MHz 1600 MHz Strong 10 MHz 42.3 MHz 67 MHz Nominal 9.5 MHz 36.2 MHz 61 MHz Weak 9.65 MHz 35 MHz 54 MHz Table 4.4: Proposal 2: simulated loop bandwidth.

4.1 Simulation Results of Proposal 2 59 Figure 4.9: Proposal 2: loop bandwidth at 200 MHz in different PVT corners. Figure 4.10: Proposal 2: loop bandwidth at 800 MHz in different PVT corners.

60 4 Results Figure 4.11: Proposal 2: loop bandwidth at 1.6 GHz in different PVT corners. 4.1.6 Power Consumption F ref 200 MHz 800 MHz 1600 MHz Average Current 12.29 ma 17.67 ma 19.14 ma Table 4.5: Proposal 2: avg current consumption in strong corner. Figure 4.12: Proposal 2: worst case average current consumption.

4.2 Simulation Results of Proposal 3 61 4.2 Simulation Results of Proposal 3 This section gives a brief account of the simulation results obtained for proposal 3, the one with topographical matching. 4.2.1 Locking Waveforms The figures 4.13 to 4.15 shows the locking waveforms for the three PVT corners along with the phase difference plots at reference frequencies of 400 MHz, 800 MHz and 1600 MHz respectively. The Table 4.12 shows the final static offset values during lock at different reference frequencies and PVT corners. Static Offset F ref 400 MHz 800 MHz 1600 MHz Strong 20 ps 7.9 ps 2.06 ps Nominal 30.63 ps 14.3 ps 14.1 ps Weak 76 ps 88.4 ps 58.6 ps Table 4.6: Proposal 3: static offset measured at different PVT corners. Figure 4.13: Proposal 3: locking and static offset at 400 MHz.

62 4 Results Figure 4.14: Proposal 3: locking and static offset at 800 MHz. Figure 4.15: Proposal 3: locking and static offset at 1600 MHz.

4.2 Simulation Results of Proposal 3 63 4.2.2 VCO and CP Reference Current Co-relation Figure 4.16: Proposal 3: VCO and Charge pump reference current tracking. The figure 4.16 illustrates the tracking of the CP reference current (REF_CURR_CP in green) with that of the VCO (REF_CUR_VCO in blue) and also shows that they have a fixed ratio between the two. Hence we can conclude that... since, I osc I cp F sys I osc = Constant F sys I cp = Constant 4.2.3 I cp Compensation Since the OSC_PROP_P is a self-compensated block which is used as a reference current source, the current in the charge-pump (I cp ) also becomes self-compensated. Figures 4.17 to 4.19 shows the compensated currents in different PVT corners. Like before, slope of the V prop is measured to calculate the current.

64 4 Results Figure 4.17: Proposal 3: Charge pump current measurement at 400 MHz. Figure 4.18: Proposal 3: Charge pump current measurement at 800 MHz.

4.2 Simulation Results of Proposal 3 65 Figure 4.19: Proposal 3: Charge pump current measurement at 1600 MHz. F ref = 400 MHz, C=500fF PVT Corner Strong Nominal Weak dv/dt 245.13 10 6 241.2 10 6 237.3 10 6 I cp = C dv/dt 122.5 10 6 120.6 10 6 118.65 10 6 F ref = 800 MHz, C=500fF PVT Corner Strong Nominal Weak dv/dt 503.05 10 6 499 10 6 465.85 10 6 I cp = C dv/dt 251.52 10 6 249.5 10 6 232.9 10 6 F ref = 1600 MHz, C=500fF PVT Corner Strong Nominal Weak dv/dt 1.034 10 9 1.087 10 9 1.277 10 9 I cp =C dv/dt 517.0 10 6 543.50 10 6 638.50 10 6 Table 4.7: Proposal 3: charge pump current in different PVT corners. 4.2.4 K prop Compensation Since OSC_PROP_P block is used as reference current source for the VCO, K prop is also self-compensated. As an example, it can be seen in figure 3.34, K prop of

66 4 Results Figure 4.20: Proposal 3: K prop measurement in different PVT corners. the VCO at 800 MHz in nominal corner is 450 MHz/V. As an example, the K prop of the VCO at 800 MHz was also measured in the strong and weak corners, and was found to be the same. F ref Strong Nominal Weak K prop 800 MHz 456 MHz/V 450 MHz/V 457 MHz/V Table 4.8: Proposal 3: K prop compensation. 4.2.5 Period Jitter Period jitter was measured with transient noise and the worst case period jitter values are tabulated below. F ref 400 MHz 800 MHz 1600 MHz Period Jitter 44.1 ps 33.8 ps 19.6 ps % of Period 1.76% 2.7% 3.1% Table 4.9: Proposal 3: period jitter.

4.2 Simulation Results of Proposal 3 67 Figure 4.21: Proposal 3: period jitter at 400 MHz, 800 MHz and 1600 MHz. 4.2.6 Bandwidth Tracking The bandwidth (BW) of the loop was measured at different reference frequencies by frequency modulating the reference clock with the frequency of the estimated bandwidth. The BW was found to track the reference frequency very well around the 5% of F ref range. The table 4.12 shows the result of the measurements in different PVT corners. Figure 4.22: Proposal 3: Bandwidth at 400 MHz.

68 4 Results Figure 4.23: Proposal 3: Bandwidth at 800 MHz. Figure 4.24: Proposal 3: Bandwidth at 1600MHz. To make sure that the Bandwidth scales with the charge-pump current (I cp ), simulations were run with double the I cp and it was seen that the bandwidth roughly doubles and still tracks the reference frequency very well.

4.2 Simulation Results of Proposal 3 69 Bandwidth F ref 400 MHz 800 MHz 1600 MHz Strong 18 MHz 39 MHz 83 MHz Nominal 18 MHz 38 MHz 76 MHz Weak 19 MHz 40 MHz 100 MHz Table 4.10: Proposal 3: Bandwidth. Figure 4.25: Proposal 3: I cp measurement for bandwidth of 10% of F ref. Figure 4.26: Proposal 3: Bandwidth measurement with double the I cp.

70 4 Results Bandwidth with double the I cp F ref 200 MHz 800 MHz 1600 MHz BW 17 MHz 80 MHz 180 MHz Table 4.11: Proposal 3: Bandwidth with double the I cp. 4.2.7 Power Consumption Due to the usage of the new level shifter, the overall power consumption too decreased by more than 50%. The following are the average power numbers in the strong corner. F ref 400 MHz 800 MHz 1600 MHz Average Current 3.79 ma 5.49 ma 8.94 ma Table 4.12: Proposal 3: worst case avg current consumption in strong corner. Figure 4.27: Proposal 3: average current measurements at 400 MHz, 800 MHz and 1.6 GHz.

5 Conclusion 5.1 Conclusions A non-conventional PLL architecture known as the semi-digital PLL was explored in this work. A semi-dital PLL consists of digital storage cells which both replaces the loop filter in a conventional charge-pump based PLL and also stores the operating point information of the loop digitally. This is a relatively new architecture and hence has minimal references. The work was divided into three phases, Literature review and problem definition. Design exploration and implementation. Documentation. The primary aim of this thesis work was to explore the current design and try to exploit the concept of digital storage cells and the operating point information provided by them. One of the obvious use of the operating point information was to make the design self-compensated. Hence this became one of the primary objective of the thesis. A consequence of self-compensation is that most of the circuit parameters vary with the operating condition of the loop. This thesis also exploits this to our advantage, by making the dependant parameters (like currents and voltages) vary linearly with respect to some of the governing parameters (like the reference frequency and PVT corners). By doing so, it was found that the bandwidth of the loop would track the reference frequency linearly. The design exploration and implementation part of the project went hand in hand. The approach used here was to try out different architectures and ways 71

72 5 Conclusion of achieving the intended goals, and those that worked were considered as one of the proposed solutions to the problems defined. At the end, only two of the tried architectures and proposals were considered fit to be documented. The design was done in 65nm CMOS technology with 1.2V VDD. The frequency range of the PLL was from 70 MHz to 1.6 GHz. The locking time of the loop was much faster then the specified 5us. Two of the successful approaches were illustrated in this thesis report. An existing semi-digital architecture was used and some of the blocks like charge-pump and VCO were modified to achieve the bandwidth tracking. An FLL mode was added in order to eliminate the divider used for both the F sys and F ref, such that the magnitude of the error function reduces. The storage cells were also modified in order to reduce peaking at lower frequencies. In the first approach, an OPAMP was used as a voltage follower to match the node voltages in the CP with that of the VCO such that the currents in them match too. This approach, though works very well, adds an additional complexity because of the OPAMP which can add non-linearity and is difficult to model within the loop. Moreover, the pull-back voltage also needs to be dynamic in order to match the UP and DOWN currents. In the Second approach, the VCO and CP architectures were changed and made topologically equivalent. The currents are matched because of circuit matching. With good matching of transistors in the VCO and the CP, both bandwidth tracking and self-compensation can be achieved easily. This approach is both simple and efficient. Power consumption of the loop was also reduced by changing the level shifter in the VCO. Figure 5.1: Proposal 2: Bandwidth tracking graph. It was successfully shown that by making the currents in CP and VCO track each other and by making the Proportional gain (K prop ) self-compensated thus making the first term in equation 1.11 constant, the bandwidth of the loop tracks the

5.2 Future Work 73 Figure 5.2: Proposal 3: Bandwidth tracking graph. reference frequency with a constant predefined ratio (5% in this case). The performance and the transfer function of the loop remains the same over PVT corners due to the self-compensation. 5.2 Future Work The entire work described in the report except for the proposal 1 (section 3.1.1) was done at the schematic level. Schematic level design in 65nm itself has many challenges, which gets aggravated in layout. Moreover, the given designs rely on parasitics for the capacitors (for example, the load capacitances for the VCO stages is of the order of femto Farads and the CP capacitor is also designed to be a few hundred femto Farads). Given this, the layout of these blocks is very critical, since a bad layout can result in too many parasitics and change the behavior of the circuit. The following are the points which can be worked upon and can be considered as future work for this thesis. The circuit layout has to be done and results need to be measured on silicon. Divided F sys frequencies have not been tried yet. This can bring out additional challenges to the design. Output jitter can be improved. Among the three, the divided F sys frequencies seems more interesting to me, since it would require the design of a much more complex active pull-back circuit for the CP.

Part IV APPENDIX

Appendix OPAMP Design and Specifications Figure 5.3: Desired OPAMP specifications. 77

78 Figure 5.4: OPAMP characteristics. Parameter DC Gain (A o ) Common mode gain (A cm ) Phase Margin (PM) Unity Gain Bandwidth (GBW) Common Mode Rejection Ratio (CMRR) Power Supply Rejection Ratio (PSRR) Common Mode Range (CMR) Slew Rate (SR) Measured Value 60 db -26 db 86 o 22 MHz 86 db 60 db 126 mv to 881mV 8.3 V/us Table 5.1: OPAMP measured parameters.