AD720, AD72 Data Sheet August 2002 FN304.4 0Bit, 2Bit, Multiplying D/A Converters The AD720 and AD72 are monolithic, high accuracy, low cost 0bit and 2bit resolution, multiplying digitaltoanalog converters (DAC). Intersil s thinfilm on CMOS processing gives up to 0bit accuracy with TTL/CMOS compatible operation. Digital inputs are fully protected against static discharge by diodes to ground and positive supply. Typical applications include digital/analog interfacing, multiplication and division, programmable power supplies, CRT character generation, digitally controlled gain circuits, integrators and attenuators, etc. Features AD720, 0Bit Resolution; 8Bit Linearity AD72, 2Bit Resolution; 0Bit Linearity Low Power Dissipation (Max)................. 20mW Low Nonlinearity Tempco at 2ppm of FSR/ o C Current Settling Time to 0.0% of FSR...........0µs Supply Voltage Range................. ±V to +V TTL/CMOS Compatible Full Input Static Protection Ordering Information PART NUMBER LINEARITY (INL, DNL) TEMP. RANGE ( o C) PACKAGE PKG. NO. AD720JN 0.2% (8Bit) 0 to 70 Ld PDIP E.3 AD72LN 0.0% (0 Bit) 0 to 70 8 Ld PDIP E8.3 Pinouts AD720 (PDIP) TOP VIEW AD72 (PDIP) TOP VIEW BIT BIT 2 BIT 3 BIT 4 BIT 2 3 4 7 8 4 3 2 0 9 V+ (LSB) BIT 9 BIT 8 BIT 7 BIT BIT BIT 2 BIT 3 BIT 4 BIT BIT 2 3 4 7 8 9 8 7 4 3 2 0 V+ BIT 2 (LSB) BIT BIT 9 BIT 8 BIT 7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888INTERSIL or 32724743 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. All Rights Reserved
AD720, AD72 Absolute Maximum Ratings Supply Voltage (V+ to )...........................+7V............................................ ±2V Digital Input Voltage Range....................... V+ to Output Voltage Compliance..................... 00mV to V+ Operating Conditions Temperature Ranges JN, LN Versions............................. 0 o C to 70 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) Ld PDIP Package 90 N/A 8 Ld PDIP Package 80 N/A Maximum Junction Temperature (Plastic Packages).......0 o C Maximum Storage Temperature Range.......... o C to 0 o C Maximum Lead Temperature (Soldering 0s).............300 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. Do not apply voltages higher than V DD or less than potential on any terminal except and.. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V+ = +V, = +0V, T A = 2 o C Unless Otherwise Specified AD720 AD72 PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS SYSTEM PERFORMANCE (Note 2) Resolution 0 0 0 2 2 2 Bits Nonlinearity J (Note 3) (Figure 2) 0V +0V L 0V +0V (Figure 2) Nonlinearity Tempco 0V +0V (Notes 3, 4) ±0.2 (8Bit) ±0.0 (0Bit) % of FSR ±0.0 (0Bit) % of FSR ±2 ±2 ppm of FSR/ o C Gain Error ±0.3 ±0.3 % of FSR Gain Error Tempco ±0 ±0 ppm of FSR/ o C Output Leakage Current (Either Output) DYNAMIC CHARACTERISTICS Output Current Settling Time Feedthrough Error REFERENCE INPUT Input Resistance Over the Specified Temperature Range To 0.0% of FSR (All Digital Inputs Low To High And High To Low) (Note 4) (Figure 7) = 20V PP, 00kHz All Digital Inputs Low (Note 4) (Figure ) All Digital Inputs High at Ground ±200 ±200 na.0.0 µs 0 0 mv PP 0 20 0 20 kω ANALOG OUTPUT Output Capacitance All Digital Inputs High 200 200 pf (Note 4) (Figure ) 7 7 pf All Digital Inputs Low 7 7 pf (Note 4) (Figure ) 200 200 pf Output Noise Both Outputs (Note 4) (Figure 4) Equivalent to 0kΩ Equivalent to 0kΩ Johnson Noise DIGITAL INPUTS Low State Threshold, V IL Over the Specified 0.8 0.8 V High State Threshold, V Temperature Range IH 2.4 2.4 V V IN = 0V or +V Input Current, I IL, I IH ± ± µa Input Coding See Tables and 2 Binary/Offset Binary 2
AD720, AD72 Electrical Specifications PARAMETER POWER SUPPLY CHARACTERISTICS Power Supply Rejection V+ = 4.V to.v (Note 3) (Figure 3) Functional Diagram V+ = +V, = +0V, T A = 2 o C Unless Otherwise Specified (Continued) TEST CONDITIONS AD720 AD72 MIN TYP MAX MIN TYP MAX ±0.00 ±0.00 % FSR/% V+ Power Supply Voltage Range + to + + to + V I+ All Digital Inputs at 0V or V+ ± ± µa Excluding Ladder Network All Digital Inputs High or Low 2 2 ma Excluding Ladder Network Total Power Dissipation Including the Ladder Network 20 20 mw 2. Full Scale Range (FSR) is 0V for Unipolar and ±0V for Bipolar modes. 3. Using internal feedback resistor. 4. Guaranteed by design, or characterization and not production tested.. Accuracy not guaranteed unless outputs at potential.. Accuracy is tested and guaranteed at V+ = V only. UNITS 0kΩ 0kΩ 0kΩ 0kΩ SPDT NMOS SWITCHES MSB Switches shown for Digital Inputs High. Resistor values are typical. BIT 2 BIT 3 0kΩ Pin Descriptions AD720 AD72 PIN NAME DESCRIPTION IOUT Current Out summing junction of the R2R ladder network. 2 2 IOUT2 Current Out virtual ground, return path for the R2R ladder network. 3 3 Digital Ground. Ground potential for digital side of D/A. 4 4 Bits Most Significant Digital Data Bit. Bit 2 Digital Bit 2. Bit 3 Digital Bit 3. 7 7 Bit 4 Digital Bit 4. 8 8 Bit Digital Bit. 9 9 Bit Digital Bit. 0 0 Bit 7 Digital Bit 7. Bit 8 Digital Bit 8. 2 2 Bit 9 Digital Bit 9. 3 3 Bit 0 Digital Bit 0 (AD72). Least Significant Digital Data Bit (AD720). 4 Bit Digital Bit (AD72). Bit 2 Least Significant Digital Data Bit (AD72). 4 V+ Power Supply +V to +V. 7 Voltage Reference Input to set the output range. Supplies the R2R resistor ladder. 8 RFEEDBACK Feedback resistor used for the current to voltage conversion when using an external Op Amp. 3
AD720, AD72 Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a best straight line through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of N bits can resolve output changes of 2 N of the fullscale range, e.g., 2 N for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., / 2 LSB) for a given digital input change, i.e., all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full scale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of LSB. Feedthrough Error: Error caused by capacitive coupling from to with all digital inputs LOW. current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between and buses which must be held either at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents. Output Capacitance: Capacitance from and terminals to ground. Output Leakage Current: Current which appears on terminal when all digital inputs are LOW or on terminal when all digital inputs are HIGH. V+ 3 4 TO LADDER 8 9 Detailed Description The AD720 and AD72 are monolithic, multiplying D/A converters. A highly stable thin film R2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS compatible operation. An external voltage or DTL/TTL/ CMOS INPUT 2 7 FIGURE. CMOS LEVEL SHIFTER AND SWITCH Test Circuits The following test circuits apply for the AD720. Similar circuits are used for the AD72. 0BIT BINARY COUNTER CLOCK BIT (LSB) BIT BIT R FEEDBACK 4 I OUT AD720 HA200 I 3 OUT2 3 2 + +V 2BIT REFERENCE DAC 0kΩ 0.0% 0kΩ 0.0% MΩ HA200 + LINEARITY ERROR x 00 +0V BIT (LSB) +V UNGROUNDED SINE WAVE GENERATOR 40Hz V PP K 0.0% kω 0.0% 4 4 AD720 HA200 3 3 2 + 00kΩ HA200 + V ERROR x 00 BIT 2 FIGURE 2. NONLINEARITY FIGURE 3. POWER SUPPLY REJECTION 4
AD720, AD72 Test Circuits The following test circuits apply for the AD720. Similar circuits are used for the AD72. (Continued) +V (ADJUST FOR V OUT = 0V) µf K +V 4 00Ω 0kΩ 4 2 AD720 0ALN 3 3 + V OUT 0kΩ kω 0.µF 0V f = khz BW = Hz QUAN TECH MODEL 34D WAVE ANALYZER +V BIT (LSB) NC +V 4 4 AD720 3 3 2 NC kω SCOPE 00mV PP MHz FIGURE 4. NOISE FIGURE. OUTPUT CAPACITANCE = 20V PP 00kHz SINE WAVE BIT (LSB) +V 4 4 AD720 3 3 2 3 2 HA200 V OUT + +V 0V +0V BIT DIGITAL INPUT (LSB) EXTRAPOLATE +V 4 4 AD720 +00mV 3 3 2 00Ω t: % SETTLING (mv) 8t: 0.03% SETTLING t = RISE TIME SCOPE FIGURE. FEEDTHROUGH ERROR FIGURE 7. OUTPUT CURRENT SETTLING TIME Applications Unipolar Binary Operation The circuit configuration for operating the AD720 in unipolar mode is shown in Figure 8. Similar circuits can be used for AD72. With positive and negative values the circuit is capable of 2Quadrant multiplication. The Digital Input Code/Analog Output Value table for unipolar mode is given in Table. DIGITAL INPUT BIT (LSB) +V 4 4 AD720 3 3 2 + V OUT FIGURE 8. UNIPOLAR BINARY OPERATION (2QUADRANT MULTIPLICATION) TABLE. CODE TABLE UNlPOLAR BINARY OPERATION DIGITAL INPUT (2 N ) ANALOG OUTPUT 00000000 ( / 2 + 2 N ) 000000000 /2 0 ( / 2 2 N ) 000000000 (2 N ) 0000000000 0. LSB = 2 N. 2. N = 8 for 720 N = 0 for 72. Zero Offset Adjustment. Connect all digital inputs to. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V at V OUT. Gain Adjustment. Connect all digital inputs to V+. 2. Monitor V OUT for a (2 N ) reading. (N = 8 for AD720 and N = 0 for AD72).
AD720, AD72 3. To decrease V OUT, connect a series resistor (0 to 20Ω) between the reference voltage and the terminal. 4. To increase V OUT, connect a series resistor (0 to 20Ω) in the amplifier feedback loop. Bipolar (Offset Binary) Operation The circuit configuration for operating the AD720 in the bipolar mode is given in Figure 9. Similar circuits can be used for AD72. Using offset binary digital input codes and positive and negative reference voltage values, 4Quadrant multiplication can be realized. The Digital Input Code/Analog Output Value table for bipolar mode is given in Table 2. DIGITAL INPUT BIT (LSB) +V TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE DIGITAL INPUT + R3 0MΩ 4 4 AD720 3 R 0K R2 0K 3 2 0.0% 0.0% + FIGURE 9. BIPOLAR OPERATION (4QUADRANT MULTIPLICATION) ANALOG OUTPUT V OUT A Logic input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT bus. A Logic 0 input forces the bit current to IOUT2 bus. For any code the IOUT and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance amplifier at IOUT output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB = Logic, all other bits = Logic 0 ), is corrected by using an external resistor, (0MW), from VREF to IOUT2. Offset Adjustment. Adjust to approximately +0V. 2. Connect all digital inputs to Logic. 3. Adjust amplifier offset adjust trimpot for 0V ±mv at amplifier output. 4. Connect MSB (Bit ) to Logic and all other bits to Logic 0.. Adjust amplifier offset adjust trimpot for 0V ±mv at V OUT. Gain Adjustment. Connect all digital inputs to V+. 2. Monitor V OUT for a (2 (N) volts reading. (N = 8 for AD720, and N = 0 for AD72.). 3. To increase V OUT, connect a series resistor of up to 20Ω between V OUT and. 4. To decrease V OUT, connect a series resister of up to 20Ω between the reference voltage and the terminal. (2 (N) ) 00000000 (2 (N) ) 000000000 0 0 (2 (N) ) 000000000 (2 (N) ) 0000000000. LSB = 2 (N). 2. N = 8 for 720 N = 0 for 72.
AD720, AD72 Die Characteristics DIE DIMENSIONS: 0 mils x 03 mils (2µm x 2µm) METALLIZATION: Type: Pure Aluminum Thickness: 0 ±kå PASSIVATION: Type: PSG/Nitride PSG: 7 ±.4kÅ Nitride: 8 ±.2kÅ PROCESS: CMOS Metal Gate Metallization Mask Layout AD720 PIN 7 BIT 4 PIN BIT 3 PIN BIT 2 PIN 4 BIT PIN 3 PIN 8 BIT PIN 2 I OUT 2 PIN I OUT PIN 9 BIT PIN 0 BIT 7 PIN PIN BIT 8 PIN PIN 4 V+ PIN 2 BIT 9 PIN 3 (LSB) NC NC 7
AD720, AD72 Die Characteristics DIE DIMENSIONS: 0 mils x 03 mils (2µm x 2µm) METALLIZATION: Type: Pure Aluminum Thickness: 0 ±kå PASSIVATION: Type: PSG/Nitride PSG: 7 ±.4kÅ Nitride: 8 ±.2kÅ PROCESS: CMOS Metal Gate Metallization Mask Layout AD72 PIN 7 BIT 4 PIN BIT 3 PIN BIT 2 PIN 4 BIT PIN 3 PIN 8 BIT PIN 2 I OUT 2 PIN I OUT PIN 9 BIT PIN 0 BIT 7 PIN 8 PIN BIT 8 PIN 7 PIN V+ PIN 2 BIT 9 PIN 3 PIN 4 BIT PIN BIT 2 (LSB) 8
AD720, AD72 DualInLine Plastic Packages (PDIP) INDEX AREA N 2 3 N/2 B A D E BASE PLANE A2 C A SEATING PLANE L C L D A e D A B e e C C B e B 0.00 (0.2) M C A B S. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y4.M982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 9. 4. Dimensions A, A and L are measured with the package seated in JE DEC seating plane gauge GS3.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.2mm).. E and e A are measured with the leads constrained to be perpendicular to datum C. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.2mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/2 and N/2 + ) for E8.3, E.3, E8.3, E28.3, E42. will have a B dimension of 0.030 0.04 inch (0.7.4mm). E E.3 (JEDEC MS00BB ISSUE D) LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.20.33 4 A 0.0 0.39 4 A2 0. 0.9 2.93 4.9 B 0.04 0.022 0.3 0.8 B 0.04 0.070..77 8, 0 C 0.008 0.04 0.204 0.3 D 0.73 0.77 8. 9.8 D 0.00 0.3 E 0.300 0.32 7.2 8.2 E 0.240 0.280.0 7. e 0.00 BSC 2.4 BSC e A 0.300 BSC 7.2 BSC e B 0.430 0.92 7 L 0. 0.0 2.93 3.8 4 N 9 Rev. 0 2/93 9
AD720, AD72 DualInLine Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B C A N 2 3 N/2 B D e D E. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y4.M982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 9. 4. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS3.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.2mm).. E and e A are measured with the leads constrained to be perpendicular to datum C. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.2mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/2 and N/2 + ) for E8.3, E.3, E8.3, E28.3, E42. will have a B dimension of 0.030 0.04 inch (0.7.4mm). B A 0.00 (0.2) M C A A2 L B S A e C E C L e A C e B E8.3 (JEDEC MS00BC ISSUE D) 8 LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.20.33 4 A 0.0 0.39 4 A2 0. 0.9 2.93 4.9 B 0.04 0.022 0.3 0.8 B 0.04 0.070..77 8, 0 C 0.008 0.04 0.204 0.3 D 0.84 0.880 2.47 22.3 D 0.00 0.3 E 0.300 0.32 7.2 8.2 E 0.240 0.280.0 7. e 0.00 BSC 2.4 BSC e A 0.300 BSC 7.2 BSC e B 0.430 0.92 7 L 0. 0.0 2.93 3.8 4 N 8 8 9 Rev. 0 2/93 All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 0