NVLJD7NZ Small Signal MOSFET V, 2 ma, Dual, N Channel, Gate ESD Protection, 2x2 WDFN Package Features Optimized Layout for Excellent High Speed Signal Integrity Low Gate Charge for Fast Switching Small 2 x 2 mm Footprint ESD Protected Gate AEC Q Qualified and PPAP Capable These Devices are Pb Free and are RoHS Compliant V (BR)DSS. @. V V 2 ma 2. @ 2. V D () R DS(on) Typ @ V GS I D MAX (Note ) D () MAXIMUM RATINGS ( unless otherwise noted) Parameter Symbol Value Unit Drain to Source Voltage V DSS V Gate to Source Voltage V GS V Continuous Drain Current (Note ) Power Dissipation (Note ) Steady State = 2 C I D 2 ma Steady State = 2 C P D 7 mw Pulsed Drain Current t P s I DM.2 A Operating Junction and Storage Temperature T J, T STG to Continuous Source Current (Body Diode) I SD 2 ma Lead Temperature for Soldering Purposes (/8 from case for s) C T L 2 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE RATINGS Parameter Symbol Max Unit Junction to Ambient Steady State (Note ) R JA C/W. Surface mounted on FR board using in sq pad size (Cu area =.27 in sq [ oz] including traces). G (2) S () N Channel S G S2 JG M 2 WDFN CASE AN 2 = Specific Device Code = Date Code = Pb Free Package PIN CONNECTIONS G () D S () N Channel MARKING DIAGRAM JG (Note: Microdot may be in either location) D G2 (Top View) ORDERING INFORMATION Device Package Shipping NVLJD7NZTAG NVLJD7NZTBG WDFN (Pb Free) WDFN (Pb Free) /Tape & Reel /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8/D. Semiconductor Components Industries, LLC, 2 May, 2 Rev. Publication Order Number: NVLJD7NZ/D
NVLJD7NZ ELECTRICAL CHARACTERISTICS ( unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = A V Drain to Source Breakdown Voltage Temperature Coefficient V (BR)DSS /T J Reference to 2 C, I D = A 27 mv/ C Zero Gate Voltage Drain Current I DSS V GS = V, V DS = V. A Zero Gate Voltage Drain Current I DSS V GS = V, V DS = 2 V, T = 8 C. A Gate to Source Leakage Current I GSS V DS = V, V GS = ± V ±2 A Gate to Source Leakage Current I GSS V DS = V, V GS = ± V ±. A Gate to Source Leakage Current I GSS V DS = V, V GS = ± V T = 8 C ±. A ON CHARACTERISTICS (Note 2) Gate Threshold Voltage V GS(TH) V DS = V GS, I D = A... V Threshold Temperature Coefficient V GS(TH) /T J Reference to 2 C, I D = A 2. mv/ C Drain to Source On Resistance R DS(on) V GS =. V, I D = 2 ma. 7. V GS = 2. V, I D = 2 ma 2. 7. Forward Transconductance g FS V DS = V, I D = 2 ma 8 ms CAPACITANCES & GATE CHARGE Input Capacitance C ISS 2.2 2 Output Capacitance C OSS V DS =. V, f = MHz, V GS = V Reverse Transfer Capacitance C RSS.. Total Gate Charge Q g Gate to Source Charge Q gs V DS = 2 V, I D = ma,.2 Gate to Drain Charge Q gd V GS =. V.2 Plateau Voltage V GP.7 V SWITCHING CHARACTERISTICS (Note ) Turn On Delay Time t d(on) Rise Time t r V GS =. V, V DS = 2 V, Turn Off Delay Time t d(off) I D = 2 ma, R G = 9 Fall Time t f 72.7 pf nc 9 ns DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD V GS = V, I S = 2 ma.79.9 V 2. Pulse Test: pulse width s, duty cycle 2%.. Switching characteristics are independent of operating junction temperatures. ns 2
NVLJD7NZ TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (A).2...9.8.7.....2. V GS = V. V. V. V.2. V DS = V.. V.9.8. V.7 T J = C 2.8 V. T J = C 2. V. 2. V. 2.2 V. 2. V.2.8 V.... 2. 2......... 2. 2..... I D, DRAIN CURRENT (A) V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Region Characteristics Figure 2. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) 9. 8. 7..... 2. I D = 2 ma.. 2. 2.... V GS, GATE VOLTAGE (V). R DS(on), DRAIN TO SOURCE RESISTANCE ( ) 9. 8. 7..... 2. T J = C I D, DRAIN CURRENT (A) V GS = 2. V V GS =. V. T J = C..2.....7.8.9...2 Figure. On Resistance vs. Gate to Source Voltage Figure. On Resistance vs. Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED).9.8 I D = 2 ma.7 V GS =. V.....2...9.8.7.. 2 2 7 2 T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature I DSS, LEAKAGE (na) T J = C T J = 8 C Figure. Drain to Source Leakage Current vs. Voltage 2 2
NVLJD7NZ TYPICAL PERFORMANCE CURVES C, CAPACITANCE (pf) 2 2 2 Figure 7. Capacitance Variation V GS = V f = MHz 2 C iss C oss C rss V GS, GATE TO SOURCE VOLTAGE (V)..... 2. 2.... Q GS V DS Q GD..2.....7.8 Q T V GS Q G, TOTAL GATE CHARGE (nc) V DS = 2 V I D = ma Figure 8. Gate to Source and Drain to Source Voltage vs. Total Charge 2 2 t, TIME (ns) V GS =. V V DD = 2 V I D = 2 ma t d(off) t f t T r J = 2 C t d(on) I S, SOURCE CURRENT (A) T J = C T J = 8 C R G, GATE RESISTANCE ( ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance....7 T J = C.8.9.. V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage vs. Current I D, DRAIN CURRENT (A).... V GS V Single Pulse T C = 2 C R DS(on) Limit Thermal Limit Package Limit Figure. Maximum Rated Forward Biased Safe Operating Area s s ms ms dc
NVLJD7NZ TYPICAL PERFORMANCE CURVES THERMAL R(t), EFFECTIVE TRANSIENT RESPONSE Duty Cycle =..2...2 Single Pulse. E E E E E 2 E E+ E+ E+2 E+ t, TIME (s) R JA Steady State = C/W Figure 2. Thermal Impedance (Junction to Ambient)
PIN ONE REFERENCE. C. C. C.8 C NOTE L DETAIL A K e D ÍÍ ÍÍ A SIDE VIEW TOP VIEW DETAIL B BOTTOM VIEW A F A B E E2 A X b. C. C NVLJD7NZ PACKAGE DIMENSIONS PLATING C. C A B SEATING PLANE A NOTE WDFN 2x2,.P CASE AN ISSUE F ÇÇ L. C A B B EXPOSED Cu DETAIL B OPTIONAL CONSTRUCTIONS L DETAIL A OPTIONAL CONSTRUCTIONS MOLD CMPD X.7 PACKAGE OUTLINE L NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99. 2. CONTROLLING DIMENSION: MILLIMETERS.. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN. AND. mm FROM THE TERMINAL TIP.. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A.7.8 A.. A.2 REF b.2. D 2. BSC.7.77 E 2. BSC E2.9. e. BSC F. BSC K.2 REF L.2. L ---. STYLE : PIN. SOURCE 2. GATE. SOURCE 2. DRAIN 2. GATE 2. DRAIN SOLDERMASK DEFINED MOUNTING FOOTPRINT.7 2X.77. 2. X.. PITCH DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 827 USA Phone: 7 27 or 8 8 Toll Free USA/Canada Fax: 7 27 or 8 87 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8 282 98 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 2 79 29 Japan Customer Focus Center Phone: 8 87 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NVLJD7NZ/D