74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -m Process 500-mA Typical Latch-Up Immunity at 25 C Package Optio Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 00-mil DIPs (NT) DB, DW, OR NT PACKAGE (TOP VIEW) Q 2Q Q 4Q 5Q 6Q 7Q 8Q 2 4 5 6 7 8 9 0 2 24 2 22 2 20 9 8 7 6 5 4 2D D 4D V CC V CC 5D 6D 7D 8D description This 8-bit latch features -state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the 74A7 are traparent D-type latches. While the latch-enable () input is high, the Q outputs follow the data (D) inputs. When is taken low, the Q outputs are latched at the levels set up at the D inputs. can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. does not affect the internal operatio of the latches. Old data can be retained or new data can be entered while the outputs are off. The 74A7 is characterized for operation from 40 C to 85 C. FUNCTION TAB (each latch) INPUTS OUTPUT D Q L H H H L H L L L L X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Itruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 996, Texas Itruments Incorporated POST OFFICE BOX 6550 DALLAS, TEXAS 75265
74A7 logic symbol 24 EN 2D D 4D 5D 6D 7D 8D 2 22 2 20 7 6 5 4 2 4 9 0 2 Q 2Q Q 4Q 5Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-2. logic diagram (positive logic) 24 2 Q 2D 22 2 2Q D 2 Q 4D 20 4 4Q 5D 7 9 5Q 6D 6 0 6Q 7D 5 7Q 8D 4 2 8Q 2 POST OFFICE BOX 6550 DALLAS, TEXAS 75265
74A7 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC.......................................................... 0.5 V to 6 V Input voltage range, V I (see Note )............................................ 0.5 V to V CC + 0.5 V voltage range, V O (see Note )......................................... 0.5 V to V CC + 0.5 V Input clamp current, I IK (V I < 0 or V I > V CC )................................................. ±20 ma clamp current, I OK (V O < 0 or V O > V CC )............................................ ±50 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±50 ma Continuous current through V CC or.................................................. ±200 ma Maximum power dissipation at T A = 55 C (in still air) (see Note 2): DB package.................. 0.65 W DW package...................7 W NT package.................... W Storage temperature range, T stg.................................................... 65 C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 50 C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. recommended operating conditio MIN NOM MAX UNIT Supply voltage 5 5.5 V = V 2. VIH High-level input voltage = 4.5 V.5 V = 5.5 V.85 = V 0.9 VIL Low-level input voltage = 4.5 V.5 V = 5.5 V.65 VI Input voltage 0 V VO voltage 0 V = V 4 IOH High-level output current = 4.5 V 24 ma = 5.5 V 24 = V 2 IOL Low-level output current = 4.5 V 24 ma t/v Input traition rise or fall rate = 5.5 V 24 0 5 Data, 0 0 TA Operating free-air temperature 40 85 C /V POST OFFICE BOX 6550 DALLAS, TEXAS 75265
74A7 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25 C MIN TYP MAX V 2.9 2.9 IOH = 50 A 4.5 V 4.4 4.4 5.5 V 5.4 5.4 VOH IOH = 4 ma V 2.58 2.48 V 4.5 V.94.8 IOH = 24 ma 5.5 V 4.94 4.8 IOH = 75 ma 5.5 V.85 V 0. 0. IOL = 50 A 4.5 V 0. 0. 5.5 V 0. 0. VOL IOL = 2 ma V 0.6 0.44 V 4.5 V 0.6 0.44 IOL =24mA 5.5 V 0.6 0.44 IOL = 75 ma 5.5 V.65 IOZ VO = or 5.5 V ±0.5 ±5 A II VI = or 5.5 V ±0. ± A ICC VI = or, IO = 0 5.5 V 8 80 A Ci VI = or 5 V 4 pf Co VO = or 5 V 0 pf Not more than one output should be tested at a time, and the duration of the test should not exceed 0 ms. timing requirements over recommended operating free-air temperature range, V CC =. V ± 0. V (unless otherwise noted) (see Figure ) TA = 25 C MIN MAX tw Pulse duration, high 5.5 5.5 tsu Setup time, data before 4 4 th Hold time, data after 2 2 timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) TA = 25 C MIN MAX tw Pulse duration, high 4 4 tsu Setup time, data before.5.5 th Hold time, data after 2 2 4 POST OFFICE BOX 6550 DALLAS, TEXAS 75265
74A7 switching characteristics over recommended operating free-air temperature range, V CC =. V ± 0. V (unless otherwise noted) (see Figure ) PARAMETER tpzh tpzl tphz tplz FROM TO TA = 25 C (INPUT) (OUTPUT) MIN TYP MAX D Q.5 9..5 4.8.5 8 0.6.5.7.5 0 4.5.5 6..5 9.5 2.8.5 4.2.5 9..5 4.7.5 8.5.6.5..5 9.5 2.5 2.7.5 7.5 0.2.5 0.8 switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) PARAMETER tpzh tpzl tphz tplz FROM TO TA = 25 C (INPUT) (OUTPUT) MIN TYP MAX D Q.5 6 8.9.5 0..5 5.5 7.6.5 8.4.5 6.5 0.5..5 6.5 9..5 0.2.5 6.5 9.5.5 0.8.5 6 8.6.5 9.7.5 8.5 0.6.5..5 6 8.2.5 8.7 operating characteristics, V CC = 5 V, T A = 25 C Cpdd PARAMETER TEST CONDITIONS TYP UNIT s enabled 47 Power dissipation capacitance per latch CL =50pF pf, f=mhz pf s disabled 6 POST OFFICE BOX 6550 DALLAS, TEXAS 75265 5
74A7 PARAMETER MEASUREMENT INFORMATION 2 From Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S Open TEST / tplz/tpzl tphz/tpzh S Open 2 LOAD CIRCUIT Input tw Timing Input (see Note B) Data Input tsu th Input In-Phase Out-of-Phase VOH VOL VOH VOL Control (low-level enabling) Waveform S at 2 (see Note B) Waveform 2 S at (see Note B) tpzl tpzh tplz tphz 20% 80% VOL VOH NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr =, tf =. D. The outputs are measured one at a time with one input traition per measurement. Figure. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 6550 DALLAS, TEXAS 75265
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