NLAST45 Analog Multiplexer/ Demultiplexer TTL Compatible, Single Pole, 8 Position Plus Common Off The NLAST45 is an improved version of the MC45 and MC74HC45 fabricated in sub micron Silicon Gate CMOS technology for lower R DS(on) resistance and improved linearity with low current. This device may be operated either with a single supply or dual supply up to ±3 to pass a 6 PP signal without coupling capacitors. When operating in single supply mode, it is only necessary to tie EE, pin 7 to ground. For dual supply operation, EE is tied to a negative voltage, not to exceed maximum ratings. Translation is provided in the device, the Address and Inhibit are standard TTL level compatible. For CMOS compatibility see NLAS45. Pin for pin compatible with all industry standard versions of 45. Features Improved R DS(on) Specifications Pin for Pin Replacement for MAX45 and MAX45A One Half the Resistance Operating at 5. Single or Dual Supply Operation Single 3. 5. Operation, or Dual ±3 Operation With of 3. to 3.3, Device Can Interface with.8 Logic, No Translators Needed Address and Inhibit Logic are Over oltage Tolerant and May Be Driven Up +6 Regardless of Address and Inhibit Pins Standard TTL Compatible Greatly Improved Noise Margin Over MAX45 and MAX45A True TTL Compatibility IL =.8, IH = 2. Improved Linearity Over Standard HC45 Devices Popular SOIC, and Space Saving TSSOP, and QSOP 6 Pin Packages Pb Free Packages are Available* NO 2 NO 4 NO NO 6 ADD C ADD B ADD A 6 5 4 3 2 9 6 SOIC 6 D SUFFIX CASE 75B TSSOP 6 DT SUFFIX CASE 948F QSOP 6 QS SUFFIX CASE 492 MARKING DIAGRAMS A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. 6 6 NLAST45 AWLYWW AST 45 ALYW NLAST 45 ALYW 2 3 4 5 6 7 NO NO 3 COM NO 7 NO 5 Inhibit EE GND Figure. Pin Connection (Top iew) *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8 Semiconductor Components Industries, LLC, 26 April, 26 Rev. 4 Publication Order Number: NLAST45/D
NLAST45 TRUTH TABLE Inhibit Address ON SWITCHES* NO X don t care C B A X don t care X don t care All switches open NO NO 2 COM NO COM NO COM NO 3 COM NO 2 NO 4 COM NO 3 NO 5 COM NO 4 COM NO 5 NO 6 COM NO 6 NO 7 COM NO 7 *NO and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well in either direction. ADD C ADD B ADD A LOGIC Inhibit Figure 2. Logic Diagram ÎÎÎ MAXIMUM RATINGS ÎÎÎ Symbol Parameter alue Unit EE Î ÎÎ ÎÎÎ Negative DC Supply oltage (Referenced to GND) 7. to.5 Î Positive DC Supply oltage (Note ) (Referenced to GND) ÎÎ.5 to 7. ÎÎÎ (Referenced to EE ) ÎÎ.5 to 7. ÎÎÎ IS Î Analog oltage ÎÎ EE.5 to.5 ÎÎÎ IN Î Digital oltage (Referenced to GND) ÎÎ.5 to 7. ÎÎÎ I Î DC Current, Into or Out of Any Pin ÎÎ 5 ÎÎÎ ma T STG Storage Temperature Range 65 to 5 ÎÎÎÎ C T L Lead Temperature, mm from Case for Seconds 26 C ÎÎÎ T J Junction Temperature under Bias 5 C ÎÎÎ JA Thermal Resistance SOIC 43 C/W Î TSSOPÎÎ 64 ÎÎÎ QSOPÎÎ 64 ÎÎÎ P D Î Power Dissipation in Still Air SOICÎÎ 5 ÎÎÎ mw TSSOP 45 QSOPÎÎ 45 ÎÎÎ MSL Î Moisture Sensitivity ÎÎ Level ÎÎÎ F R Î Flammability Rating Oxygen Index: 3% 35% ÎÎ UL 94 @. in ÎÎÎ ESD Î ESD Withstand oltage Human Body Model (Note 2) ÎÎ 2 ÎÎÎ Machine Model (Note 3) 2 Charged Device Model (Note 4) ÎÎ ÎÎÎ I LATCHUP Î Latchup Performance Above and Below GND at C (Note 5)ÎÎ 3 ÎÎÎ ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. The absolute value of EE 7.. 2. Tested to EIA/JESD22 A4 A. 3. Tested to EIA/JESD22 A5 A. 4. Tested to JESD22 C A. 5. Tested to EIA/JESD78. 2
NLAST45 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit EE ÎÎ Negative DC Supply oltage (Referenced to GND) 5.5ÎÎÎÎ GND ÎÎÎ ÎÎ Positive DC Supply oltage (Referenced to GND) ÎÎÎ 2.5 ÎÎÎÎ 5.5 ÎÎÎ (Referenced to EE ) 2.5 6.6 ÎÎÎ IS Analog oltage EE Î ÎÎ ÎÎÎ IN Digital oltage (Note 6) (Referenced to GND) 5.5 ÎÎÎ T A Operating Temperature Range, All Package Types 55 ÎÎÎÎ ÎÎÎ C t r, t f ÎÎ Rise/Fall Time ÎÎÎ = 3..3 Î (Channel Select or Enable s) = 5..5 ÎÎÎ ÎÎÎÎ 2 ÎÎÎ ns/ 6. Unused digital inputs may not be left open. All digital inputs must be tied to a high logic voltage level or a low logic input voltage level. DC CHARACTERISTICS Digital Section (oltages Referenced to GND) Symbol Parameter Condition IH IL I IN I CC Minimum High Level oltage, Address or Inhibit s Maximum Low Level oltage, Address or Inhibit s Maximum Leakage Current, Address or Inhibit s Maximum Quiescent Supply Current (per Package) 3. 5.5 3. 5.5 Guaranteed Limit 55 to C 85 C C.6 2. 2..5.8.8.6 2. 2..5.8.8.6 2. 2..5.8.8 IN = 6. or GND to 6.... A Address or Inhibit and IS = or GND Unit 6. 4. 4 8 A DC ELECTRICAL CHARACTERISTICS Analog Section ÎÎ Î ÎÎÎÎ Symbol ÎÎÎÎ Parameter ÎÎÎÎ Test Conditions ÎÎÎ ÎÎ Guaranteed Limit ÎÎ EE 55 to C ÎÎÎ 85 C ÎÎÎÎ C ÎÎ Unit ÎÎÎÎ R ON ÎÎÎÎ ÎÎÎÎ Maximum ON Resistance ÎÎÎÎ IN = IL or IH IS = ( EE to ÎÎÎ 3. ÎÎ 86 ÎÎÎ 8ÎÎÎÎ 2 ÎÎ ) 37 46 55 ÎÎÎÎ ÎÎÎÎ I S = ma ÎÎÎ 3. ÎÎ 3. 26 ÎÎÎ 33 ÎÎÎÎ 37 ÎÎ (Figures 4 thru 9) ÎÎÎ R ÎÎÎÎ ON Maximum Difference in ON ÎÎÎÎ Resistance Between Any Two ÎÎÎÎ IN = IL or IH, IS = 2. 3. 5 2 2 IS = 3. ÎÎÎ ÎÎ 3 ÎÎÎ 8 ÎÎÎÎ 8 ÎÎ Channels in the Same Pack- I S = ma, IS = 2. ÎÎÎ 3. ÎÎ 3. ÎÎÎ 5 ÎÎÎÎ 5 ÎÎ age Rflat (ON) ON Resistance Flatness COM =, 2, 3.5 COM = 2,, 2 I NC(OFF) I NO(OFF) I COM(ON) Maximum Off Channel Leakage Current Maximum On Channel Leakage Current, Channel to Channel Switch Off IN = IL or IH IO =. or EE +. (Figure 7) Switch On IO =. or EE +. (Figure 7) 3. 3. 6. 3. 6. 3. 3. 3. 4 2.... 4 2 5. 5. 5. 5. 5 3 na na 3
NLAST45 AC CHARACTERISTICS ( t r = t f = 3 ns) ÎÎ Guaranteed Limit ÎÎ ÎÎ ÎÎÎÎ Symbol Parameter ÎÎÎ Test Conditions ÎÎÎ CC ÎÎ 55 to CÎÎ EE ÎÎÎ MinÎÎÎ Typ* ÎÎÎ 85 CÎÎÎÎ C ÎÎ Unit t BBM Minimum Break Before Make Time IN = IL or IH IS = R L = 3 C L = 35 pf (Figure 9) *Typical Characteristics are at C. AC CHARACTERISTICS (C L = 35 pf, t r = t f = 3 ns) 3. 3... 3.... 6.5 5. 3.5 Guaranteed Limit ns Symbol Parameter EE 55 to C 85 C C Min Typ Max Min Max Min Max Unit t TRANS Transition Time (Address Selection Time) (Figure 8) 2.5 3. 3. 3. 4 28 23 23 45 3 5 35 3 28 ns t ON Turn on Time (Figures 4, 5, 2, and 2) Enable to N O or N C 2.5 3. 3. 3. 4 28 23 23 45 3 5 35 3 28 ns t OFF Turn off Time (Figures 4, 5, 2, and 2) Enable to N O or N C 2.5 3. 3. 3. 4 28 23 23 45 3 5 35 3 28 ns Typical @ C, = 5. C IN Maximum Capacitance,Select s 8 pf C NO or C NC Analog I/O C COM Common I/O C (ON) Feedthrough. ADDITIONAL APPLICATION CHARACTERISTICS (GND = ) Symbol Parameter Condition EE Typ C Unit BW Maximum On Channel Bandwidth or Minimum Frequency Response IS = ½ ( EE ) Source Amplitude = dbm (Figures and 22) 3. 6. 3.... 3. 8 9 95 95 MHz ISO Off Channel Feedthrough Isolation f = khz; IS = ½ ( EE ) Source = dbm (Figures 2 and 22) 3. 6. 3.... 3. 93 93 93 93 db ONL Maximum Feedthrough On Loss IS = ½ ( EE ) Source = dbm (Figures and 22) 3. 6. 3.... 3. 2 2 2 2 db Q Charge Injection IN = to EE, f IS = khz, t r = t f = 3 ns R IS =, C L = pf, Q = C L * OUT (Figures 6 and 23) 5. 3.. 3. 9. 2 pc THD Total Harmonic Distortion THD + Noise f IS = MHz, R L = K, C L = 5 pf, IS = 5. PP sine wave IS = 6. PP sine wave (Figure 3) 6. 3.. 3...5 % 4
NLAST45 8 2. I CC (na).... = 3. = 5. R ON ( ) 6 4 2 3.3 3. 5.5. 4 2 2 6 8 2 Temperature ( C) Figure 3. I CC versus Temp, = 3 and 5 4. 2. 2. 4. 6. IS (DC) Figure 4. R ON versus, Temp = C R ON ( ) 9 8 7 6 5 4 3 2 C C 85 C 55 C.5..5 2. Com () Figure 5. Typical On Resistance = 2., EE = R ON ( ) 5 4 3 2 C 85 C C 55 C.5..5 2. 2.5 3. Com () Figure 6. Typical On Resistance = 3., EE = 2 85 C C 2 85 C C R ON ( ) 5 C 55 C R ON ( ) 5 55 C C 5 5.5..5 2. 2.5 3. 3.5 4. Com () Figure 7. Typical On Resistance =, EE =.5.5 2 2.5 3 3.5 4 5 5.5 Com () Figure 8. Typical On Resistance = 5.5, EE = 5
NLAST45 2 85 C C R ON ( ) 5 C 55 C 5 4 2 2 4 Com () Figure 9. Typical On Resistance = 3.3, EE = 3.3 5 9 BANDWIDTH (db) 4 3 2 2 3 4 5 BANDWIDTH (ON RESPONSE).. PHASE SHIFT 8%/DI (db) 72 54 36 8 8 36 54 72 9 PHASE SHIFT.. FREQUENCY (mhz) FREQUENCY (mhz) Figure. Bandwidth Figure. Phase Shift OFF ISOLATION db/di 2 3 4 5 6 7 8 9 DISTORTION (%). 5.5 3. 3.3.. FREQUENCY (mhz) Figure 2. Off Isolation. FREQUENCY (mhz) Figure 3. Total Harmonic Distortion 6
NLAST45 3 3 T A = C = 2 2 TIME (ns) 5 t ON (ns) TIME (ns) 5 t ON 5 t OFF (ns) 5 t OFF 2.5 3 3.5 4 5 (OLTS) Figure 4. t ON and t OFF versus 55 4 85 Temperature ( C) Figure 5. t ON and t OFF versus Temp 3. Q (pc) 2.5 2..5..5 = 5 = 3 LEAKAGE (na).. I COM(ON) I COM(OFF) = 5..5 2 3 4 5 COM (). 55 I NO(OFF) 2 7 85 TEMPERATURE ( C) Figure 6. Charge Injection versus COM oltage Figure 7. Switch Leakage versus Temperature 7
NLAST45. F EE 3 OUT 35 pf 5% 5% 9% Address Select Pin EE % t trans t trans Figure 8. Channel Selection Propagation Delay. F DUT 3 OUT 35 pf GND 9% t BMM 9% of OH Address Select Pin GND Figure 9. t BBM (Time Break Before Make) DUT 5% 5%. F Open 3 OUT 35 pf OH 9% 9% Enable GND t ON t OFF Figure 2. t ON /t OFF 8
NLAST45 DUT 3 5% 5% Open 35 pf OUT CC Enable OL t OFF % t ON % Figure 2. t ON /t OFF Reference DUT 5 5 Generator Transmitted 5 Channel switch Address and Inhibit/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. ISO, Bandwidth and ONL are independent of the input signal direction. ISO = Off Channel Isolation = 2 Log OUT IN for IN at khz ONL = On Channel Loss = 2 Log OUT IN Bandwidth (BW) = the frequency 3 db below ONL for IN at khz to 5 MHz Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/ ONL 9
NLAST45 DUT Open IN GND C L IN Off On Off OUT Figure 23. Charge Injection: (Q) TYPICAL OPERATION +5. 6 6 +3. EE GND 7 8 EE GND 3. 7 8 Figure 24. 5. olts Single Supply = 5., EE = Figure. Dual Supply = 3., EE = 3. ORDERING INFORMATION Device Package Shipping NLAST45DR2 SOIC 6 48 Units / Rail NLAST45DT TSSOP 6* 96 Units / Rail NLAST45DTR2 TSSOP 6* Tape & Reel NLAST45DTR2G TSSOP 6* Tape & Reel NLAST45QSR SOEIAJ 6 2 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *This package is inherently Pb Free.
NLAST45 PACKAGE DIMENSIONS SOIC 6 D SUFFIX CASE 75B 5 ISSUE J A 6 9 8 B P 8 PL. (.) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D 6 PL. (.) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.8..386.393 B 3.8 4..5.57 C.35.75.54.68 D.35.49.4.9 F.4..6.49 G.27 BSC.5 BSC J.9..8.9 K...4.9 M 7 7 P 5.8 6.2.229.244 R..5..9 TSSOP 6 DT SUFFIX CASE 948F ISSUE A.5 (.6) T.5 (.6) T. (.4) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C 6X K REF. (.4) M T U S S 6 9 8 A G B U N H N J J F DETAIL E DETAIL E K K ÇÇÇ ÉÉ SECTION N N. (.) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED.5 (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED. (.) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.9 5..93.2 B 4.3.69.77 C.2.47 D.5.5.2.6 F.5.75.2.3 G.65 BSC.26 BSC H.8.28.7. J.9.2.4.8 J.9.6.4.6 K.9.3.7.2 K.9..7. L 6.4 BSC.2 BSC M 8 8
NLAST45 PACKAGE DIMENSIONS QSOP 6 QS SUFFIX CASE 492 ISSUE O L B. (.) M T C A G R U K P Q H x 45 RAD..3 X.5 DP. MAX RAD..5. TYP DETAIL E MOLD PIN MARK N 8 PL NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAITY I.D. INCHES MILLIMETERS DIM MIN MAX MIN MAX A.89.96 4.8 4.98 B.5.57 3.8 3.99 C.6.68.55.73 D.8.2.2.3 F.6.35.4.89 G. BSC.64 BSC H.8.8.2.46 J.98.75.249.9 K.4... L.23.244 5.84 6.2 M 8 8 N 7 7 P.7..8.28 Q.2 DIA.5 DIA R..35.64.89 U..35.64.89 8 8 D 6 PL. (.) M T B S A S T SEATING PLANE M J F DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, Arizona 8582 32 USA Phone: 48 829 77 or 8 344 386 Toll Free USA/Canada Fax: 48 829 779 or 8 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8 282 9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan 53 5 Phone: 8 3 5773 385 2 ON Semiconductor Website: Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NLAST45/D