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Ultra Low-Power Sensor Node for Wireless Health Monitoring System T. Hui Teo, Gin Kooi Lim, Darwin Sutomo David, Kuo Hwi Tan, Pradeep Kumar Gopalakrishnan, Rajnder Singh Institute of Microelectronics Singapore teehui@ime.a-star.edu.sg Abstract Ultra low power sensor node for wireless health monitoring system was designed and implemented in 0.18-µm CMOS. The sensor node functions as an interface circuit to both sensor and RF transceiver. The sensor node consists of an amplifier, an ADC (analog-to-digital converter) as well as digital system. The digital system is embedded with DSP (digital signal processing) for heart rate processing and RF interface for transceiver. The sensor node draws a total current of 7.5-µA from a 0.9-V single supply. The decoding scheme in the RF transceiver can tolerate up to ±22% clock frequency variation. I. INTRODUCTION Providing basic health monitoring services has became a necessity as the population grows older and more elderly people are living alone. It is important to develop sensor nodes which are the most critical components of a health monitoring system as shown in Figure 1. Body signal is extracted by the sensor node and transmit to the personal server. Health information of a person can be monitored thru the health care network. Many sensor nodes can share the same personal server. Thus, the sensor node should be at low cost and low power for wide adaptation. digitally in the sensor node before the results are transmitted to the rest of the system. This approach is different from monitoring a parameter and transmitting the entire data thru the wireless communication system, which is not power efficient since RF data transmission requires large power. The computation which is performed here is heart count. Cardiac application is selected due to the fact that CVD (cardio-vascular diseases) are the leading course of death in most of the countries, [1]. Information from cardiac, such as heart rate, heart rate/period variability, total heart count and etc. is important for CVD prevention, diagnostic, and treatment, [2]. Computation at sensor node, however, poses challenges in designing low power DSP and the sensor interface signal conditioning circuits. This paper is organized as follow. Section II describes the system and circuits design of the sensor node. It is followed by the measured results of the sensor node, in Section III. Conclusion and discussion are drawn in Section IV. Figure 2. Sensor node blocks diagram. Figure 1. Wireless health monitoring system. This work presents integrated circuits and system design for sensor node, including analog and digital blocks in creating a RF data link. To minimize the power consumption of the sensor node, some of the computations are performed II. SYSTEM, ARCHITECTURE AND CIRCUITS IMPLEMENTATION The sensor node is powered by a battery which should be smaller in size, such as Zinc-air battery. In this case, ultra low power is required. The best way of reducing the power consumption of a particular circuit is to operate the circuit at low voltage. The operating supply voltage is thus set at 0.9-V in this work. 1-4244-0921-7/07 $25.00 2007 IEEE. 2363
The block diagram of the sensor node is depicted in Figure 2. The sensor interface signal conditioning circuits consist of a low power amplifier and ADC. The amplifier increases the SNR (signal to noise ratio) of the signal provided by the external sensor. ADC converts the analog signal to digital signal to be processed by the DSP unit. The sensor node communicates with the transceiver thru the RF interface. A transceiver is required for receive and transmit data with personal server. Since only low data rate is to be transmitted, wireless standards such as, ZigBee can be used. However, only sensor node design is described in this paper. At 0.9-V, the ADC consumes 3.6-µA with 1-kHz clock frequency and 6-bit resolution. Figure 5. Offset compensated comparator. Figure 3. Amplifier. A. Amplifier The amplifier is required to drive large capacitive load at the input of the ADC. To ensure amplifier s stability and driving capability, 2-stage common source amplifier with fewest internal nodes is used. It operates in sub-threshold region to minimize the current consumption at low voltage supply. Closed-loop charge amplifier topology with MOS- Bipolar pseudo-resistor is then adopted to set the gain and bandwidth, [3-4]. The schematic of the amplifier is shown in Figure 3. This amplifier consumes 0.9-µA at 0.9-V, a close loop gain of 14-dB with achievable bandwidth of 4.5-kHz, while driving a load capacitance of 80-pF. Figure 6. Programmable relaxation oscillator. C. Oscillator and Current Reference One of the challenges in this sensor node design is to have self-generated reference clock since no accurate external clock is available. In this case, all the circuitries in the sensor node have to tolerant to large clock frequency variation. However, clock with approximately 50% duty cycle is required. Thus, programmable relaxation oscillator is used as the clock generator, Figure 6, [9]. The oscillation frequency is programmed through 2-bit control signal at the current source/sink. Simple single stage common source amplifiers are used as the comparators. At low supply voltage, the input transistors of the comparators are body biased to reduce their threshold voltages. The comparators are also operating in sub-threshold region. TABLE I MEASURED OSCILLATION FREQUENCY OF THE PROGRAMMABLE RELAXATION OSCILLATOR Figure 4. Charge redistribution SAR ADC. B. ADC SAR (successive approximation register) ADC was implemented to achieve minimum possible current consumption for analog to digital signal conversion, [5-8]. Charge re-distribution SAR ADC which utilizes only capacitor array and single comparator is adopted for medium resolution and low convention rate. Figure 4 shows the SAR ADC block diagram. Offset compensated comparator is used in this ADC as shown in Figure 5, two cascaded preamplifiers are used to minimize the offset. Control bits Oscillation frequency 00 1.98-MHz 01 1.65-MHz 10 1.25-MHz 11 0.86-MHz On-chip current reference is also included to provide biasing current to all the active circuits. The measured current consumption of the oscillators and the current reference are 1.0-µA and 0.5-µA respectively. The measured oscillation frequency is summarized in TABLE I, which shows approximately 0.40-MHz programmability per bit. 2364
D. Digital System The digital system contains digital base-band, DSP, and system control. The digital base-band performs CRC generation and encoding/decoding of the transmission data. CRC-8 polynomial x 8 +x 2 +x+1, is used in implementing the CRC checks, [10]. Manchester data format is used as a form of the transmission of the data. Since logic high in Manchester is presented as transition from low to high and logic low is presented as transition from high to low, the encoding of the data can simply be done using a XOR gate. On the other hand, XOR gate can also be used as a Manchester decoder. However, due to large variation in clock frequency used in the system, a divided-by-six Johnson counter is implemented in the decoding scheme to tolerate the clock frequency variation up to ±25%. temperatures (-40 o C, 25 o C, 85 o C), which is approximately ±22% variation. TABLE II CURRENT DISTRIBUTION OF CIRCUIT BLOCKS IN SENSOR NODE AT 0.9-V Blocks Current Core Area Amplifier 0.9-µA 150-µm 300-µm ADC 3.6-µA 600-µm 600-µm Current Reference 0.5-µA 140-µm 250-µm Programmable Oscillator 1.1-µA 90-µm 70-µm Digital System 1.0-µA 320-µm 320-µm III. MEASURED RESULTS The sensor node is implemented in 0.18-µm CMOS technology. Normal operation supply voltage of this technology is 1.8-V. However, the whole sensor node is operating at 0.9-V including both analog and digital blocks. The current consumption as well as active area for various blocks in the sensor node is summarized in TABLE II. The sensor node consumes approximately 7.5-µA when it is used to measure the heart rate. Measurement was carried out human samples for sensor node functionality and performance validation. Figure 7. Architecture of heart rate counter. A power efficient adaptive threshold peak detecting scheme was developed in calculation of the heart rate. A reference level is first detected and the following signal amplitude above reference level and threshold is counted as on peak. The threshold is initially set at a predefined level. With respect to the first peak level, the threshold is then reset to 75% of the particular peak. This threshold value is refreshed according to every peak value, which is particularly an adaptive threshold. The detailed implementation of the heart rate counter is depicted in Figure 7. The main advantage of using this technique is that no analogue or digital filters are required. Thus the power consumption is minimized, since the digital filter implementation at these frequencies requires large number of taps. The whole digital system is designed using Verilog- HDL. At 0.9-V most digital cell has to be operated at subthreshold region. In this case, the synthesis process needs to consider only logic gate with minimum inputs and minimum current consumption. In other words, stringent power constraints are applied. The total current consumption of the whole digital system was measured to be 1.1-µA at 0.9-V during heart rate measurement. The decoding scheme can tolerate clock frequency variation from 700-kHz to 1.1-MHz at various supply voltages (0.9-V, 1.2-V, 1.4-V), and Figure 8. Sensor node evaluation setup. Figure 9. Snapshot of arterial pulse waveform at the output of the amplifier. The functionality validation of the sensor node chip is accomplished with the assistant of FPGA board which acts as a wired personal server. The test setup is illustrated in Figure 8, T X, R X represents encoded and decoding signals respectively. At normal operation, T X is heart count and R X is instructions from the server, such as start/stop count. In this work, the sensor node is used for real time heart count. Incorporate with personal server, heart rate, heart rate/period 2365
variability, and total heart count can also be measured. Direct transmission of the raw data is also possible by bypassing the DSP, this option is only enable when it is required. For heart count, it is measured on the arterial pulse wave which is depicted in Figure 9. This signal is measured at the output of the amplifier. Note that the peak-to-peak period is approximately 800mSec. The corresponding total heart count in 60-Sec from the DSP is 75, which is consistent with the counting on the pulse wave. Heart rate is obtained by averaging the total heart count. The integrated chip of the sensor node is depicted in Figure 10. The active die area of the sensor node is approximately 1000-µm 700-µm. Figure 10. Integrated sensor node microphotograph (Amp: amplifier, Ref: current reference). IV. CONCLUSION An ultra low power sensor node for heart rate sensor is designed and demonstrated in 0.18-µm CMOS. By operating both analog and digital blocks in sub-threshold region, the sensor node consumes 7.5-µA from 0.9-V supply voltage. This ultra low power characteristic makes the sensor node a suitable candidate for wireless health monitoring system. Heart rate counting was selected as a test vehicle for the sensor node application. ACKNOWLEDGMENT The authors would like to thank Li Qiang, Ade Putra, Liu Haiqi and Chew Song Lin for various technical discussions and consultancy on test setup. We would like to acknowledge the support from ICS support team. REFERENCES [1] http://www.who.int/dietphysicalactivity/publications/facts/cvd/en/ [2] R. Barbieri, E. C. Matten, and E. N. Brown, Instantaneous monitoring of heart rate variability, Proceedings of the 25 th Annual International Conference of the IEEE Engineering in Medicine and Biology Society 2003, vol. 1, pp. 204-207, September 2003. [3] G. K. Lim, and T. Hui Teo, A low-power low-voltage amplifier for heart rate sensor, Proceeding of 2006 IEEE Asia Pacific Conference on Circuits and Systems, pp. 503-506, December 2006. [4] R. R. Harrison, and C. Cameron, A low-power, low-noise CMOS amplifier for neural recording applications, IEEE Journal of Solid- State Circuits, vol. 38, no. 6, pp. 958-965, June 2003. [5] M. D. Scott, B. E. Boser, and K. S. J. Pister, An ultralow energy ADC for smart dust, IEEE Journal of Solid-State Csircuits, vol. 38, no.7, pp. 1123-1129, July 2003. [6] H. Mulyadi, T. Hui Teo, J. Anuj, and K. Hu, 1.2V subranging dynamic reference flash ADC in 0.18µm CMOS process, Symposium on Microelectronics 2006, September 2006. [7] K. Hu, T. Hui Teo, J. Anuj, and H. Mulyadi, A cyclic ADC with modified RSD-based digital correction, Symposium on Microelectronics 2006, September 2006. [8] J. Anuj, T. Hui Teo, K. Hu, and H. Mulyadi, Digital error correction for a pipelined ADC, Symposium on Microelectronics 2006, September 2006. [9] T. H. Teo, E. S. Khoo, and D. Uday, On-chip automatic frequency tuning circuit using relaxation oscillator, Proceedings of the 21 st IEEE NORCHIP Conference, pp. 200-203, November 2003. [10] P. Koopman, and T. Chakravarty, Cyclic Redundancy Code (CRC) polynomial selection for embedded networks, 2004 International Conference on Dependable System and Networks, pp. 145-154, June 2004. 2366