IEEE ICET 26 2 nd International Conference on Emerging Technologies Peshawar, Pakistan 3-4 November 26 Single Chip FPGA Based Realization of Arbitrary Waveform Generator using Rademacher and Walsh Functions Syed Manzoor Qasim and Shuja Ahmad Abbasi Department of Electrical Engineering, VLSI Research Lab King Saud University, Riyadh, Saudi Arabia 42 {smanzoor, abbasi}@ksu.edu.s Abstract: Arbitrary waveform generators (AWGs) are becoming increasingly important for test and measurement applications. This paper describes a new approach for generating arbitrary waveforms using FPGA and a set of Rademacher and Walsh Functions. Utilizing these orthogonal functions, any periodic waveform can be realized. Recent advancements in Field Programmable Gate Array (FPGA) technology have made waveform generation very easy and cost-effective. For demonstration purpose we used a custom defined arbitrary waveform that is a concatenation of trapezoidal, sinusoidal and triangular waveforms. Simulation results for the proposed AWG are presented. Topdown approach has been adopted to realize the waveform generator in Spartan-3 FPGA. The maimum clock frequency for this design is 24.944 MHz with a power consumption of 62 mw. Keywords: Arbitrary Waveform Generation, Field- Programmable Gate Array (FPGA), Rademacher, Walsh Functions, VHDL. INTRODUCTION The ability to generate arbitrary waveform is of importance for many commercial and military applications. By using arbitrary waveforms, engineers and scientists are able to generate unique waveform signals that are specific to their applications. Most often, arbitrary waveforms are designed to simulate real world signals. A number of techniques utilizing both analog and digital approaches are available for the generation of arbitrary waveforms. However, digital methods, based on high-level design methodology offer better fleibility at the cost of increased compleity. Orthogonal functions such as Rademacher and Walsh functions are a set of discrete valued functions [][5]. These functions and their transforms are important analytical tools for signal processing and have wide applications in digital communication, digital image processing, statistical analysis and waveform generation [3]. Since Walsh functions are binary related, they are easy to generate and control using relatively simple hardware and readily lend itself for real-time waveform generation ideal for the synthesis of different waveforms. With the recent advancement in Field Programmable Gate Array (FPGA) technology, it is now possible to realize high performance Arbitrary Waveform Generator (AWG) in a single chip. This will drastically reduce the system cost and thus avoid the dependency on eternal function generators to generate arbitrary waveforms. These waveforms can be easily generated on-chip. Being dynamically reconfigurable, the same FPGA can be used for different applications [6]. The objective of this paper is to realize a single-chip low cost approach for arbitrary waveform generation. To achieve this we used FPGA architecture for high-speed generation of arbitrary waveforms. In this paper, we have used a set of Rademacher and Walsh functions for the generation of digital arbitrary waveform in FPGA. The rest of the paper is organized as follows. Orthogonal functions such as Rademacher and Walsh functions are defined and the methods used for their generation are discussed in section 2. Section 3 gives a brief overview of the Spartan-3 FPGA architecture and the top-down design methodology adopted in this work is described in section 4. In section 5, techniques for the generation of arbitrary waveform using Rademacher-Walsh functions is described. Section 6 summarizes the FPGA implementation results and finally section 7 gives some concluding remarks. -4244-52-5/6/$2. 26 IEEE 25
2. GENERATION OF RADEMACHER AND WALSH FUNCTIONS The Rademacher functions constitute an incomplete and orthogonal set of periodic square waveforms of amplitude + and. Mathematically, k th order Rademacher function is defined by the relation [4] (k+, ) = sgn {sin (22 k )}, k = (),,2,... where (, ) = and, sgn (2), Fig. depicts the first four Rademacher functions. Fig.. First four Rademacher Functions The Rademacher functions are generated as follows [4]: Let (, ) be the function with the value for the entire interval of duration T = i.e., (, ) =. To obtain (, ), divide the interval (,) in half, and let the value of (, ) in the first half interval be + and in the second half of the interval. To obtain (2, ), divide each of the intervals (,/2) and (/2,) in half and let the value of the function in the first half of each interval be + and in the second half of the interval. The process is repeated until each interval is a single-pulse element. The same functions generated using MATLAB for the purpose of verification are shown in Fig.2. Fig. 2. First four Rademacher functions generated using MATLAB A simple digital counter circuit is used for the generation of Rademacher functions. The Walsh functions form a complete and orthogonal set of functions of rectangular waveforms taking only two amplitudes + and. We denote the Walsh function by n, defined on the interval [,) such that [5] and,, (3) N ni n, i,, ni, (4) i where the integer n is represented by [5] n N i 2 i ni (5) Fig. 3 shows the first eight continuous Walsh functions. All the eight functions take on the values {+,}. Every function starts with the value +. The same functions generated using MATLAB for verification purpose are shown in Fig.4. The Walsh functions can be generated by many methods [4]. One way to compute the Walsh functions are by using Rademacher functions. The Walsh functions are generated using products of the Rademacher functions. The Walsh functions are developed as products 26
- - - - - - - (, ) (, ) (2, ) (3, ) (4, ) (5, ) (6,) (7, ) Fig. 3. First eight continuous Walsh functions Fig. 4. MATLAB generated First Eight Walsh functions of the Rademacher functions, based on the gray code conversion of the Walsh function inde sequence. If we convert the ± amplitudes of the Walsh functions to a binary logic {,} representation with the conversions + and, then multiplication of Rademacher functions is equivalent to Eclusive-OR operation. 3. SPARTAN-3 FPGA ARCHITECTURE The Spartan-3 FPGA architecture consists of an array of Configurable Logic Blocks (CLBs), which are the basic elements that can be programmed to perform various logic functions. Each CLB is coupled with a programmable interconnect switch matri that connects the CLB to adjacent and nearby CLBs [6]. Each CLB contains four logic slices, where each logic slice usually consists of two fourinput Look Up Tables (LUTs), two configurable flip-flops, some mues, and other control logic. In addition to the CLBs and the switch matrices, the Spartan-3 FPGA have a number of higher level logic blocks such as block RAMs (BRAMs), 8-bit multipliers, digital clock managers (DCMs) and even CPUs [6]. 4. DESIGN FLOW An FPGA design flow is the process of turning an FPGA design into a correctly timed bitstream file used to program the FPGA. In order to realize any algorithm on an FPGA it must be programmed (configured) first. To achieve this, a design methodology is adopted. Usually, design entry is done using hardware description language (HDL) such as Very High Speed Integrated Circuit Hardware Description Language (VHDL) or Verilog. In this paper, the design entry is done in VHDL. The objective is to make the system description independent of the physical hardware such that it can be used on other FPGAs and even on Application Specific Integrated Circuits (ASICs). Once a design has been completed it is simulated to verify the correct operation. A netlist is generated from the design and is mapped onto the FPGA using synthesis, place and route and optimizing tools. Mapping produces a bit-stream file that is used to program the FPGA [7]. 5. GENERATION OF ARBITRARY WAVEFORM USING WALSH FUNCTIONS Generating arbitrary waveforms using Walsh functions consists of three stages: ) Generation of the Rademacher functions 2) Generation of the Walsh functions using Rademacher functions, and 3) Adjustment of the coefficients of each Walsh function. Generation of periodic arbitrary waveform involves weighted addition of different Walsh functions. The addition of more Walsh functions would produce a smoother approimation of a particular waveform, of course at the cost of more computational compleity. The functionality of the arbitrary waveform generator is written in VHDL and synthesized into a configuration file that is downloaded into the Spartan-3 FPGA [6]. This is done using 27
Xilin ISE 7.i software. By using a single, appropriately sized FPGA, digital arbitrary waveform as defined by f can be synthesized thus avoiding the use of any analog to digital converter and hence minimizing the area and cost of hardware. Since Walsh functions constitute a complete set, any arbitrary function f can be epressed as follows [2]: f A n, n n (6) where, A n are the coefficients of the epansion and can be obtained by [2] A n f n, d (7) The arbitrary waveform defined by (8) is shown in fig. 5. f = 4.8.25.6.25.25 4.8.8.25.375 sin(4 (.375).375.625 2.667 4.267.625.825 4.267 4.267.825 (8) The sity four epansion coefficients required for the generation of arbitrary waveform as defined by (8) are listed in Table. Some of the coefficients turn out to be zero. As shown in Table, approimations to the arbitrary waveform can be obtained by using 64 Walsh functions. For validation of results, MATLAB was used. Fairly smooth arbitrary waveform was obtained through MATLAB simulation as shown in Fig. 6. TABLE WALSH FUNCTION COEFFICIENTS Walsh coefficients (n = 64) A.459 A 23 -.669 A 46 -.23 A A 24 -.24 A 47 -.4 A 2 -.83 A 25.84 A 48 -.24 A 3 -.8 A 26.83 A 49 A 4.66 A 27.48 A 5 A 5 -.758 A 28 -.84 A 5.3 A 6.8 A 29.24 A 52 A 7.85 A 3 -.48 A 53.28 A 8 A 3 -.8 A 54 -.3 A 9 -.658 A 32 -.6 A 55 A -.48 A 33 -.59 A 56 A -.43 A 34 -.22 A 57.3 A 2.658 A 35 -.9 A 58.2 A 3 A 36.59 A 59 A 4 -.4 A 37 A 6 -.3 A 5 -.369 A 38 -.2 A 6 A 6 -.6 A 39 -.333 A 62 A 7 -.38 A 4 -.7 A 63.9 A 8 -.39 A 4.43 A 9 -.9 A 42.42 A 2.38 A 43.23 A 2 A 44 -.43 A 22 -.22 A 45.7 Fig. 5. Custom-defined arbitrary waveform Fig. 6. MATLAB generated arbitrary waveform 28
6. FPGA IMPLEMENTATION RESULTS Based on the given architecture, design and simulation of the AWG has been performed using VHDL. The design is synthesized and placed and routed into Xilin Spartan-3 FPGA (XC3S2-4ft256) using Xilin ISE 7.i [8]. The hardware resource utilization is reported for an XC3S2-4ft256 Spartan-3 FPGA device and the results are summarized in Table 2. Modelsim is used for both pre-synthesis and post-synthesis simulation. Fig. 7 represents the snapshot of simulation results of Rademacher functions (R R 6 ), Walsh functions (W W 63 ) and 6-bit digital arbitrary waveforms (P P 5 ). As shown in fig. 7, clk is the clock signal, reset is the reset signal. The estimated power consumption of the architecture was obtained with Xilin XPower software using a clock frequency of 24.944 MHz. 7. CONCLUSION A new technique for high-speed arbitrary waveform generation using FPGA and a set of Rademacher and Walsh functions has been presented. Rademacher and Walsh are Fig. 7. Snapshot of Simulation of Rademacher, Walsh and arbitrary waveform. 29
orthogonal functions widely used in engineering applications such as waveform generation. Xilin spartan-3 (XC3S2-4FT) FPGA chip is used. FPGA implementation results have been presented which shows that the proposed design is very compact utilizing just 7% of total FPGA slices, so there is a possibility of implementing more parallel processors on the same FPGA. TABLE 2 HARDWARE RESOURCE UTILIZATION FOR XC3S2 SPARTAN-3 FPGA Number of Slices 34 out of,92 7% Number 4 input LUTs 54 out of 3,84 4% Number of bonded IOBs 87 out of 73 5% Number of GCLKs out of 8 2% Maimum Frequency (After Place and Route) : 24.944 MHz Total estimated power consumption : 62 mw The proposed design being digital can be easily integrated as an IP Core for on-chip waveform generation. AWG works correctly as shown by the simulation results and validated by MATLAB. The chip was thoroughly tested after implementation. The maimum clock frequency obtained after place and route of the design is 24.944 MHz consuming only 62 mw of power. REFERENCES [] J. L. Walsh, A closed set of normal orthogonal functions, Amer. J. of Math, vol. 55, pp. 5-24, 923. [2] K. G. Beauchamp, Walsh functions and their applications, Academic Press: New York, 975. [3] H. F. Harmuth, Applications of Walsh functions in communications, IEEE Spectrum, vol.6, pp.82-9, Nov. 969. [4] J. S. Lee and L. E. Miller, CDMA Systems Engineering Handbook, Artech House: Boston, 998. [5] B. Golubov, A. Efimov and V. Skvortsov, Walsh series and transforms: Theory and applications, Kluwer Academic Publishers: Dordrecht 99. [6] T. Tuan, S. Kao, A. Rahman, S. Das, and S. Trimberger, A 9 nm low-power FPGA for batterypowered applications, in Proc. of 4 th ACM/SIGDA Int. Symp. on FPGAs, Feb. 26, pp. 3-. [7] J-P. Deschamps, G. J. A. Bioul, and G. D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded systems, John Wiley & Sons: New Jersey, 26. [8] ISE 7.i Manual, Xilin Inc, 25. http://www.ilin.com 2