Lecture 030 ECE4430 Review III (1/9/04) Page 0301 LECTURE 030 ECE 4430 REVIEW III (READING: GHLM Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught in ECE 4430 2.) Insure that the students of ECE 6412 are adequately prepared Outline Models for IntegratedCircuit Active Devices Bipolar, MOS, and BiCMOS IC Technology SingleTransistor and MultipleTransistor Amplifiers Transistor Current Sources and Active Loads
Lecture 030 ECE4430 Review III (1/9/04) Page 0302 SINGLETRANSISTOR AND MULTIPLETRANSISTOR AMPLIFIERS Characterization of Amplifiers Amplifiers will be characterized by the following properties: Largesignal voltage transfer characteristics (.DC) Largesignal voltage swing limitations (.DC and.tran) Smallsignal, frequency independent performance (.TF) Gain (.TF) Input resistance (.TF) Output resistance (.TF) Smallsignal, frequency response (.AC) Other properties (.TEMP,.FOUR, etc.) Noise (.NOISE) Power dissipation (.OP) Slew rate (.TRAN) Etc.
Lecture 030 ECE4430 Review III (1/9/04) Page 0303 Types of Single Transistor Amplifiers R C R C v IN R C v OUT v OUT v OUT v OUT v IN v IN R E v IN R E Common Emitter Common Base Common Collector Emitter Degeneration R D R D v IN R D v OUT v OUT v OUT vout v IN v IN v IN R S R S Common Source Common Gate Common Drain Source Degeneration Fig. 03001
Lecture 030 ECE4430 Review III (1/9/04) Page 0304 Signal Flow in Transistors It is important to recognize that ac signals can only flow into and out of certain transistor terminals. Illustration: C D 180 180 B 0 G 0 0 0 E S Fig. 03002 Rules: The collector or drain can never be an input terminal. The base or gate can never be an output terminal. In addition it is important to note polarity reversals on these signal paths. The basecollector or gatedrain path inverts. All other paths are noninverting. (This of course assumes that there are no reactive elements causing phase shifts)
Lecture 030 ECE4430 Review III (1/9/04) Page 0305 Common Emitter Amplifer LargeSignal: i C v OUT v IN R C v OUT R C V IN, I B v CE (sat) Forward Active Region Saturation Region Common Emitter 0 0 v CE 0 0 0.5V 1.0V v IN Fig. 03003 SmallSignal: = I C Vt and r o = V A IC R in i in i out R out B C v in r π v in ro R C v out E E Fig. 03004 R in = r π = β ο, R out = r or C v out r o R C, v in = r o R C r o R C and i out i in = β o r o r o R C (One should also consider the case of a source resistance, R S, in series with the input)
Lecture 030 ECE4430 Review III (1/9/04) Page 0306 Common Source Amplifier LargeSignal: v IN R D v OUT R D i D v DS = V GS V T V IN v OUT Cutoff Region Saturation Region Triode Region v OUT = v IN V T Fig. 03005 SmallSignal: 0 0 v DS 0 V T 0 V IN R in =, R in i in i out R out G D v in v in rds R D v out S S Fig. 030055 R out = r dsr D r ds R D, v out v in = r ds R D r ds R D and i out i in =
Lecture 030 ECE4430 Review III (1/9/04) Page 0307 Summary of Single BJT Transistor Amplifiers SmallSignal Common Common Common Collector Performance Emitter Base Input Resistance r π r π r (Medium) 1β o (Low) π (1β o )R E (High) Output Resistance r o r o (1β o ) r π R S (High) (Very high) 1β o (Very low) Voltage Gain R L R L 1 Current Gain β o α (1β o )
Lecture 030 ECE4430 Review III (1/9/04) Page 0308 Summary of Single MOSFET Transistor Amplifiers SmallSignal Performance Input Resistance Output Resistance Voltage Gain Common Source Common Gate r ds R D 1 r ds r ds R D r ds R D Common Drain r ds R D r ds R D r ds R D r ds R D R D 0.8 R S 1 R S Current Gain 1
Lecture 030 ECE4430 Review III (1/9/04) Page 0309 BJT Cascode Amplifer Circuit and smallsignal model: v in v a Q1 Q2 R L V Bias v out B1 C1 = E2 r o2 C2 r π1 r o1 v a v π2 v out 1 v π1 r π2 gm2 v π2 v in i in i out E1=B2 Fig. 03006 If β 1 β 2 and r o can be neglected, then: R in = r π1 R out β 2 r o2 (not including R L ) v out v in = v out v a v a v in = (g m2 R L ) r π2 o2 β o1 1β r π1 (2 R L ) (1) = 2 R L i out i in = α 2 β 1 The advantage of the cascode is that the gain of Q1 is 1 and therefore the Miller capacitor, C µ, is not translated to the baseemitter as a large capacitor. R L
Lecture 030 ECE4430 Review III (1/9/04) Page 03010 MOS Cascode Amplifier Circuit and smallsignal model: Smallsignal v in performance (assuming a load resistance in the drain of R L ): M1 M2 V Bias v out 2 v gs2 = 2 v 1 G1 D1=S2 D2=D3 r ds2 v in = v v gs1 1 v 1 R gs1 rds1 L S1=G2=G3 R in = Using nodal analysis, we can write, [g ds1 g ds2 2 ]v 1 g ds2 v out = 1 v in and [g ds2 2 ]v 1 (g ds2 G L )v out = 0 Solving for v out /v in yields, v out 1 (g ds2 2 ) v in = g ds1 g ds2 g ds1 G L g ds2 G L G L 2 1 G L = 1 R L Note that unlike the BJT cascode, the voltage gain, v 1 /v in is greater than 1. v 1 v in = 1 r ds2 R L r ds1 12 r ds2 r ds2r L r ds2 = 1 R L r ds2 (R L < r ds2 for the gain to be 1) The smallsignal output resistance is, r out = [r ds1 r ds2 2 r ds1 r ds2 ] R L R L, assuming that R L is small. v out Fig. 03007
Lecture 030 ECE4430 Review III (1/9/04) Page 03011 Transconductance Characteristic of the BJT Differential Amplifier Consider the following NPNBJT differential amplifier (sometimes called an emittercoupled pair): i C1 i C2 LargeSignal Analysis: Q1 Q2 1.) Input loop eq.: v v BE1 I1 v BE2 v I1 v BE1 v BE2 v I2 = v I1 v I2 v BE1 v BE2 I EE = v ID v BE1 v BE2 = 0 v I2 2.) Forwardactive region: i C1 v BE1 = V t ln I S1 and v BE2 = V t ln i C2 I S2 i C1 3.) If I S1 = I S2 then i C2 = exp v I1 v I2 V t = exp v ID Vt V EE Fig. 03008 4.) Nodal current equation at the emitters: (i E1 i E2 ) = I EE = α 1 F (i C1 i C2 ) α F I EE α F I EE 5.) Combining the above equations gives: i C1 = v ID and i C2 = v ID 1 exp V t 1 exp Vt
Lecture 030 ECE4430 Review III (1/9/04) Page 03012 Differential and Commonmode SmallSignal BJT Amplifier Performance The smallsignal performance of a differential amplifier can be separated into a differential mode and common mode analysis. This separation allows us to take advantage of the following simplifications. HalfCircuit Concept: R C RC v i1 R C V EE v od i c1 ic2 v o1 v o2 Q1 Q2 v be1 v be2 I EE V EE R EE RC Differential Mode Analysis vi2 Common Mode Analysis v od i c1 ic2 v o1 v o2 Q1 Q2 v id v be1 vid v be2 2 2 Fig. 03009 v ic R C V EE RC v od i c1 ic2 v o1 v o2 Q1 Q2 v be1 v be2 I EE I EE 2 2 2R EE 2R EE V EE V EE Note: The halfcircuit concept is valid as long as the resistance seen looking into each emitter is approximately the same. V EE v ic
Lecture 030 ECE4430 Review III (1/9/04) Page 03013 Transconductance Performance of the Differential Amplifier Consider the following nchannel differential amplifier: I Bias M4 v ID v G1 M1 i D1 i D2 M3 M2 v GS1 v GS2 I SS V Bulk v G2 Fig. 03010 Where should bulk be connected? Consider a pwell, CMOS technology, D1 G1 S1 S2 G2 D2 n n p n n n pwell nsubstrate Fig. 03011 1.) Bulks connected to the well: No modulation of V T but large common mode parasitic capacitance. 2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but modulation of V T. If the technology is nwell CMOS, the bulks must be connected to ground.
Lecture 030 ECE4430 Review III (1/9/04) Page 03014 Transconductance Performance of the Differential Amplifier Continued Defining equations (Assume that the MOSFETs are in saturation): v ID = v GS1 v GS2 = Solution: 2i D1 2i D2 β 1/2 β 1/2 and I SS = i D1 i D2 βv 2 ID I SS i D1 = I SS 2 I SS 2 β2 v 4 ID 4I 2 SS 1/2 which are valid for v ID < (2I SS /β)1/2. Illustration of the result: and βv 2 ID I SS i D2 = I SS 2 I SS 2 β2 v 4 ID 4I 2 SS 1/2 i D /I SS 1.0 0.8 0.6 i D1 2.0 1.414 0.4 0.2 0.0 i D2 1.414 2.0 v ID (I SS /ß)0.5 Fig. 03012
Lecture 030 ECE4430 Review III (1/9/04) Page 03015 Differential and Commonmode SmallSignal Performance The smallsignal performance of a differential amplifier can be separated into a differential mode and common mode analysis. This separation allows us to take advantage of the following simplifications. HalfCircuit Concept: R D RD v i1 R D V SS v od i d1 id2 v o1 v o2 M1 M2 v gs1 v gs2 I SS V SS R SS RD Differential Mode Analysis vi2 Common Mode Analysis v od i d1 id2 v o1 v o2 M1 M2 v id v gs1 vid v gs2 2 2 Fig. 03013 v ic R D V SS RD v od i d1 id2 v o1 v o2 M1 M2 v gs1 v gs2 I SS I SS 2 2 2R SS 2R SS V SS V SS Note: The halfcircuit concept is valid as long as the resistance seen looking into each source is approximately the same. V SS v ic
Lecture 030 ECE4430 Review III (1/9/04) Page 03016 Other Characteristics of the Differential Amplifier Commonmode rejection ratio Input commonmode range Slew rate BJT: ICMR: The maximum and minimum input common mode range is: v ic (max) = 0.5I EE R C v CE1 (sat)v BE1 v ic (min) = V EE v CE3 (sat)v BE1 SR: The differential amplifier has a slew rate limit of I EE /C eq where C eq is the capacitance seen to ground from either collector. MOSFET: ICMR: The maximum and minimum input common mode range is: v ic (max) = 0.5I SS R D V T1 v ic (min) = V SS v DS3 (sat)v GS1 SR: The differential amplifier has a slew rate limit of I SS /C eq where C eq is the equivalent capacitance seen from either of the drains to ground.
Lecture 030 ECE4430 Review III (1/9/04) Page 03017 TRANSISTOR CURRENT SOURCES AND ACTIVE LOADS Summary of Current Sinks and Sources Current Sink/Source r OUT V MIN Simple MOS Current Sink r ds = λι 1 D V DS (sat) = V ON Simple BJT Current Sink r o = V A ΙC V CE (sat) 0.2V Cascode MOS 2 r ds2 r ds1 V T 2V ON Cascode BJT β F r o 2V CE (sat) Minimum V MIN Cascode 2 r ds2 r ds1 2V ON Current Sink Regulated Cascode Current Sink r ds3 3 r ds2 4 (r ds4 r ds5 ) V T V ON Minimum V MIN Regulated Cascode Current Sink r ds3 3 r ds2 4 (r ds4 r ds5 ) V ON
Lecture 030 ECE4430 Review III (1/9/04) Page 03018 Summary of MOS Current Mirrors Current Mirror Accuracy Output Resistance Input Resistance Minimum Output Voltage Minimum Input Voltage Simple Poor r ds 1 V ON V T V ON Cascode Excellent r ds 2 Wide Output Swing Cascode Selfbiased Cascode Excellent r ds 2 2 V T 2V ON 2(V T V ON ) 1 2V ON V T V ON Excellent r ds 2 R 1 2V ON V T 2V ON Wilson Poor r ds 2 Regulated Cascode Good Excellent 2r ds 3 1 2 2(V T V ON ) V T 2V ON V T 2V ON (min. is 2V ON ) V T V ON (min. is V ON )
Lecture 030 ECE4430 Review III (1/9/04) Page 03019 Summary of BJT Current Mirrors Current Mirror Accuracy Output Resistance Input Resistance Minimum Output Voltage Minimum Input Voltage Simple Poor r o 1 V CE (sat) V BE Cascode Excellent β F r o 2 V CE (sat)v BE 2V BE Wide Output Swing Cascode Selfbiased Cascode Excellent β F r o 1 2V CE (sat) V BE Excellent β F r o R 1 2V CE (sat) V CE (sat)v BE Wilson Poor β F r o 2 Regulated Cascode Good Excellent β F r o 1 or less V CE (sat)v BE V CE (sat)v BE V CE (sat)* V CE (sat)* * One can design the regulated cascode so that effectively the minimum value of V MIN (out) is just V CE (sat).
Lecture 030 ECE4430 Review III (1/9/04) Page 03020 Active Load Amplifiers What is an active load amplifier? V T 2V ON V T V ON V EB V EB V EC (sat) MOS Loads BJT Loads I Bias IBias I Bias I Bias V T 2V ON V BE V CE (sat) V T V ON MOS Transconductors BJT Transconductors Fig. 03014 It is a combination of any of the above transconductors and loads to form an amplifier. (Remember that the above are only some of the examples of transconductors and loads.) V BE
Lecture 030 ECE4430 Review III (1/9/04) Page 03021 BJT Differential Amplifier with a Current Mirror Load Design Considerations: Constraints Specifications Q3 Power supply Smallsignal gain i C3 Technology Frequency response (C L ) i C1 Temperature ICMR Q1 Slew rate (C L ) v OS Power dissipation Relationships V Bias A v = 1 R out ω 3dB = 1/R out C L v IC (max) = V BE3 V CE1 (sat) V BE1 V CE1 (sat) v IC (min) = V EE V CE5 (sat) V BE1 SR = I EE /C L P diss = ( V EE ) All dc currents flowing from or to V EE 4.4V 5V Q5 I EE 5V Q4 Q2 ic4 ic2 Fig. 03015 C L v out
Lecture 030 ECE4430 Review III (1/9/04) Page 03022 CMOS Differential Amplifier with a Current Mirror Load Design Considerations: Constraints Specifications Power supply Smallsignal gain Technology Frequency response (C L ) Temperature ICMR Slew rate (C L ) Relationships A v = 1 R out ω 3dB = 1/R out C L Power dissipation V IC (max) = V SG3 V TN1 V IC (min) = V DS5 (sat) V GS1 = V DS5 (sat) V GS2 SR = I SS /C L vin M1 M2 P diss = ( V SS ) All dc currents flowing from or to V SS V Bias M3 V SS I 5 M5 M4 C L Fig. 03016 v out
Lecture 030 ECE4430 Review III (1/9/04) Page 03023 Summary of Active Load Amplifiers Active load amplifier consists of a transconductor and a load There are a large number of combinations of loads and transconductors possible. We have not considered the many cascoded possibilities and other configurations. The BJT amplifier generally has more gain and wider signal swing than the MOS amplifier The voltage gain of the MOS transconductor with a current source or current mirror load is inversely proportional to the square root of the bias current. The current mirror load differential amplifier is a widely used input stage The frequency response is generally determined by the dominant pole which is found at points in the circuit that are high impedance to ac ground and large capacitance The active load amplifier is the primary gain stage in operational amplifiers and other applications and will be a fundamental building block in more complex circuits Performance not considered include slew rate and noise
Lecture 030 ECE4430 Review III (1/9/04) Page 03024 SUMMARY Single and Multiple Transistor Amplifiers Characterization BJT: Common emitter, commonbase, commoncollector, general MOSFET: Common source, commongate, commondrain, general Cascode Amplifiers Differential Amplifiers Differential mode analysis (balance requirements) Halfcircuit concept Common mode analysis Halfcircuit concept Input common mode range and slew rate Transistor Current Sources and Current Mirrors Active Load Amplifiers Other Material not Included in this Review Voltage and Current References Bandgap Voltage Reference Simple twostage op amps