IN THIS paper, we present an innovative architecture for optimal

1264 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 3, JUNE 2006 New Signal Conditioning Architecture for Optimal A/D Conversion in Digital Spectroscopy Setups Angelo Geraci, Senior Member, IEEE, Roberto Abbiati, Emilio Gatti, Fellow, IEEE, and Giancarlo Ripamonti Abstract By exploiting some interesting properties of feedback loops including an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC), it is possible to perform filtering action on both signal and noise in a mixed digital-analog realm, similar to the well-known sigma-delta ADC. In particular, we present a signal conditioning architecture based on this loop, which optimizes the analog-to-digital conversion operation in a high-resolution digital spectrometer. Elimination of pile-up at the ADC input, which minimizes the probability of its saturation as well as minimization of alias effects are achieved with no significant hardware burden and no measurement resolution loss. The filtering action inherent in the loop is used to obtain pole-zero cancellation, to improve the input signal rate, to reduce the effects of quantization noise by pushing it out-of-band, and to enhance the linearity of the converter. The technique has been implemented and validated. Index Terms Analog digital conversion, digital analog conversion, digital circuits, digital spectroscopy, feedback circuits, infinite-impulse response (IIR) digital filters. I. INTRODUCTION IN THIS paper, we present an innovative architecture for optimal conditioning of the analog signal to be sampled in a digital spectroscopy processor. In particular, the aim of the work has been the design and the implementation of a procedure for feeding the analog-to-digital converter (ADC) device with a signal treated for achieving the maximum concomitant reduction of alias and converter saturation effects. Most advantages of digital processing can be exploited by means of customized weighting function shapes, which can be conveniently obtained by using an analog prefilter followed by an ADC and a digital filter [1]. A feasible architecture of such a mixed analog-digital setup for the energy measurement of detected pulses is shown in Fig. 1. Many of the most relevant features of a spectrometer are almost fixed once the analog prefilter and the ADC have been selected. From the converter side, the alias effect and the saturation of the input dynamic range [2] have been focused. It is evident that the minimization of the alias effect and of the probability of saturation are conflicting demands: the reduction of the alias requires band limiting the input pulses (i.e., broadening their temporal shape) while the saturation probability minimization Manuscript received November 23, 2005. Revised January 25, 2006. This work was supported in part by the Italian INFN and MIUR. A. Geraci, R. Abbiati, and G. Ripamonti are with the Department of Electronics, Politecnico di Milano, Milan, Italy and also with INFN Sezione di Milano, 20133 Milan, Italy (e-mail: geraci@elet.polimi.it; abbiati@elet.polimi.it; ripamont@elet.polimi.it). E. Gatti is with the Department of Electronics, Politecnico di Milano, Milano, 20133 Milan, Italy (e-mail: gatti @elet.polimi.it). Digital Object Identifier 10.1109/TNS.2006.872201 Fig. 1. Mixed analog-digital architecture for the processing of detected events. Fig. 2. Schematic of the proposed conversion architecture. The digital section contains the digital filter of the proposed technique and the processing architectures for information extracting. needs the lowest superposition of incoming pulses (i.e., shortening their temporal shape). In order to overcome the conflict of the classic solutions of compromise, e.g., [2], a proper conditioning architecture of the analog signal at the input of the ADC has been conceived, simulated and implemented (see Fig. 2). The fundamental signal path is a classic topology based on a loop with a forward A/D conversion and a feedback D/A conversion of the signal, as in the sigma-delta A/D conversion architecture or, e.g., in [3], [4], and [5]. The idea consists in tracking in advance the analog signal course in order not to exceed the input dynamic range of the ADC through a proper digital filter and a feedback loop (so reducing at most saturation risk and consequently allowing also a higher input signal rate) and in maintaining at the same time a strictly controlled spectral band of the signal to be sampled (so making negligible any alias effect). Moreover, a configurable digital filtering stage is introduced in the ring thus allowing a fully adaptive data treatment. II. PROPOSED IDEA The kernel of the proposed conversion architecture is therefore the feedback loop (see Fig. 2). In order to make the ring as fast as possible, the input analog signal has to be properly band limited. Moreover, the digital filter (Fig. 2) in the loop has to foresee the future samples, which subtracted from the analog input signal make the ADC input a sequence of delta-like pulses. For instance, if the analog signal has an all-poles shape, the digital filter implements an all-zero transfer function. In this way 0018-9499/$20.00 2006 IEEE

GERACI et al.: NEW SIGNAL CONDITIONING ARCHITECTURE FOR OPTIMAL A/D CONVERSION 1265 Fig. 3. Experimental setup [12] for testing the proposed conversion architecture. The proper relative values of the time constants and allow a correct operation of the feedback loop and the necessary antialias effect. The output of the ring feeds a digital processing unit (not shown in figure) for optimal event energy and/or occurrence time estimation. In the prototyped architecture, the gain G is set fixed by a fully differential amplifier. Of course, it is possible to group the digital filter B (z) and the digital processing unit into only one programmable device, e.g., a FPGA. the converter saturation probability is minimized through the deconvolution of the singularities from the analog input signal. This kind of architecture does not require analog pole-zero cancellation classic procedures, as the pile-up is a priori avoided, and it is possible to use a very simple single pole analog cell for antialias purposes. For the experimental validation of the proposed technique, the setup shown in Fig. 3 has been realized. The preamplifier output is fed to the analog section of the processor that is a simple single pole antialias cell [6]. The quasi-exponential pulse seen at the analog output enters the ring of the sampling stage. The sampled data stream feeds the digital stage, which is made of a field programmable gate array (FPGA) working as processor. Let us analyze the ring operation (see Fig. 4). The digital transfer function to be synthesized in order to deconvolve the two analog poles is where is the sampling period, and are, respectively, the antialias filter and preamplifier time constants, is a gain factor, is the transfer function of the forward path, and the transfer function of the feedback path. The design of the digital filter consists in computing the digital transfer functions and. Without loss of generality but just for implementation convenience, we set equal to the constant gain (see (1) Fig. 4. Analog and digital transfer functions of the signal conditioning architecture. Fig. 3). Taking into account that the filter has an intrinsic latency because its output occurs one sampling period after the input, the digital filter results in the following: i.e., (please see equation (3) at the bottom of the page). It should be noted that the gain in the forward path is placed before the ADC in order to use the full converter input range also in presence of low amplitude input pulses. The experimental plots in Fig. 5 show the shapes of the signals along the ring, i.e., the signal at the input of the antialias filter, the signal at the input of the ADC (corresponding to a fixed value of the gain ) and the digital signal at the output of the conversion ring. Because of the presence of the negative feedback, the stability of the loop has been investigated and verified. It is well known that the digital poles of the closed loop transfer function must be inside the unit circle in the -plane to grant the stability of a causal system. The ideal closed loop transfer function has no poles but two zeros [see (1)] that corresponds to know exactly the value of the gain. As the gain value is measured and estimated, an estimation error influence on the stability has been investigated. In the presence of an estimation error, the closed loop transfer function becomes (please see equation (4) at the bottom of the page). whose poles are (please see equation (2) (3) (4)

1266 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 3, JUNE 2006 range (6) For actual values of time constants and sampling period, the condition results are not demanding at all, i.e., a tolerance of more than 50% of value can be tolerated in ordinary applications. I. Unknown Parameters Estimation In order to initialize the processor, the estimation of the unknown parameters,, has to be addressed. The most critical parameter is the gain, since it influences the stability of the system and, besides, a gain estimation error can result in the presence of unwanted poles in the closed loop transfer function. The architecture of the system allows disentangling the gain estimation from the pole time constant estimations. In fact, disconnecting the system input (see Fig. 3) only the digital-to-analog converter device (DAC) output enters the ADC after the multiplication. For instance, forcing a normalized ramp shaped signal at the DAC input, the slope of the corresponding ADC output is the sought value of that can be calculated, e.g., by means of a standard least mean squares (LMS) estimation [7] (7) Pole time constants can be estimated in different ways. The backstage theory of these procedures is widely addressed in literature. For instance, a way can be followed [8], [9] that determines the analog filter poles by using a subspace-based system state-space identification. The procedure is based on the singular value decomposition (SVD) of the generalized Hankel matrix that is obtained from the sampled pulse response of the whole analog section of the processor. This returns a matrix variable state-space representation of the system (8) Fig. 5. Experimental sequence of the proposed conversion process. (a) Analog signal at the input of the antialias filter. (b) Analog signal at the input of the ADC. (c)undersampled (see main text) deconvolved digital signal at the output of the conversion ring. The data source is an electronic signal generator that generates delta-like pulses. (5) at the bottom of the page). By imposing the stability condition, the gain estimation error has to be bound in the where the poles of the analog section are the eigenvalues of the matrix. Another way can be an algorithm that identifies the pole estimations by trimming the time constants values of zero singularities that compensate them. The iterative procedure operates on the analysis of the tail of the pulse response shape of the analog stage. Both procedures return time constant and values that are estimated with extremely high precisions. (5)

GERACI et al.: NEW SIGNAL CONDITIONING ARCHITECTURE FOR OPTIMAL A/D CONVERSION 1267 Fig. 7. Schematic diagram for timing representation of the processing ring. Fig. 6. Power spectrum of the quantization noise at the output of the proposed conversion ring. II. Quantization Noise Shaping It should be pointed out that the proposed technique also shapes the quantization noise of the ADC towards higher frequencies, as in sigma-delta converters [10]. This constitutes a sensitive quantization noise reduction in energy measurements where the processing filters have low pass frequency profile. In fact, assuming that the quantization error of the ADC can be modeled as a noise with white spectral density, the quantization noise spectrum at the output of the conversion ring results in i.e., (9) (10) which is plotted in Fig. 6 where the noise shaping towards high frequencies is evident. III. EXPERIMENTAL VALIDATION In order to dimension the prototype of the proposed converter scheme, system characteristic parameters have been set. In particular, a good signal range at the ADC input, a good antialias action and a correct loop operating frequency have to be guaranteed. For the ADC input range, the amplitude of the signal to be sampled is adjusted at best by the gain factor. The alias effect is minimized by the couple of poles and : e.g., if the preamplifier time constant is 50 s, a s analog filter time constant guarantees a very effective antialias performance. The sampling frequency is mainly determined by the characteristics of the A/D and D/A converters. It has to be considered that high-speed ADC architectures are pipelined, i.e., operate at high speed but the conversion data are available only at the end of the pipeline. As a fast ADC is needed in this appli- cation, conversion latency has to be taken into account. Let us define the number of pipeline stages and as the sampling period of the used ADC device and as the sampling period of the obtained global ADC architecture, i.e., the effective ring operating period. Referring to Fig. 7 and defining: the summing stage settling time ; the gain stage settling time ; the ADC device output data ready time ; the digital filter elaboration time ; the DAC output ready time, that is the sum of the DAC propagation delay plus the output settling time, the timing condition for the proper working of the proposed architecture is (11) The proposed technique has been implemented for experimental testing in a digital spectroscopy processor using for the A/D conversion the device AD9236, that is a 12 bit, 80 mega-samples-per-second (MSPS), 7 cycle pipelined converter, and for the D/A conversion the device AD768, a 16 bit, 30 MSPS converter (Fig. 8). The hardware realization has to grant a good signal range at the ADC input (through ), a good antialias response (through and ), and a correct loop operating frequency. With s, a totally negligible alias effect is obtained setting s. Considering the overall loop delays sum, i.e., the summing node settling time plus the pipelined ADC time response plus the digital filter processing time plus the D/A converter settling time, an effective operation frequency of the closed loop of 5 MHz is obtained. This means that the throughput of significant samples at the output of the ring (see Fig. 3) is 5 MSPS. As the output of the conversion ring is the output of the ADC running at 80 MSPS, the stream of digitized samples has to be properly undersampled by the following processing stage. For instance, Fig. 5 shows waveforms that are captured in different points of the ring of the prototype shown in Fig. 9. The digital infinite-impulse response (IIR) filter has been implemented in a customized direct form II (Fig. 10) [11] that takes less of 1% of the resources of a one million gate Xilinx Virtex-II FPGA device, which could be also devoted to the following processing of the digitized information. In the prototype, the FPGA manages the reception of the data from the ADC and feeds the DAC with the processed information. If there is need, in order to reduce the nonlinearities (integral INL and differential DNL) of the realized ADC, a dithering

1268 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 3, JUNE 2006 Fig. 8. High-level electric scheme prototyping the analog conditioning stage and the proposed conversion architecture, i.e., the "analog section" and the "A/D converter" of Fig. 1. In detail, the former is constituted by the G gain stage (based on U2-AD8138 device), by the single pole antialias filter (based on U1-AD8021 device) and by a current-voltage conversion stage (based on U3-AD8021 device). The latter implements the conversion architecture by means of a ADC (AD9236 device) and a DAC (AD768 device) that are connected according to Fig. 2. Precisely, the node summing the signal to be converted and the output of the DAC is realized by the G gain stage and the digital filter is implemented into a FPGA device (not shown in the scheme). Of course, ancillary networks of the implemented schematic are not shown. Fig. 9. Realized prototype of multichannel digital spectrometer with the presented conversion technique implemented.the vertical board is a single-channel digital processor implementing the proposed conversion architecture. The module is inserted in a configurable mother board that hosts up to eight single channels. (sometimes dynamically) the baseline at a comfortable level to avoid converter saturation. Instead, this paper shows that the presence of a feedback loop around the converter can be useful to gain advantages in both elimination of saturation occurrence of the ADC and minimization of alias effects with no significant hardware burden and no expected measurement resolution loss. Also, consequent considerable improvements in input signal rate and quantization noise weight reduction are obtained and enhancing of the linearity properties of the ADC can be achieved. The technique has been implemented and validated in a testing setup. The presence of an inherent delay in state-of-the-art converters, due to pipelining, limits the achievable bandwidth of the loop to the megahertz range. Nevertheless, this is more than enough to compensate the slow preamplifier pole without using analog pole-zero compensation networks. Fig. 10. Customized direct form II of the IIR filter B(z). effect that acts as a sliding scale stage [13], [14] can easily be added by implementing it into the configurable digital device. IV. CONCLUSION In standard digital spectrometers, the ADC is usually used open loop. Sometimes DACs are employed, but only to set REFERENCES [1] R. Abbiati, A. Geraci, and G. Ripamonti, Self-configuring digital processor for online pulse analysis, IEEE Trans. Nucl. Sci., vol. 51, no. 3, pp. 826 830, Jun. 2004. [2], A new filter concept yielding improved resolution and throughput in radiation detection systems, in Proc. IEEE Nucl. Sci. Symp., Rome, Italy, Oct. 16 22, 2004, pp. 277 280. [3] N. T. Thao, Analysis framework for the digital inversion of nonlinear deterministic characteristics in 61 modulation, in 1997 IEEE Int. Symp. Circuits Syst., Hong Kong, China, Jun. 9 12, 1997, pp. 405 408. [4] S. Saggini, M. Ghioni, and A. Geraci, A low-complexity high-performance digital control architecture for voltage regulator modules, in Power Electron. Specialists Conf. - PESC, Acapulco, Mexico, Jun. 15 19, 2003, pp. 121 126. [5] A. Pullia, S. Riboldi, G. M. Franchi, and F. Zocca, Active control of the baseline of digitized preamplifiers with sliding-scale correction, in Proc. IEEE Nucl. Sci. Symp., Rome, Italy, Oct. 16 22, 2004, pp. 1378 1381. [6] R. Abbiati, A. Geraci, and G. Ripamonti, Analog shaping optimization for digital processing of radiation detector signals, IEEE Trans. Nucl. Sci., vol. 52, no. 5, pt. 3, pp. 1638 1642, Oct. 2005.

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