Chapter 3: The CMOS verter This chapter is devoted to analyzg the static (DC) and dynamic (transient) behavior of the CMOS verter. The ma purpose of this analysis is to lay a theoretical ground for a dynamic itchg model from which the propagation delay between the output and put signals can be calculated. In the next chapter, this model will be extended to any CMOS logic gate, and not be restricted to verters only. In later sessions, these models will be used for estimatg the propagation delay along critical timg paths an tegrated circuit. A. Static properties The overall aim of this lecture is to derive a model for the verter voltage transfer characteristic (TC), i.e. for the output voltage response to a slowly creasg (quasi-static) put voltage. As a result of the lecture, we will have derived a model based on the square-law MOSFET model for calculatg the itchg voltage, i.e. the put voltage for which the output voltage of an verter flips from one state to the other (formal defition = ). The model can easily be extended for calculatg the itchg voltage of any logic gate by replacg the pull-up and pull-down networks by MOSFETs with an effective aspect ratio, W eff /L. Our approach for keepg track of whether the two MOSFETs of the verter are OFF or ON, lear or saturated, is to start by overlayg the two diagrams showg the MOSFET regions of operation. The pmosfet diagram is similar to that of the nmosfet, but it has its origo (, ) sce the source of the pmosfet is connected to and not to as for the nmosfet. By dog so, we obta five regions of verter operation as shown Fig. 3.1. In regions A and E, when one of the MOSFETs are OFF, the output node is pulled to the rail by the ON MOSFET. The itchg from high to low, or vice versa, occurs the green region, C, when both MOSFETs are saturated. I DSAT,P I DSAT,N Region C equivalent circuit Fig. 3.1. The CMOS verter and its voltage transfer curve (TC). OUT A: n subthreshold region Region B: nmos saturated pmos resistive E: p subthreshold region Region D: pmos saturated nmos resistive TN + TP By applyg Kirchhoff s current law (KCL) to the output node of the verter, we can derive the verter voltage transfer characteristic (TC) on the form of five different functions, =f( ). The most simple to derive and the most useful of these five functions, except for those regions A and E where, OUT DD IN TN SS DD TP IN DD, (3.1) 10
are those for region C, where both MOSFETs are saturated. From KCL we obta I DSAT,N =I DSAT,P, an expression from which the itchg voltage, SW = =, can be readily derived. The result is x 1 x DD TP TN, (3.2) where x=k N /k P. The complete TC is shown Fig. 3.1. Durg the lecture and the hands-on laboratory session, we will also defe and determe the high and low noise margs, NMH and NML. From the discussions of noise margs that we will have, we can conclude that CMOS is a robust technology. Exercises Exercise 3.1: Use the square-law MOSFET model and Kirchhoff s current law to derive equation (3.2)! Often verters are designed with x=1, but what is the effect on the TC if x is creased to, say x=4? Exercise 3.2: For three different put voltages, the output voltage of an verter is ept from to while measurg the two MOSFET currents, I DSN and I DSP. The current-voltage characteristics thus obtaed are shown below. Match the two MOSFET currents for each of the three verter put voltages, and fd the bias pots where the two currents are equal! Mark each of these three bias pots with B, C, or D, dependg on to which region of operation the vs graph that they belong. I DSP 1 2 3 I DSN Exercise 3.3: In the verter regions of operation diagram Fig. 3.1, we can add a secondary axis for the plottg the short-circuit current, I SC =m(i DSP, I DSN ). Plot the short-circuit current after havg identified the current-limitg MOSFET the different regions of operation. Exercise 3.4: *Derive the followg TC equations for the blue regions (regions B and D): 2 2 out, high DD b b x a 1 a a b x 2 2 out, low where a= TN and b= + TP. (3.3) Please, note, that with this nomenclature, the itchg voltage can be written on the form b 1 xa, x (3.4) Exercise 3.5: To account for voltage fluctuations, i.e. noise, the valid high and low output voltages are usually defed with certa ranges like 0 OL,max, and OH,m. Sce CMOS is a robust technology, the put voltage can vary with ranges larger than those defed for valid output voltages without causg valid output voltages, 0 IL,max, and IH,m. These regions 11
are usually defed from the two pots, ( OL,max, IH,m ) and ( OH,m, IL,max ), on the TC where the amplifications is equal to mus one, A v =-1. a) Derive expressions for the low and high noise margs, NML and NMH, as defed the graph usg the followg expressions for ( OL,max, IH,m ) and ( OH,m, IL,max )! DD TP TN DD TP TN OH,m DD OL,max 8 8,, (3.5) DD TP TN DD TP TN IL,max IH,m 8 8 b) What are the explicit noise marg values terms of fractions of if TN =- TP = /5? c) *Derive the expressions for ( OL,max, IH,m ) and ( OH,m, IL,max ) given above for a CMOS verter with k n =k p! ALID ONE OH,MIN OUTPUT OLTAGE [OUT] ALID ZERO OL,MAX OUTPUT OLTAGE [OUT] ALID ZERO OL,MAX NML IL,MAX IH,MIN NMH OH,MIN ALID ONE INPUT OLTAGE [IN] INPUT OLTAGE [IN] d) Derive expressions for the low and high noise margs, NML and NMH, as defed the graph usg the followg expressions for ( OL,max, IH,m ) and ( OH,m, IL,max )! DD TP TN DD TP TN OH,m DD OL,max 8 8,, (3.6) DD TP TN DD TP TN IL,max IH,m 8 8 e) What are the explicit noise marg values terms of fractions of if TN =- TP = /5? f) *Derive the expressions for ( OL,max, IH,m ) and ( OH,m, IL,max ) given above for a CMOS verter with k n =k p! Suggested laboratory exercise: Use the.dc analysis tool of the Spice circuit simulator to derive the TC for three different values of x! Use the slope marker tool to derive the noise margs from the pots on the TC where the ga is equal to -1! Fally, determe the voltage ga when =! B. Dynamic properties The overall aim of this second half of the verter chapter is to make a simple electrical model of the verter for rough estimations of its dynamic itchg behavior ( contrast to its static behavior 12
discussed the previous half). In particular, we are terested estimatg the propagation delay between the put and output signals due to the capacitances of the loadg gates. For simplicity, we will only consider verters where the two MOSFETs are sized for equal drivg capability. By dog so, we need not treat the delay of risg outputs differently from the delay of fallg outputs. This is simple enough for back-of-the-envelope calculations prior to a more accurate computer-aided timg analysis performed by usg state-of-the-art electronic design automation (EDA) tools. Chargg and dischargg a load capacitor through a constant-current source, I ON, yield lear relationships time. Therefore, the step response propagation delay, i.e. the time it takes to reach the 50% level, /2, from either rail is given by t C L DD /2 0.5 R C. (3.7) I pd eff L ON However, a real circuit the put signal, beg the output from a previous gate, is better approximated by a lear ramp, see Fig. 3.2. Experience and many simulations have shown that the propagation delay for this situation is about 40% longer, i.e. t 0.7R C. (3.8) pd eff L Fig. 3.2. CMOS verter put signal and output response approximated by ramps. This delay model yields the same delay as the delay when chargg or dischargg a capacitor, C L, through a resistor, R eff. To obta a simple enough electrical model of the verter for calculatg its propagation delay given a certa load capacitance, C L, we will simply replace the MOSFET current source by its effective resistance. The step-by-step derivation of the electrical circuit modelg the verter output drivg capability is illustrated Fig. 3.3. C LOAD R eff,p C DP R eff,n C DN C L C LOAD Electrical verter driver model RC circuit model Fig. 3.3. The CMOS verter and the derivation of its output equivalent RC circuit. I R eff,n =R eff,p C L =C LOAD +C DN +C DP R eff + In a previous session, we have already learnt how to calculate the effective resistance of a MOSFET. In the case of an n-channel MOSFET deliverg a maximum current I ON =600 A/m at =1.2, we obta 13
R eff 2 kω μm DD I W μm, (3.9) ON N where W N is the channel width of the nmosfet. In the followg, we will always assume the pmosfet beg twice as wide as the nmosfet ), i.e. W P =2W N, to compensate for its herent lower drivg capability (due to a factor of two lower hole mobility). Sce the C LOAD most often is the put capacitance of another verter, it might be appropriate to recall the expression for the verter put capacitance 3 3.6 ff/ m C C C W W LC W LC W, (3.10) G GN GP N P ox N ox N for an L=60 nm MOSFET with C ox =20 ff/m 2. The parasitic output capacitance is similarly assumed to scale with the verter drivg capability if we assume C D =pc G. This discussion leads us to the important conclusion that the R eff C G product of an verter is constant, dependent of W N, or equivalently, dependent of the verter drivg capability. Hence, the propagation delay of an ideal verter without parasitics, loaded by an identical verter is given by 0.7R C 5 ps. (3.11) eff G This is true dependent of whether the verter is of size (with W N =200 nm) or of size X10 (with W N =1 m). This fact will significantly simplify our lives as designers, sce this is the only time throughout the course that we have to calculate the RC constant. All other delay calculations will be expressed as multiples or fractions of this fundamental RC constant. The value of 5 ps given above is for a 65 nm process, a value that an ideal world scales as L 2 / between process nodes, where aga L is the channel length, or, equivalently, the mimum feature size. The process of replacg the MOSFETs by their electrical models to obta the complete verter two-port model, and not only a model for its drivg capability, is illustrated Fig. 3.4. C GP R eff,p C DP + R eff + C G C D C GN R eff,n C DN Inverter schematic MOSFETs replaced by their electrical models Fig. 3.4. The CMOS verter and the derivation of its equivalent RC circuit. Now, let us consider the case where an verter, for example, is loaded by four identical verters, or the equivalent case where an verter is loaded by an X8 verter. In both cases, the fanout of the verter is equal to four, sce it is loaded by a capacitance four times its put capacitance. This delay is denoted the FO4 delay of the verter. See Fig. 3.5. In both cases, the FO4 delay can be calculated as follows: CD C L FO4 delay 5 ps p f 25 ps, (3.12) CG CG 14 Resultg electrical verter two port model
where the fanout f=c L /C G =4, and p is the relative delay due to the parasitic capacitance at the gate output, p=c D /C G =1. As we shall see durg the next lecture, the ratio between the loadg capacitance and the put capacitance is also called the electrical effort, h. But, for the case of an verter, its fanout and its electrical effort are the same, f=h. t d Driver verter Loadg verters Driver verter Fig. 3.5. Illustration of the fanout-of-4 (FO4) concept. t d X8 Loadg verter Now, what would be the propagation delay if the verter is loaded by three 2-put NAND gates, or by three 2-put NOR gates, both with a drivg capability, i.e. the same as that of the verter? To solve this problem, we have to go back to the schematics of the NAND and NOR gates, and size the gate MOSFETs so that all path resistances are equal to the effective resistance of the verter. This is a two-stage process. First, as discussed before, the reference p-channel MOSFETs should, by default, be twice as wide as the reference n-channel MOSFETs. Second, when two MOSFETs appear series, they must be sized for twice the reference width to reduce the effective path resistance to R eff, the effective resistance of a reference verter. The results of such sizg processes are shown for NAND2 and NOR2 gates Fig. 3.6. A 2 B 2 B 4 2 NOR2 Z A 4 B 2 Z 1 NAND2 A 2 A 1 B 1 Fig. 3.6. Sizg MOSFET widths for the same effective resistances. By simply countg the number of unit capacitances connected to the gate put these MOSFET schematics, we can draw the conclusion that the gate put capacitance of the NAND gate is 4 unis, or 4/3 times that of the verter, while the gate put capacitance of the NOR gate is five units, or 5/3 times the put capacitance of the verter. From this discussion, we obta the followg verter FO3 delays: 4 5 ps13 25 ps NAND load 3 FO3 delay=. (3.13) 5 5 ps13 30 ps NOR load 3 The conclusion of this discussion is that all CMOS logic gates, due to its herent more complex topology, have an put gate capacitance larger than that of an verter with the same drivg capability. Of course, logic gates like the NAND and NOR gates this example, can always be resized for the 15
same put capacitance as for the verter, but then their drivg capabilities will be only ¾ or 3/5 of the verter drivg capability, respectively. This is due to the fact that the RC products are constant also for logic gates. This will be discussed more detail the next chapter, where we will derive models for calculatg propagation delays when the driver is a logic gate and not an verter. Fally, I would like to pot out that the ramp response of an verter is not identical to the exponential curve form of the RC circuit. However, the two curve forms yield approximately the same delay at the 50% level as illustrated Fig. 3.7. Fig. 3.7. Inverter ramp response as compared to the exponential decay of an RC circuit. Exercises Exercise 3.6: Analyze the RC circuit and show that the time needed for the exponential decay of the voltage across the capacitor to 50% of the itial voltage,, is given by t d =RC. ln2! Exercise 3.7: What do we mean with an ideal verter concerng its parasitic output capacitance? Exercise 3.8: Calculate the propagation delay of an ideal verter drivg an identical verter! Assume the followg MOSFET data: n-channel MOSFETs can sk 500 A/m channel width at =1, and their put capacitances are 1.3 ff/m. The p-channel MOSFET is made twice as wide as the n-channel device to obta the same drivg capability. Exercise 3.9: Assume that we, for simplicity, troduce a modified effective resistance R =Rln2, how large would this resistance be [ mfor the MOSFET Exercise 3.3? How does the use of R modify our delay model? Exercise 3.10: The FO4 delay of the AMS 0.35 m CMOS process runng at 3.3 is 125 ps. What would be the FO4 delay of a 0.13 m CMOS process runng at =1.8 and of a 65 nm CMOS process runng at 1.2? Exercise 3.11: Four is sort of a magic number, if the number of loadg verters becomes much larger than four, it is often more efficient to sert an extra verter with a better drivg capability as a buffer between the origal verter and the capacitive load. a) What drivg capability should the serted buffer verter have to mimize the delay? b) For what number of loadg verters does the serted buffer shorten the propagation delay? c) How does the parasitic output capacitance fluence these critical numbers? 16
Exercise 3.12: For how big a capacitive load would the sertion of a non-vertg, two-verter buffer give the shortest propagation delay? Exercise 3.13: Determe the number of buffer verters needed to mimize the delay if the load capacitance is 1000 times larger than the verter put capacitance? What would be the optimum taperg factor? Exercise 3.14: As a preparation for the next chapter, determe the parasitic output capacitances of the two logic gates the figure above simply by countg the number of unit dra capacitances connected to the output. How large are these parasitic capacitances with respect to the 3C put capacitance of the reference verter? Suggested laboratory exercise: Use the.tran 1 analysis simulation tool of the Spice/Spectre simulator to derive the rise and fall FO4 delays of an verter that you have designed. Defe your put signal so that its rise and fall times are about equal to those expected for the output. Did simulations give the output rise and fall times that you expected? Did you fd them equal or different? Why or why not? Compare your results from the FO4 delay simulations with your pre-lab estimations usg our simple RC model. If you have the time, run the same simulations also for the FF and SS process corners. What are the deviations from the typical case? A fal task would be to check how, and if, the FO4 delay varies with the verter drivg capability by changg the channel widths. If the FO4 delay is different for verters of different drivg capabilities, how could that be explaed? 1 tran stands for transient, large-signal analysis suitable for digital circuits 17