CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI Design I; A. Milenkovic 2 VLSI Design I; A. Milenkovic 1
CMOS Inverter: Steady State Response V OL = V OH = V M = f(r n, R p ) R p = 1 = R n = = 9/11/26 VLSI Design I; A. Milenkovic 3 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in kω range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors 9/11/26 VLSI Design I; A. Milenkovic 4 VLSI Design I; A. Milenkovic 2
Short Channel I-V Plot (NMOS) I D (A) 2.5 2 1.5 1.5 X 1-4 V GS = 2.5V V GS = 2.V V GS = 1.5V V GS = 1.V Linear dependence.5 1 1.5 2 2.5 V DS (V) NMOS transistor,.25um, L d =.25um, W/L = 1.5, = 2.5V, V T =.4V 9/11/26 VLSI Design I; A. Milenkovic 5 Short Channel I-V Plot (PMOS) All polarities of all voltages and currents are reversed -2 V DS (V) -1 V GS = -1.V -.2 V GS = -1.5V V GS = -2.V -.4 -.6 I D (A) -.8 V GS = -2.5V -1 X 1-4 PMOS transistor,.25um, L d =.25um, W/L = 1.5, = 2.5V, V T = -.4V 9/11/26 VLSI Design I; A. Milenkovic 6 VLSI Design I; A. Milenkovic 3
nmos Operation Cutoff V gsn < Linear V gsn > V dsn < Saturated V gsn > V dsn > I dsp 9/11/26 VLSI Design I; A. Milenkovic 7 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn I dsp 9/11/26 VLSI Design I; A. Milenkovic 8 VLSI Design I; A. Milenkovic 4
nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = I dsp V dsn = 9/11/26 VLSI Design I; A. Milenkovic 9 nmos Operation Cutoff V gsn < V tn < V tn Linear V gsn > V tn > V tn V dsn < V gsn V tn < -V tn Saturated V gsn > V tn > V tn V dsn > V gsn V tn > -V tn V gsn = I dsp V dsn = 9/11/26 VLSI Design I; A. Milenkovic 1 VLSI Design I; A. Milenkovic 5
pmos Operation Cutoff V gsp > Linear V gsp < V dsp > Saturated V gsp < V dsp < I dsp 9/11/26 VLSI Design I; A. Milenkovic 11 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp I dsp 9/11/26 VLSI Design I; A. Milenkovic 12 VLSI Design I; A. Milenkovic 6
pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V gsp = - V tp < V dsp = - I dsp 9/11/26 VLSI Design I; A. Milenkovic 13 pmos Operation Cutoff V gsp > V tp > + V tp Linear V gsp < V tp < + V tp V dsp > V gsp V tp > -V tp Saturated V gsp < V tp < + V tp V dsp < V gsp V tp < -V tp V gsp = - V tp < V dsp = - I dsp 9/11/26 VLSI Design I; A. Milenkovic 14 VLSI Design I; A. Milenkovic 7
I-V Characteristics Make pmos is wider than nmos such that β n = β p V gsn5 V gsn4 V gsp1 V gsp2 - -V dsp V gsn3 V gsn2 V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5 9/11/26 VLSI Design I; A. Milenkovic 15 Current vs., 5, I dsp 1 4 2 3 3 4 2 1 9/11/26 VLSI Design I; A. Milenkovic 16 VLSI Design I; A. Milenkovic 8
Load Line Analysis =, I dsp 9/11/26 VLSI Design I; A. Milenkovic 17 Load Line Analysis =.2, I dsp 1 1 9/11/26 VLSI Design I; A. Milenkovic 18 VLSI Design I; A. Milenkovic 9
Load Line Analysis =.4, I dsp 2 2 9/11/26 VLSI Design I; A. Milenkovic 19 Load Line Analysis =.6, I dsp 3 3 9/11/26 VLSI Design I; A. Milenkovic 2 VLSI Design I; A. Milenkovic 1
Load Line Analysis =.8, I dsp 4 4 9/11/26 VLSI Design I; A. Milenkovic 21 Load Line Analysis = 5, I dsp 1 2 3 4 9/11/26 VLSI Design I; A. Milenkovic 22 VLSI Design I; A. Milenkovic 11
Load Line Summary 5, I dsp 1 4 2 3 3 4 2 1 9/11/26 VLSI Design I; A. Milenkovic 23 DC Transfer Curve Transcribe points onto vs. plot 5 A B 1 4 C 2 3 3 4 2 1 D E V tn /2 +V tp 9/11/26 VLSI Design I; A. Milenkovic 24 VLSI Design I; A. Milenkovic 12
CMOS Inverter Load Lines PMOS = V 2.5 2 X 1-4 NMOS = 2.5V I Dn (A) =.5V = 1.V 1.5 1 = 2V.5 = 1.5V = 2.V V = 1.5V in = 1V = 2.5V.5 1 1.5 2 2.5 (V) = 2.V = 1.5V =.5V = 1.V =.5V = V.25um, W/L n = 1.5, W/L p = 4.5, = 2.5V, V Tn =.4V, V Tp = -.4V 9/11/26 VLSI Design I; A. Milenkovic 25 CMOS Inverter VTC (V) 2.5 2 1.5 1.5.5 1 1.5 2 2.5 (V) 9/11/26 VLSI Design I; A. Milenkovic 26 VLSI Design I; A. Milenkovic 13
Operating Regions Revisit transistor operating regions Region A B C D E nmos pmos A B C D E V tn /2 +V tp 9/11/26 VLSI Design I; A. Milenkovic 27 CMOS Inverter VTC 2.5 2 NMOS off PMOS res NMOS sat PMOS res (V) 1.5 1 NMOS sat PMOS sat.5 NMOS res PMOS sat NMOS res PMOS off.5 1 1.5 2 2.5 (V) 9/11/26 VLSI Design I; A. Milenkovic 28 VLSI Design I; A. Milenkovic 14
Beta Ratio If β p / β n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter β p.1 β = n β p 1 β = n 2 1.5 9/11/26 VLSI Design I; A. Milenkovic 29 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H V IH V IL Input Characteristics Indeterminate Region Logical High Input Range Logical Low Output Range V OL NM L GND Logical Low Input Range 9/11/26 VLSI Design I; A. Milenkovic 3 VLSI Design I; A. Milenkovic 15
Logic Levels To maximize noise margins, select logic levels at β p /β n > 1 9/11/26 VLSI Design I; A. Milenkovic 31 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic Unity Gain Points Slope = -1 V OH β p /β n > 1 V OL V tn V IL V IH - V tp 9/11/26 VLSI Design I; A. Milenkovic 32 VLSI Design I; A. Milenkovic 16
CMOS Inverter: Switch Model of Dynamic Behavior R p C L R n C L = = 9/11/26 VLSI Design I; A. Milenkovic 33 CMOS Inverter: Switch Model of Dynamic Behavior R p C L R n C L = = Gate response time is determined by the time to charge C L through R p (discharge C L through R n ) 9/11/26 VLSI Design I; A. Milenkovic 34 VLSI Design I; A. Milenkovic 17
Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics 9/11/26 VLSI Design I; A. Milenkovic 35 Switching Threshold V M where = (both PMOS and NMOS in saturation since V DS = V GS ) V M r /(1 + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = /2 (to have comparable high and low noise margins), so want r 1 (W/L) p k n V DSATn (V M -V Tn -V DSATn /2) = (W/L) n k p V DSATp ( -V M +V Tp +V DSATp /2) 9/11/26 VLSI Design I; A. Milenkovic 36 VLSI Design I; A. Milenkovic 18
Switch Threshold Example In our generic.25 micron CMOS process, using the process parameters from slide L3.25, a = 2.5V, and a minimum size NMOS device ((W/L) n of 1.5) NMOS PMOS V T (V).43 -.4 γ(v.5 ).4 -.4 V DSAT (V).63-1 k (A/V 2 ) 115 x 1-6 -3 x 1-6 λ(v -1 ).6 -.1 (W/L) p (W/L) n = 9/11/26 VLSI Design I; A. Milenkovic 37 Switch Threshold Example In our generic.25 micron CMOS process, using the process parameters, a = 2.5V, and a minimum size NMOS device ((W/L) n of 1.5) NMOS PMOS V T (V).43 -.4 γ(v.5 ).4 -.4 V DSAT (V).63-1 k (A/V 2 ) 115 x 1-6 -3 x 1-6 λ(v -1 ).6 -.1 (W/L) p 115 x 1-6.63 (1.25.43.63/2) = x x = 3.5 (W/L) n -3 x 1-6 -1. (1.25.4 1./2) (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V 9/11/26 VLSI Design I; A. Milenkovic 38 VLSI Design I; A. Milenkovic 19
Simulated Inverter V M V M (V) 1.5 1.4 1.3 1.2 1.1 1.9.8.1 ~3.4 1 1 (W/L) p /(W/L) n Note: x-axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives V M s of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward GND 9/11/26 VLSI Design I; A. Milenkovic 39 Noise Margins Determining V IH and V IL 3 By definition, V IH and V IL are where d /d = -1 (= gain) V OH = 2 1 V OL = GND VIL V M A piece-wise linear approximation of VTC VIH NM H = -V IH NM L = V IL -GND Approximating: V IH = V M -V M /g V IL = V M + ( -V M )/g So high gain in the transition region is very desirable 9/11/26 VLSI Design I; A. Milenkovic 4 VLSI Design I; A. Milenkovic 2
(V) 2.5 2 1.5 1.5 CMOS Inverter VTC from Simulation.5 1 1.5 2 2.5 (V).25um, (W/L) p /(W/L) n = 3.4 (W/L) n = 1.5 (min size) = 2.5V V M 1.25V, g = -27.5 V IL = 1.2V, V IH = 1.3V NM L = NM H = 1.2 (actual values are V IL = 1.3V, V IH = 1.45V NM L = 1.3V & NM H = 1.5V) Output resistance low-output = 2.4kΩ high-output = 3.3kΩ 9/11/26 VLSI Design I; A. Milenkovic 41 Gain Determinates gain -1-12 -14-16 -18.5 1 1.5 2-2 -4-6 -8 Gain is a strong function of the slopes of the currents in the saturation region, for = V M (1+r) g ---------------------------------- (V M -V Tn -V DSATn /2)(λ n - λ p ) Determined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing). 9/11/26 VLSI Design I; A. Milenkovic 42 VLSI Design I; A. Milenkovic 21
Impact of Process Variation on VTC Curve (V) 2.5 2 1.5 1.5 Bad PMOS Good NMOS Good PMOS Bad NMOS Nominal.5 1 1.5 2 2.5 (V) process variations (mostly) cause a shift in the switching threshold 9/11/26 VLSI Design I; A. Milenkovic 43 Scaling the Supply Voltage 2.5.2 2.15 (V) 1.5 1.5.5 1 1.5 2 2.5 (V) Device threshold voltages are kept (virtually) constant (V).5.1.15.2 9/11/26 VLSI Design I; A. Milenkovic 44.1.5 Gain=-1 (V) Device threshold voltages are kept (virtually) constant VLSI Design I; A. Milenkovic 22