PD 976 Applications l Motion Control Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l Hard Switched and High Frequency Circuits Benefits l Low R DSON Reduces Losses l Low Gate Charge Improves the Switching Performance l Improved Diode Recovery Improves Switching & EMI Performance l 3V Gate Voltage Rating Improves Robustness l Fully Characterized Avalanche SOA G D HEXFET Power MOSFET V DSS 5V R DS(on) typ. 2m: max. 5.5m: 78A I D D S D G S TO247AC G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 78 c A I D @ T C = C Continuous Drain Current, V GS @ V 55 I DM Pulsed Drain Current d 33 P D @T C = 25 C Maximum Power Dissipation 3 W Linear Derating Factor 2. W/ C V GS GatetoSource Voltage ±3 V E AS (Thermally limited) Single Pulse Avalanche Energy e 2 mj Operating Junction and 55 to 75 C T STG Thermal Resistance Storage Temperature Range Soldering Temperature, for seconds 3 (.6mm from case) Mounting torque, 632 or M3 screw lbxin (.Nxm) Parameter Typ. Max. Units R θjc JunctiontoCase g.49 R θcs CasetoSink, Flat, Greased Surface.24 C/W R θja JunctiontoAmbient g 4 www.irf.com 6/23/6
Static @ = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS DraintoSource Breakdown Voltage 5 V V (BR)DSS / Breakdown Voltage Temp. Coefficient 5 mv/ C Reference to 25 C, I D = mad R DS(on) Static DraintoSource OnResistance 2 5.5 mω V GS = V, I D = 33A f V GS(th) Gate Threshold Voltage 3. 5. V V DS = V GS, I D = 25µA I DSS DraintoSource Leakage Current 2 µa V DS = 5V, V GS = V. ma V DS = 5V, V GS = V, = 25 C I GSS GatetoSource Forward Leakage na V GS = 2V GatetoSource Reverse Leakage V GS = 2V R G(int) Internal Gate Resistance.8 Ω Dynamic @ = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 3 S Q g Total Gate Charge 7 nc Q gs GatetoSource Charge 24 Q gd GatetoDrain ("Miller") Charge 2 t d(on) TurnOn Delay Time 8 ns t r Rise Time 6 t d(off) TurnOff Delay Time 25 t f Fall Time 35 C iss Input Capacitance 446 pf C oss Output Capacitance 39 C rss Reverse Transfer Capacitance 82 Conditions V GS = V, I D = 25µA Conditions V DS = 25V, V DS = 75V V GS = V f V DD = 75V R G = 2.5Ω V GS = V f V GS = V V DS = 25V ƒ =.MHz Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 78c A Conditions MOSFET symbol (Body Diode) showing the I SM Pulsed Source Current 33 A integral reverse G (Body Diode)d pn junction diode. V SD Diode Forward Voltage.3 V = 25 C, I S = 5A, V GS = V f t rr Reverse Recovery Time 89 3 ns Q rr Reverse Recovery Charge 3 45 nc V R = 28V, I RRM Reverse Recovery Current 6.5 A di/dt = A/µs f t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) D S Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by max, starting = 25 C, L =.7mH R G = 25Ω, I AS = 5A, V GS =V. Part not recommended for use above this value. Pulse width 4µs; duty cycle 2%. R θ is measured at approximately 9 C 2 www.irf.com
C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (Α) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) VGS TOP 5V V 8.V 7.V 6.5V 6.V 5.5V BOTTOM 5.V VGS TOP 5V V 8.V 7.V 6.5V 6.V 5.5V BOTTOM 5.V 5.V. 5.V 6µs PULSE WIDTH Tj = 25 C. V DS, DraintoSource Voltage (V) 6µs PULSE WIDTH Tj = 75 C. V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 3.5 3. V GS = V = 75 C 2.5 2. = 25 C.5 V DS = 25V 6µs PULSE WIDTH. 3. 4. 5. 6. 7. 8. 9. V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics..5 6 4 2 2 4 6 8 2 4 6 8, Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature 7 6 5 4 Ciss V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 2 6 2 V DS = 2V VDS= 75V VDS= 3V 3 Coss 8 2 Crss V DS, DraintoSource Voltage (V) 4 2 4 6 8 2 Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. DraintoSource Voltage Fig 6. Typical Gate Charge vs. GatetoSource Voltage www.irf.com 3
Energy (µj) E AS, Single Pulse Avalanche Energy (mj) I D, Drain Current (A) V (BR)DSS, DraintoSource Breakdown Voltage I D, DraintoSource Current (A) OPERATION IN THIS AREA LIMITED BY R DS (on) I SD, Reverse Drain Current (A). = 75 C = 25 C V GS = V.2.4.6.8..2.4. Tc = 25 C Tj = 75 C Single Pulse msec µsec msec DC V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage V DS, DraintoSource Voltage (V) Fig 8. Maximum Safe Operating Area 8 LIMITED BY PACKAGE 9 6 8 7 4 6 2 5 25 5 75 25 5 75 T C, Case Temperature ( C) 4 6 4 2 2 4 6 8 2 4 6 8, Junction Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig. DraintoSource Breakdown Voltage 5. 7 4. 6 5 I D TOP 3A 2A BOTTOM 5A 3. 4 2. 3 2.. 2 4 6 8 2 4 6 25 5 75 25 5 75 V DS, DraintoSource Voltage (V) Starting, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy Vs. DrainCurrent 4 www.irf.com
E AR, Avalanche Energy (mj) Avalanche Current (A) Thermal Response ( Z thjc ) D =.5..2...5.2. R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci= τi/ri τ C τ Ri ( C/W) τι (sec).76792.83.233645.75.79727.8326 SINGLE PULSE ( THERMAL RESPONSE ). E6 E5.... t, Rectangular Pulse Duration (sec) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig 3. Maximum Effective Transient Thermal Impedance, JunctiontoCase Duty Cycle = Single Pulse. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 5 C and Tstart =25 C (Single Pulse).5. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τ j = 25 C and Tstart = 5 C. 24 2 6 2 8 4..E6.E5.E4.E3.E2.E TOP Single Pulse BOTTOM % Duty Cycle 25 5 75 25 5 75 Starting, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature tav (sec) Fig 4. Typical Avalanche Current vs.pulsewidth Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5
Q RR (nc) I RRM (A) Q RR (nc) V GS(th), Gate threshold Voltage (V) I RRM (A) 6. 5. I D =.A I D =.ma I D = 25µA 4 3 4. 2 3. 2.. 75 5 25 25 5 75 25 5 75, Temperature ( C ) Fig 6. Threshold Voltage Vs. Temperature I F = 33A V R = 28V = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt (A / µs) Fig. 7 Typical Recovery Current vs. di f /dt 4 32 28 3 24 2 2 6 I F = 5A V R = 28V = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt (A / µs) Fig. 8 Typical Recovery Current vs. di f /dt 2 8 I F = 33A V R = 28V 4 = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt (A / µs) Fig. 9 Typical Stored Charge vs. di f /dt 32 28 24 2 6 2 8 I F = 5A V R = 28V 4 = 25 C = 25 C 2 3 4 5 6 7 8 9 di f / dt (A / µs) Fig. 2 Typical Stored Charge vs. di f /dt 6 www.irf.com
D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD ReApplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T I AS.Ω V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms L D V DS V DD V DS 9% D.U.T % V GS Pulse Width < µs Duty Factor <.% V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Vds Id Vgs K DUT L VCC Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform www.irf.com 7
TO247AC Package Outline Dimensions are shown in millimeters (inches) TO247AC package is not recommended for Surface Mount Application. TO247AC Part Marking Information EXAMPLE: THIS IS AN IRFPE3 WIT H AS S E MBLY LOT CODE 5657 ASSEMBLED ON WW 35, 2 IN THE ASSEMBLY LINE "H" Note: "P" in assembly line position indicates "LeadFree" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFPE3 35H 56 57 PART NUMBER DATE CODE YEAR = 2 WEEK 35 LINE H Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 25275 TAC Fax: (3) 252793 Visit us at www.irf.com for sales contact information. 6/6 8 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/