GaN based Power Devices Michael A. Briere ACOO Enterprises LLC Under contract to International Rectifier RPI CFES Conference January 25, 2013 1
Motivation : Potential Energy Savings Worldwide M.A. Briere S2K 2005 1 Quad BTU = 168 Million Barrels of crude oil Point of Load (20-1200 V power devices) Possible with 100 % adoption of (Point of Load): efficient lighting (20% electricity, 8% energy), IT PS (15% electricity, 6% energy), inverterized motors (50% electricity, 20% energy) and hybrid vehicles (20% energy). Energy Information Administration / International Energy Outlook 2004; Assumes Transportation energy savings of 60% and 25% electricity savings Savings at $ 40/barrel 2
What limits adoption rate of new power devices? First: If quality, reliability and robustness is not provided : THERE IS NO PRODUCT only a Science project NO MARKET SHARE The governing metric for market adoption is : performance / cost (P/C) For power electronic systems : P/C = efficiency*density/cost This translates for power semiconductor devices as: P/C = Conduction loss* Switching Loss / cost If P/C ratio to incumbant 1, NICHE MARKET, SAM < 2-5 % of TAM IF P/C ratio to incumbant > 2-3 x, widespread adoption, SAM > 80 % of TAM About $ 4 B between 20 and 40 V ( mostly electronic dc-dc power supply ) About $ 6 B between 400 and 900 V ( mostly inverters and motor drives) 3
Material Based Device Limitations Ron = Ldrift / (q*μdrift*ndrift) (+ Lch/(q*μch*Nch) +2 * ρcontact ) SJ limit Unipolar Si IGBT limit Si IGBT limit GaN HEMT μ > 2000 cm 2 /Vs Inversion MISFET μ <200 Bulk (vertical) μ < 500 4
Be careful of device leakage / BV criteria! Normally-off 5A/1100 V GaN on Silicon Device for High Voltage Application K.S. Boutros et.al. (HRL Labs) IEDM 2009 paper 7.5 5
Measured R onaa for Si, SiC, and GaN HEMTs Large ( Wg > 100 mm) power devices Measured data Ecrit : Si = 20 V/μm, GaN = 300 V/ μm Ref: N. Ikeda et.al. ISPSD 2008 p.289 6
Difference between GaN HEMTs and Si FETs Hetero-epitaxy (lower cost) : strain engineering No p-n junctions No intentional doping - 2D Electron gas spontaneously forms No native Insulated Gate buried channel not surface inversion Lateral device - Highest Fields in Passivating Insulating Layers Native device is Depletion Mode (normally on) S G Gate Dielectric D b 2D Electron Gas AlGaN Gate Metal GaN AlGaN GaN Transition Layers Silicon Substrate 2 DEG 7
Gold Free Contact Resistance- lower cost 8
Scalable III-N on Si Technology IR s GaNpowIR : Lower Cost Compositionally Graded III-N Transition Layer(s), eg. X > Y > Z IR s III-N epi IP portfolio (as of March 2012) 17 issued US patents (2000-2010) 10 issued outside US patents 8 published pending US patents 19 Unpublished US Apps 5 Licensed Patents/Pend. III-N Device Layers III-N Buffer Layer.. Al z Ga (1-z) N Al y Ga (1-y) N Al x Ga (1-x) N Nucleation and Intermediate layer(s) Silicon Based Substrate Copyright 2013. 2012. International Rectifier. All Rights Reserved. 9
Wafer Distortion maps 2 um epi - Reactor 4 6 (625 um) Warp < 20 um, Bow -7 +/- 10 um 8 (725 um) Warp < 40 um, Bow 12 +/- 10 um Copyright 2013. 2012. International Rectifier. All Rights Reserved. 10
HV Cascoded GaN switch: A powerful Circuit D Depletion mode GaN G S Enhancement mode Si Cascoded Switch Leverages > 30 years of reliable drive experience Normally Off operation Gate drive compatible with existing Silicon solutions: +/-10V, +/- 15V, etc. Vgs(th) set by low voltage Si FET: Select Vt (3 V vs SJ, 5 V vs. IGBT), high enough to avoid C*dV/dt induced turn on Anti-parallel diode included: much lower reverse recovery than Si switches Minimal compromise in GaN HEMT performance 11
600 V Switch Performance vs. Current Density Performance FOM (V-uJ, 25C) 1000 900 800 700 600 500 400 300 200 100 0 Best in class IGBT 0 0.5 1 1.5 2 2.5 Current Density (A/mm^2) Performance FOM: Vds(on) * (Eon + Eoff) IR GaN Prototypes 12 12
600 V Device Trr Performance Comparison GaN based device has 20x Lower Qrr compared to IGBT Copak and more than 200x less than Super Junction body diode GaN Qrr independent of temperature and current 13
600 V rated device R-Q comparison table (RT) Device type R*Qoss (Ω-nC) R*Qg(Ω-nC) R*Qrr(Ω-nC) Si SJ FET 4x 9x 224x GaN cascode switch 1x 1x 1x 14
600 V GaN vs Si SJ Switch in PFC Boost Vin = 150 V, Vout= 400 V, Iav = 1 A, Freq= 100kHz, 25 C 10 ns / div, 100 V/ div Turn on Switching Transient 160 mohmgan 199 mohm Si About 100 V/ns 15
GaN vs Superjunction in Resonant DC:DC 16
Class-D Audio THD comparison Si vs GaN Audio Precision A-A THD+N vs POWER 08/29/12 18:59:26 10 % 5 2 1 0.5 0.2 0.1 0.05 THD for GaN Devices is 10x better than for Si Silicon FET: IRF6645 0.02 0.01 0.005 0.002 GaN 0.001 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 200 W Sweep Trace Color Line Style Thick Data Axis Comment 1 1 Red Solid 3 Anlr.THD+N Ratio Left IRF6645 2 1 Green Solid 3 Anlr.THD+N Ratio Left 1921#2 THD, Liz 720kHz, Vbus=+/-35V 1921 vs IRF6645-THDvsPower_DBver2_, 08-29-2012.at2 17
Transfer Curve for large device (Wg=850mm, Lg=0.3µm) Ion/Ioff > 10 12 Gmax > 300 S Ig < 100 na Higher Gm and comparable Ion/Ioff to Silicon devices 18
Forward Biased SOA (Width=960mm) ( 30 V devices) Id(A) 400 350 300 250 200 150 100 50 0 0 10 20 30 40 50 Vds(V) Vg= 3V Vg= 2V Vg= 1V Vg=0V Vg=1V 40 us pulse SOA of the device is wide compared to application requirements and is virtually independent of temperature from 25 to 125 0 C 19
Large area ( AA =8 mm 2 ) 600 V rated cascoded device Current Capability Output, 25C 900 A/cm 2 90 80 70 15V 60 8V ID (A) 50 40 7.5V 30 7V 20 6.5V 10 0 0 2 4 6 8 10 12 V DS (V) 20
Large area ( AA =8 mm 2 ) 600 V rated cascoded device Current Capability Output, 150C 60 50 8V 40 7V ID (A) 30 6.5V 20 6V 10 5.5V 0 0 2 4 6 8 10 12 V DS (V) 21
Large area ( AA =8 mm 2 ) 600 V rated cascoded device Current Capability Transfer 100 ID (A) 10 1 150C 25C 0.1 0.01 0 1 2 3 4 5 6 7 8 9 10 V GS (V) 22
GaN cascode switch Blocking voltage 1E-5 Blocking V GS = 0V 8E-6 I drain I D /W G A (A/mm)/ mm 6E-6 4E-6 2E-6 25 C 150 C 0E+0 0 200 400 600 800 1000 V DS (V) GaN device shows leakage determined breakdown (not an avalanche breakdown) At V DS = 600V, the typical drain leakages of HV GaN cascodes at 25 o C: < 50 na/mm 150 o C: < 400 na/mm 23
Temperature Dependence of Rdson, GaN HEMT and Si SJ Normalized value vs temperature 3.5 Rdson / 25 o C Rdson 3.0 2.5 2.0 1.5 1.0 Si SJ GaN 0.5 0.0 0 50 100 150 200 Temperature ( o C) GaN cascode switch has about 33% lower increase in Rds(on) from room to hot (150 o C), when compared to Si SJ FET. 24
Dielectric Breakdown of 600 V rated device > 1000 V. Wg > 100 mm 25
Lack of charge screening dynamic Rdson S G Gate Dielectric D AlGaN GaN Transition Layers Silicon Substrate 2 DEG 26
600V GaN Device Stability - Improvements Ratio of Rds(on) post/rds(on) pre stress 2.5 2.0 1.5 1.0 2007 0 100 200 300 350 400 500 550 Voltage May 2010 August 2010 Nov 2010 27
No Evidence of Inverse Piezo-Electric Effect in GaNpowIR TM devices TEM Image ( No physical damage) from stress : HTRB ( Vd=26 V, Vg=-14 V at 150 C ) > 3000 Hours. HTRB ( Vd=26 V, Vg=-7V at 175 C) > 3000 hrs HTRB (Vd = 34 V, Vg=-22V at 150 C) > 600 hrs HTGB of -50 V for > 3000 hrs Foward conduction (I=200 ma/mm, Vd= 25 V) 28
> 9000 hrs/device on HTRB : 30 V discrete HEMTs 11814-1-HTRB IGSS @ -7.5V VGSS 80.0E-9 70.0E-9 IGSS in Amps 60.0E-9 50.0E-9 40.0E-9 30.0E-9 20.0E-9 Test Hours 29
IR 600 V GaNpowIR Gate Dielectric Reliability MTTF at 150 C and Vg = - 20 V : > 10 8 hours Vg = -50 V 30
600 V Cascode device room temperature reverse bias stability Vd= +480 V, Vg = -20 V 31
Early 600 V device long term stability not TD limited 1 na /mm Idrain in A/mm Vd Stress = 480 V, 150 C Stress Time in hours at 150 C Copyright 2013. 2012. International Rectifier. All Rights Reserved. 32
600 V Cascode device step stress at 650 V for > 72 hours 650 V stress >72 hours Wg > 100 mm Id-s < 10 na/mm 33
The Next Revolution in Power Electronics : Integration 34
Data Processing Vintage 1950-1960 s 8 bit relay from Univac How today s power electronics will look to future engineers in 15-20 years 35
Summary GaN Based Power Devices have the Potential to Provide 10-100 times Improvement in both conduction (Rdson) and switching (Qr) Performance compared to Si The lateral GaN based HEMT likely has a practical limit of about 1200 V. Significant effort will be required to bring this technology in line with the expectations for quality and reliability set by silicon incumbents The Inherent Integratability of Lateral GaN based Power Devices will Enable High Levels of Integration, Propelling Power Electronics Along a Revolutionary Tragectory akin to that in Data Processing in the 1970 s. As GaN based power devices are further developed a wide range of applications and markets will achieve significantly higher levels of density, efficiency and cost effectiveness It is essential to bring costs < 2x of silicon based alternatives to achieve wide-spread adoption of GaN based power device technology 36
Dedication I would like to dedicate this and all my work in the power semiconductor field to Eric Lidow Dec 1912 Jan 2013 Founder of International Rectifier And my Inspiration 37