Power MOSFET PRODUCT SUMMRY (V) 600 R DS(on) ( ) V GS = V 0. Q g (Max.) (nc) 330 Q gs (nc) 84 Q gd (nc) 50 Configuration Single D FETURES Low Gate Charge Q g Results in Simple Drive Requirement Improved Gate, valanche and Dynamic dv/dt Ruggedness vailable RoHS* COMPLINT Fully Characterized Capacitance and valanche Voltage and Current Enhanced Body Diode dv/dt Capability Compliant to RoHS Directive 2002/95/EC Super-247 S D G G S PPLICTIONS Hard Switching Primary or PFC Switch Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching N-Channel MOSFET Motor Drive ORDERING INFORMTION Package Lead (Pb)-free SnPb Super-247 IRFPS40N60KPbF SiHFPS40N60K-E3 IRFPS40N60K SiHFPS40N60K BSOLUTE MXIMUM RTINGS (T C = 25 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage 600 Gate-Source Voltage V GS ± 30 V Continuous Drain Current V GS at V T C = 25 C 40 I D T C = C 24 Pulsed Drain Current a I DM 60 Linear Derating Factor 4.5 W/ C Single Pulse valanche Energy b E S 600 mj Repetitive valanche Current a I R 40 Repetitive valanche Energy a E R 57 mj Maximum Power Dissipation T C = 25 C P D 570 W Peak Diode Recovery dv/dt c dv/dt 7.5 V/ns Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 Soldering Recommendations (Peak Temperature) for s 300 d C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Starting T J = 25 C, L = 0.84 mh, R g = 25, I S = 38, dv/dt = 5.5 V/ns (see fig. 2a). c. I SD 38, di/dt 50 /μs, V DD, T J 50 C. d..6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 926 S-02-Rev. B, 3-Jan-
THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 40 Case-to-Sink, Flat, Greased Surface R thcs 0.24 - C/W Maximum Junction-to-Case (Drain) R thjc - 0.22 SPECIFICTIONS (T J = 25 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V GS = 0 V, I D = 250 μ 600 - - V Temperature Coefficient /T J Reference to 25 C, I D = m - 0.63 - V/ C Gate-Source Threshold Voltage V GS(th) = V GS, I D = 250 μ 3.0-5.0 V Gate-Source Leakage I GSS V GS = ± 30 V - - ± n = 600 V, V GS = 0 V - - 50 Zero Gate Voltage Drain Current I DSS = 480 V, V GS = 0 V, T J = 25 C - - 250 μ Drain-Source On-State Resistance R DS(on) V GS = V I D = 24 b - 0. 0.30 Forward Transconductance g fs = 50 V, I D = 24 b 2 - - S Dynamic Input Capacitance C iss VGS = 0 V, - 7970 - Output Capacitance C oss = 25 V, - 750 - Reverse Transfer Capacitance C f =.0 MHz, see fig. 5 rss - 75 - pf =.0 V, f =.0 MHz - 9440 - Output Capacitance C oss V GS = 0 V = 480 V, f =.0 MHz - 200 - Effective Output Capacitance C oss eff. = 0 V to 480 V c - 260 - Total Gate Charge Q g - - 330 Gate-Source Charge Q gs I D = 38, = 480 V, see fig. 6 and 3 b - - 84 nc Gate-Drain Charge Q gd - - 50 Turn-On Delay Time t d(on) V GS = V - 47 - Rise Time t r V DD = 300 V, I D = 38, - - Turn-Off Delay Time t d(off) R G = 4.3, see fig. b - 97 - ns Fall Time t f - 60 - Drain-Source Body Diode Characteristics MOSFET symbol D Continuous Source-Drain Diode Current I S - - 40 showing the integral reverse G Pulsed Diode Forward Current a I SM p - n junction diode - - 60 S Body Diode Voltage V SD T J = 25 C, I S = 38, V GS = 0 V b - -.5 V T J = 25 C - 630 950 Body Diode Reverse Recovery Time t rr ns T J = 25 C I F = 38, di/dt = - 730 90 T J = 25 C /μs - 4 20 Body Diode Reverse Recovery Charge Q rr μc T J = 25 C - 7 25 Body Diode Recovery Current I RRM T J = 25 C - 39 58 Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 μs; duty cycle 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as C oss while is rising from 0 % to 80 %. Document Number: 926 2 S-02-Rev. B, 3-Jan-
I D, Drain-to-Source Current () I D, Drain-to-Source Current () TYPICL CHRCTERISTICS (25 C, unless otherwise noted) 0. 0.0 0.00 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20μs PULSE WIDTH Tj = 25 C 0., Drain-to-Source Voltage (V) Fig. - Typical Output Characteristics I D, Drain-to-Source Current () 0. T = 50 J C T = 25 J C = 50V 20μs PULSE WIDTH 0.0 4 6 8 3 5 V GS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics 0. VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20μs PULSE WIDTH Tj = 50 C 0., Drain-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.5 I D = 38 3.0 2.5 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 20 40 60 T J, Junction Temperature ( C) Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 926 S-02-Rev. B, 3-Jan- 3
I D, Drain-to-Source Current () 00 V GS = 0V, f = MHZ C = C C, C SHORTED iss gs gd ds C rss = C gd C oss = C ds C gd C, Capacitance(pF) 0 Ciss Coss Crss I SD, Reverse Drain Current () T J= 50 C T = 25 J C, Drain-to-Source Voltage (V) V GS= 0 V 0. 0.2 0.6 0.9.3.6 V SD,Source-to-Drain Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage 2 I D = 38 = 480V = 300V = 20V OPERTION IN THIS RE LIMITED BY R DS (on) V GS, Gate-to-Source Voltage (V) 7 5 2 0 0 50 50 200 250 Q G, Total Gate Charge (nc) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage 0. Tc = 25 C Tj = 50 C Single Pulse μsec msec msec 0, Drain-toSource Voltage (V) Fig. 8 - Maximum Safe Operating rea Document Number: 926 4 S-02-Rev. B, 3-Jan-
R D I D, Drain Current () 40 30 20 R G V GS V Pulse width µs Duty factor 0. % D.U.T. - V DD Fig. a - Switching Time Test Circuit 90 % 0 25 50 75 25 50 T, Case Temperature ( C C) % V GS t d(on) t r t d(off) t f Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. b - Switching Time Waveforms Thermal Response (Z thjc ) 0. 0.0 D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) P DM t t 2 Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc T C 0.00 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig. - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 926 S-02-Rev. B, 3-Jan- 5
V GS(th) Gate threshold Voltage (V) 5.0 5 V 4.5 L Driver 4.0 I D = 250μ 3.5 R G 20 V t p D.U.T. I S 0.0 Ω - V DD 3.0 2.5 Fig. 2a - Unclamped Inductive Test Circuit t p 2.0-75 -50-25 0 25 50 75 25 50 T J, Temperature ( C ) Fig. 2d - Threshold Voltage vs. Temperature V GS V Q G I S Q GS Q GD V G Fig. 2b - Unclamped Inductive Waveforms 200 I D Charge 960 TOP BOTTOM 7 24 38 Fig. 3a - Basic Gate Charge Waveform E S, Single Pulse valanche Energy (mj) 720 480 240 0 25 50 75 25 50 Starting Tj, Junction Temperature ( C) Fig. 2c - Maximum valanche Energy vs. Drain Current 2 V Current regulator Same type as D.U.T. 50 kω 0.2 µf 0.3 µf D.U.T. V GS 3 m V - DS Fig. 3b - Gate Charge Test Circuit I G I D Current sampling resistors Document Number: 926 6 S-02-Rev. B, 3-Jan-
Peak Diode Recovery dv/dt Test Circuit D.U.T. - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 4 - For N-Channel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?926. Document Number: 926 S-02-Rev. B, 3-Jan- 7
Package Information TO-274 (High Voltage) B E4 E R E D2 D D L L Detail e b C 2 0. (0.25) M B M 5 Lead Tip b2 Detail Scale: 2: b4 MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX. 4.70 5.30 0.85 0.209 D 5.50 6. 0.6 0.634.50 2.50 0.059 0.098 D2 0.70.30 0.028 0.05 2 2.25 2.65 0.089 0.4 E 5. 6. 0.594 0.634 b.30.60 0.05 0.063 E 3.30 3.90 0.524 0.547 b2.80 2.20 0.07 0.087 e 5.45 BSC 0.25 BSC b4 3.00 3.25 0.8 0.28 L 3.70 4.70 0.539 0.579 c () 0.38 0.89 0.05 0.035 L.00.60 0.039 0.063 D 9.80 20.80 0.780 0.89 R 2.00 3.00 0.079 0.8 ECN: X7-0056-Rev. B, 27-Mar-7 DWG: 5975 Notes Dimensioning and tolerancing per SME Y4.5M-994 Dimension D and E do not include mold flash. Mold flash shall not exceed 0.27 mm (0.005") per side. These dimensions are measured at the outer extremes of the plastic body Outline conforms to JEDEC outline to TO-274 () Dimension measured at tip of lead Revision: 27-Mar-7 Document Number: 9365 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T /doc?9
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