Power MOSFET PRODUCT SUMMARY V DS (V) 500 R DS(on) (Ω) V GS = V 0.26 Q g (Max.) (nc) 20 Q gs (nc) 34 Q gd (nc) 54 Configuration Single D TO220 G G DS S NChannel MOSFET ORDERING INFORMATION Package Lead (Pb)free SnPb FEATURES Low Gate Charge Q g Results in Simple Drive Requirement Improved Gate, Avalanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche Voltage and Current Low R DS(on) Lead (Pb)free Available APPLICATIONS Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits TO220 IRFB8N50KPbF SiHFB8N50KE3 IRFB8N50K SiHFB8N50K Available RoHS* COMPLIANT ABSOLUTE MAXIMUM RATINGS T C = 25 C, unless otherwise noted PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage V DS 500 GateSource Voltage V GS ± 30 V Continuous Drain Current V GS at V T C = 25 C 7 I D T C = C A Pulsed Drain Current a I DM 68 Linear Derating Factor.8 W/ C Single Pulse Avalanche Energy b E AS 370 mj Repetitive Avalanche Current a I AR 7 A Repetitive Avalanche Energy a E AR 22 mj Maximum Power Dissipation T C = 25 C P D 220 W Peak Diode Recovery dv/dt c dv/dt 7.8 V/ns Operating Junction and Storage Temperature Range T J, T stg 55 to 50 Soldering Recommendations (Peak Temperature) for s 300 d C Mounting Torque 632 or M3 screw N Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. Starting T J = 25 C, L = 2.5 mh, R G = 25 Ω, I AS = 7 A. c. I SD 7 A, di/dt 376 A/µs, V DD V DS, T J 50 C. d..6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 9 S09005Rev. A, 9Jan09
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient a R thja 58 CasetoSink, Flat, Greased Surface R thcs 0.50 C/W Maximum JunctiontoCase (Drain) a R thjc 0.56 Note a. R th is measured at T J approximately 90 C. SPECIFICATIONS T J = 25 C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage V DS V GS = 0 V, I D = 250 µa 500 V V DS Temperature Coefficient ΔV DS /T J Reference to 25 C, I D = ma 0.59 V/ C GateSource Threshold Voltage V GS(th) V DS = V GS, I D = 250 µa 3.0 5.0 V GateSource Leakage I GSS V GS = ± 30 V ± na V DS = 500 V, V GS = 0 V 50 Zero Gate Voltage Drain Current I DSS V DS = 400 V, V GS = 0 V, T J = 25 C 250 µa DrainSource OnState Resistance R DS(on) V GS = V I D = A b 0.26 0.29 Ω Forward Transconductance g fs V DS = 50 V, I D = A 6.4 S Dynamic Input Capacitance C iss V GS = 0 V, 2830 Output Capacitance C oss V DS = 25 V, 330 f =.0 MHz, see fig. 5 Reverse Transfer Capacitance C rss 38 pf V DS =.0 V, f =.0 MHz 33 Output Capacitance C oss V GS = 0 V V DS = 400 V, f =.0 MHz 93 Effective Output Capacitance C oss eff. V DS = 0 V to 400 V c 55 Total Gate Charge Q g 20 GateSource Charge Q gs I D = 7 A, V DS = 400 V, see fig. 6 and 3 b 34 nc GateDrain Charge Q gd 54 TurnOn Delay Time t d(on) V GS = V 22 Rise Time t r V DD = 250 V, I D = 7 A, 60 TurnOff Delay Time t d(off) R G = 7.5 Ω, see fig. b 45 ns Fall Time t f 30 DrainSource Body Diode Characteristics MOSFET symbol D Continuous SourceDrain Diode Current I S 7 showing the integral reverse Pulsed Diode Forward Current a G I SM 68 p n junction diode S A Body Diode Voltage V SD T J = 25 C, I S = 7 A, V GS = 0 V b.5 V Body Diode Reverse t rr 520 780 ns Recovery Time T J = 25 C, I F = 7 A, di/dt = A/µs b Body Diode Reverse Recovery Charge Q rr 5.3 8.0 µc Forward TurnOn Time t on Intrinsic turnon time is negligible (turnon is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 µs; duty cycle 2 %. c. C oss eff. is a fixed capacitance that givs the same charging time as C oss while V DS is rising from 0 to 80 % V DS. Document Number: 9 2 S09005Rev. A, 9Jan09
I D, DraintoSource Current (A) I D, DraintoSource Current (A) I D, DraintoSource Current (A) TYPICAL CHARACTERISTICS 25 C, unless otherwise noted VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V.00.00 T J = 50 C 0. 5.0V.00 T J = 25 C 0.0 0.00 20µs PULSE WIDTH Tj = 25 C 0. V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics 0. V DS = V 20µs PULSE WIDTH 0.0 5.0 6.0 7.0 8.0 9.0.0 V GS, GatetoSource Voltage (V) Fig. 3 Typical Transfer Characteristics 0. 0.0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH Tj = 50 C 0. V DS, DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics R DS(on), DraintoSource On Resistance (Normalized) 3.0 I D = 7A 2.5 2.0.5.0 0.5 V GS= V 0.0 60 40 20 0 20 40 60 80 20 40 60 T J, Junction Temperature ( C) Fig. 4 Normalized OnResistance vs. Temperature Document Number: 9 S09005Rev. A, 9Jan09 3
000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd 00 C oss = C ds C gd C, Capacitance(pF) Ciss 0 Coss Crss 0 V DS, DraintoSource Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage I SD, Reverse Drain Current (A) T J = 50 C T J = 25 C V GS= 0 V 0. 0.2 0.5 0.8..4 V SD,SourcetoDrain Voltage (V) Fig. 7 Typical SourceDrain Diode Forward Voltage V GS, GatetoSource Voltage (V) 20 6 2 8 4 I D = 7A V DS= 400V V DS= 250V V DS= V 0 0 30 60 90 20 50 Q G, Total Gate Charge (nc) Fig. 6 Typical Gate Charge vs. GatetoSource Voltage I D, Drain Current (A) 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us us ms ms TC = 25 C TJ = 50 C Single Pulse 0. 0 00 V DS, DraintoSource Voltage (V) Fig. 8 Maximum Safe Operating Area Document Number: 9 4 S09005Rev. A, 9Jan09
20 V DS R D I D, Drain Current (A) 5 5 R G V GS V Pulse width µs Duty factor 0. % D.U.T. Fig. a Switching Time Test Circuit V DS 90 % V DD 0 25 50 75 25 50 T C, Case Temperature ( C) % V GS t d(on) t r t d(off) t f Fig. 9 Maximum Drain Current vs. Case Temperature Fig. b Switching Time Waveforms Thermal Response(Z thjc ) 0. 0.0 D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D =t / t 2 0.00 2. Peak T J=P DMx Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase PDM t t2 5 V V DS t p V DS L Driver R G I AS V DD A 20 V I AS 0.0 Ω t p D.U.T. Fig. 2a Unclamped Inductive Test Circuit Fig. 2b Unclamped Inductive Waveforms Document Number: 9 S09005Rev. A, 9Jan09 5
E AS, Single Pulse Avalanche Energy (mj) 750 600 450 300 50 TOP BOTTOM I D 7.6A A 7A 0 25 50 75 25 50 Starting T, Junction Temperature ( J C) Fig. 2c Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q G 50 kω V GS 2 V 0.2 µf 0.3 µf Q GS Q GD D.U.T. V DS V G V GS Charge Fig. 3a Basic Gate Charge Waveform 3 ma Fig. 3b Gate Charge Test Circuit I G I D Current sampling resistors Document Number: 9 6 S09005Rev. A, 9Jan09
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by duty factor "D" D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = V* D.U.T. I SD waveform Reverse recovery current Reapplied voltage Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt Inductor current Body diode forward drop V DD Ripple 5 % I SD * V GS = 5 V for logic level devices Fig. 4 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?9. Document Number: 9 S09005Rev. A, 9Jan09 7
Package Information TO220 D L H() Q L() E 2 3 M * b() Ø P A F DIM. MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 4.24 4.65 0.67 0.83 b 0.69.02 0.027 0.040 b().4.78 0.045 0.070 c 0.36 0.6 0.04 0.024 D 4.33 5.85 0.564 0.624 E 9.96.52 0.392 0.44 e 2.4 2.67 0.095 0.5 e() 4.88 5.28 0.92 0.208 F.4.40 0.045 0.055 H() 6. 6.7 0.240 0.264 J() 2.4 2.92 0.095 0.5 L 3.36 4.40 0.526 0.567 L() 3.33 4.04 0.3 0.59 Ø P 3.53 3.94 0.39 0.55 Q 2.54 3.00 0. 0.8 ECN: X50364Rev. C, 4Dec5 DWG: 603 Note M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM e b C e() J() ASE Package Picture Xi an Revison: 4Dec5 Document Number: 66542 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?90
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