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Transcription:

N-channel 600 V, 0.150 Ω typ., 20 A MDmesh M2 EP Power MOSFET in TO-220FP package Datasheet - production data Features Order code V DS R DS(on) max I D 600 V 0.163 Ω 20 A TO-220FP Figure 1: Internal schematic diagram D(2) G(1) Extremely low gate charge Excellent output capacitance (C OSS ) profile Very low turn-off switching losses 100% avalanche tested Zener-protected Applications Switching applications Tailored for very high frequency converters (f > 150 khz) Description These devices are N-channel Power MOSFETs developed using MDmesh M2 EP enhanced performance technology. Thanks to their strip layout and an improved vertical structure, these devices exhibit low on-resistance, optimized switching characteristics with very low turn-off switching losses, rendering them suitable for the most demanding very high frequency converters. S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing 27N60M2EP TO-220FP Tube January 2016 DocID028863 Rev 1 1/13 This is information on a product in full production. www.st.com

Contents Contents 1 Electrical ratings... 3 2 Electrical characteristics... 4 2.1 Electrical characteristics (curves)... 6 3 Test circuits... 8 4 Package information... 9 4.1 TO-220FP package information... 10 5 Revision history... 12 2/13 DocID028863 Rev 1

Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ± 25 V I D (1) I D (1) I DM (2) Drain current (continuous) at T C = 25 C 20 A Drain current (continuous) at T C = 100 C 13 A Drain current (pulsed) 80 A P TOT Total dissipation at T C = 25 C 30 W dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns V ISO T stg T j Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; T c = 25 C) Storage temperature Operating junction temperature 2.5 kv - 55 to 150 C Notes: (1) Limited by maximum junction temperature (2) Pulse width limited by safe operating area. (3) ISD 20 A, di/dt 400 A/µs; V DS(peak) < V (BR)DSS, V DD = 400 V. (4) VDS 480 V Table 3: Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max 4.2 C/W R thj-amb Thermal resistance junction-ambient max 62.5 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit I AR Avalanche current, repetetive or not repetetive (pulse width limited by T jmax ) 3.6 A E AS Single pulse avalanche energy (starting T j = 25 C, I D = I AR ; V DD = 50 V) 260 mj DocID028863 Rev 1 3/13

Electrical characteristics 2 Electrical characteristics T C = 25 C unless otherwise specified Table 5: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage drain current V GS = 0 V, I D = 1 ma 600 V V GS = 0 V, V DS = 600 V 1 µa V GS = 0 V, V DS = 600 V, T C = 125 C 100 µa I GSS Gate-body leakage current V DS = 0 V, V GS = ±25 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa 2 3 4 V R DS(on) V GS = 10 V, I D = 10 A 0.150 0.163 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss C oss C rss C oss eq. (1) R G Q g Q gs Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Intrinsic gate resistance Total gate charge Gate-source charge V DS = 100 V, f = 1 MHz, V GS = 0 V - 1320 - pf - 70 - pf - 1 - pf V DS = 0 to 480 V, V GS = 0 V - 146 - pf f = 1 MHz, I D = 0 A - 4 - Ω V DD = 480 V, I D = 20 A, V GS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 33 - nc - 5.2 - nc Q gd Gate-drain charge - 16 - nc Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit Static drain-source onresistance Turn-on - 13.4 - ns delay time V DD = 300 V, I D = 10 A, R G = 4.7 Ω, t r Rise time V GS = 10 V (see Figure 14: "Test circuit for - 8.1 - ns Turn-offdelay time "Switching time waveform" ) - 55.6 - resistive load switching times" and Figure 19: ns t d(on) t d(off) t f Fall time - 6.3 - ns 4/13 DocID028863 Rev 1

Table 8: Source-drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I SD I SDM (1) V SD (2) Source-drain current Source-drain current (pulsed) Forward on voltage - 20 A - 80 A V GS = 0 V, I SD = 20 A - 1.6 V t rr Q rr I RRM Reverse recovery time Reverse recovery charge Reverse recovery current I SD = 20 A, di/dt = 100 A/µs, V DD = 60 V (see Figure 19: "Switching time waveform") - 271 ns - 3.44 µc - 25.4 A t rr Q rr I RRM Reverse recovery time Reverse recovery charge Reverse recovery current I SD = 20 A, di/dt = 100 A/µs, V DD = 60 V, T j = 150 C (see Figure 19: "Switching time waveform") - 352 ns - 4.82 µc - 27.4 A Notes: (1) Pulse width is limited by safe operating area (2) Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID028863 Rev 1 5/13

Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Safe operating area GIPG140120161308 RV ID (A) Figure 3: Thermal impedance Operation in this area is 10 Limited by RDS(on) t p = 10 µs t p = 100µs 1 Single pulse,tc =25 C Tj 150 C,VGS=10 V t p = 1 ms t p = 10 ms 0.1 0.1 1 10 100 V DS [V] Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/13 DocID028863 Rev 1

Figure 8: Capacitance variations Electrical characteristics Figure 9: Output capacitance stored energy Figure 10: Normalized V(BR)DSS vs temperature Figure 11: Normalized gate threshold voltage vs temperature Figure 12: Normalized on-resistance vs temperature Figure 13: Source-drain diode forward characteristics DocID028863 Rev 1 7/13

Test circuits 3 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/13 DocID028863 Rev 1

Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DocID028863 Rev 1 9/13

Package information 4.1 TO-220FP package information Figure 20: TO-220FP package outline 10/13 DocID028863 Rev 1

Package information Table 9: TO-220FP package mechanical data mm Dim. Min. Typ. Max. A 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.45 0.7 F 0.75 1 F1 1.15 1.70 F2 1.15 1.70 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 Dia 3 3.2 DocID028863 Rev 1 11/13

Revision history 5 Revision history Table 10: Document revision history Date Revision Changes 14-Jan-2016 1 First release. 12/13 DocID028863 Rev 1

IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 2016 STMicroelectronics All rights reserved DocID028863 Rev 1 13/13