FDMB38PZ Dual Common Drain P-Channel PowerTrench MOSFET - V, -7 A, 36 mω Features Max r SS(on) = 36 mω at V GS = -4.5 V, I D = -5.7 A Max r SS(on) = 5 mω at V GS = -.5 V, I D = -4.6 A Low Profile -.8 mm maximum - in the new package MicroFET x3 mm HBM ESD protection level.8 kv (Note 3) RoHS Compliant Pin MLP x3 Pin S S S D/D S G G General Description April 4 This device is designed specifically as a single package solution for Li-Ion battery pack protection circuit and other ultra-portable applications. It features two common drain P-channel MOSFETs, which enables bidirectional current flow, on Fairchild s advanced PowerTrench process with state of the art MircoFET Leadframe, the FDMB38PZ minimizes both PCB space and r SS(on). Application Li-Ion Battery Pack G S S 4 3 5 6 G S S FDMB38PZ Dual Common Drain P-Channel PowerTrench MOSFET MOSFET Maximum Ratings T A = 5 C unless otherwise noted Symbol Parameter Ratings Units V SS Source to Source Voltage - V V GS Gate to Source Voltage ± V Source to Source Current -Continuous T A = 5 C (Note a) -7 I SS -Pulsed -3 A Power Dissipation T A = 5 C (Note a). P D Power Dissipation T A = 5 C (Note b).8 W T J, T STG Operating and Storage Junction Temperature Range -55 to +5 C Thermal Characteristics R θja Thermal Resistance, Junction to Ambient (Note a) 57 R θja Thermal Resistance, Junction to Ambient (Note b) 6 Package Marking and Ordering Information C/W Device Marking Device Package Reel Size Tape Width Quantity 38 FDMB38PZ MLP x3 7 8 mm 3 units 3 Fairchild Semiconductor Corporation FDMB38PZ Rev.C3
Electrical Characteristics T J = 5 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics I SS Zero Gate Voltage Source to Source Current V SS = -6 V, V GS = V - μa I GSS Gate to Source Leakage Current V GS = ± V, V SS = V ± μa On Characteristics V GS(th) Gate to Source Threshold Voltage V GS = V SS, I SS = -5 μa -.6 -.9 -.5 V Dynamic Characteristics Switching Characteristics Source- Source Diode Characteristics V GS = -4.5 V, I SS = -5.7 A 7 36 V r SS(on) Static Source to Source On Resistance GS = -.5 V, I SS = -4.6 A 36 5 mω V GS = -4.5 V, I SS = -5.7 A, 35 49 T J = 5 C g FS Forward Transconductance V SS = -5 V, I SS = -5.7 A 9 S C iss Input Capacitance 8 33 pf V SS = - V, V GS = V, C oss Output Capacitance 36 54 pf f = MHz C rss Reverse Transfer Capacitance 339 5 pf t d(on) Turn-On Delay Time 4 5 ns t r Rise Time V SS = - V, I SS = -5.7 A 33 5 ns t d(off) Turn-Off Delay Time V GS = -4.5 V, R GEN = 6 Ω 74 8 ns t f Fall Time 58 93 ns Q g Total Gate Charge V SS = - V, I SS = -5.7 A, 3 nc Q gs Gate to Source Charge V GS = -4.5 V, V GS = V 3.6 nc Q gd Gate to Source Miller Charge 7.7 nc I fss Maximum Continuous Source-Source Diode Forward Current -5.7 A V fss Source to Source Diode Forward Voltage V GS = V, V GS = -4.5 V, - -.6 V I fss = -5.7 A (Note ) FDMB38PZ Dual Common Drain P-Channel PowerTrench MOSFET NOTES:. R θja is determined with the device mounted on a in pad oz copper pad on a.5 x.5 in. board of FR-4 material. R θjc is guaranteed by design while R θca is determined by the user's board design. a. 57 C/W when mounted on a in pad of oz copper b. 6 C/W when mounted on a minimum pad of oz copper. Pulse Test: Pulse Width < 3 μs, Duty cycle <.%. 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 3 Fairchild Semiconductor Corporation FDMB38PZ Rev.C3
Typical Characteristics T J = 5 C unless otherwise noted -ISS, SOURCE TO SOURCE CURRENT (A) NORMALIZED SOURCE TO SOURCE ON-RESISTANCE 3 V GS = -4.5 V V GS = -3 V V GS = -.5 V V GS = -4.5 V V GS = -.8 V.5..5. Figure. 3 V GS = - V -V SS, SOURCE TO SOURCE VOLTAGE (V) V GS = -.8 V -ISS, SOURCE TO SOURCE CURRENT (A).5..5. -V SS, SOURCE TO SOURCE VOLTAGE (V) On-Region Characteristics Figure. On-Region Characteristics V GS = - V V GS = -4.5 V V GS = -.5 V V GS = -3 V V GS = -4.5 V 3 -I SS, SOURCE TO SOURCE CURRENT (A) Figure 3. Normalized On-Resistance vs Source to Source Current and Gate Voltage NORMALIZED SOURCE TO SOURCE ON-RESISTANCE 3 4 3 V GS = -4.5 V V GS = -3 V V GS = -.8 V V GS = -.5 V V GS = - V V GS = - V V GS = -.8 V V GS = -.5 V V GS = -4.5 V 3 -I SS, SOURCE TO SOURCE CURRENT (A) V GS = -3 V Figure 4. Normalized On-Resistance vs Source to Source Current and Gate Voltage FDMB38PZ Dual Common Drain P-Channel PowerTrench MOSFET NORMALIZED SOURCE TO SOURCE ON-RESISTANCE.6.4...8 I SS = -5.7 A V GS = -4.5 V.6-5 -5 5 5 75 5 5 T J, JUNCTION TEMPERATURE ( o C) rss(on), SOURCE TO SOURCE ON-RESISTANCE (mω) 5 5 T J = 5 o C T J = 5 o C I SS = -5.7 A.5..5 3. 3.5 4. 4.5 -V GS, GATE TO SOURCE VOLTAGE (V) Figure 5. Normalized On Resistance vs Junction Temperature Figure 6. On Resistance vs Gate to Source Voltage 3 Fairchild Semiconductor Corporation FDMB38PZ Rev.C3 3
Typical Characteristics T J = 5 C unless otherwise noted -I SS, SOURCE TO SOURCE CURRENT (A) -VGS, GATE TO SOURCE VOLTAGE (V) 3 V SS = -5 V T J = -55 o C..5..5 -V GS, GATE TO SOURCE VOLTAGE (V) 4.5 3..5 Figure 7. T J = 5 o C T J = 5 o C -Ifss, SOURCE TO SOURCE FORWARD CURRENT (A)..6..8 Transfer Characteristics Figure 8. Source to Source Diode Forward Voltage vs Source Current V GS = V, I SS = -5.7 A V SS = - V V SS = -8 V V SS = - V 5 5 5 Q g, GATE CHARGE (nc) Figure 9. Gate Charge Characteristics CAPACITANCE (pf).. 5 V GS = V, V GS = -4.5 V T J = 5 o C T J = 5 o C T J = -55 o C -V fss, BODY DIODE FORWARD VOLTAGE (V) f = MHz V GS = V C iss C oss C rss. -V SS, SOURCE TO SOURCE VOLTAGE (V) Figure. Capacitance vs Source to Source Voltage FDMB38PZ Dual Common Drain P-Channel PowerTrench MOSFET -Ig, GATE LEAKAGE CURRENT (A) -3-4 -5-6 -7-8 -9-5 5 -V GS, GATE TO SOURCE VOLTAGE (V) Figure. V SS = V T J = 5 o C T J = 5 o C Gate Leakage Current vs Gate to Source Voltage -ISS, SOURCE TO SOURCE CURRENT (A) 5.. THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE T J = MAX RATED R θja = 6 o C/W T A = 5 o C.. Figure. Forward Bias Safe Operating Area ms ms ms s s DC -V SS, SOURCE TO SOURCE VOLTAGE (V) 3 Fairchild Semiconductor Corporation FDMB38PZ Rev.C3 4
Typical Characteristics T J = 5 C unless otherwise noted P (PK), PEAK TRANSIENT POWER (W) NORMALIZED THERMAL IMPEDANCE, Z θja. -3 - - t, PULSE WIDTH (sec).. DUTY CYCLE-DESCENDING ORDER D =.5...5.. Figure 3. Single Pulse Maximum Power Dissipation SINGLE PULSE R θja = 6 o C/W SINGLE PULSE R θja = 6 o C/W T A = 5 o C. -3 - - t, RECTANGULAR PULSE DURATION (sec) P DM t t NOTES: DUTY FACTOR: D = t /t PEAK T J = P DM x Z θja x R θja + T A FDMB38PZ Dual Common Drain P-Channel PowerTrench MOSFET Figure 4. Junction-to-Ambient Transient Thermal Response Curve 3 Fairchild Semiconductor Corporation FDMB38PZ Rev.C3 5
Dimensional Outline and Pad Layout FDMB38PZ Dual Common Drain P-Channel PowerTrench MOSFET Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http:///package/packagedetails.html?id=pn_mldea-c6 3 Fairchild Semiconductor Corporation FDMB38PZ Rev.C3 6
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Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete 3 Fairchild Semiconductor Corporation FDMB38PZ Rev.C3 Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. 7 Rev. I68
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