Feature-level Compensation & Control

Feature-level Compensation & Control

2 Sensors and Control Nathan Cheung, Kameshwar Poolla, Costas Spanos Workshop 11/19/2003

3 Metrology, Control, and Integration Nathan Cheung, UCB SOI Wafers Multi wavelength Emitters /Filter/Detectors Si & Si-Ge Si-/Ge Low power electronics Green LED Blue LED 200 µm - 5mm Interest: Heterogeneous Integration of Electronic Materials and Microsystems Layer transfer technologies IC, Photonics, and MEMS 3D IC structures CPU Encapsulated battery with switch/led MOS IC III-V Photonics on Si Micro pump OLED display Laser Array Laser Emitter Arrays Micro Optical mirrors Modulator Micro-fluidic channels Encapsulated MEMS Power source MEMS 1µm Research Themes: Layer Transfer for Si/Ge-on-insulator and Strained Si-on- insulator substrates Zero footprint metrology wafer with optical mapping capability Si channels

4 Zero-Footprint Metrology Wafer ZhongSheng Luo, Prof. Nathan Cheung, UC Berkeley First Year Objectives Demonstrate 3x3 pixels wired zero-footprint metrology wafer. Thickness monitoring for etching, resist development, and CMP

5 Zero-Footprint Metrology Wafer Data Transmission ZhongSheng Luo and Nathan Cheung University of California, Berkeley Dielectric Layer 500µm Si Photo-/RF Transmitter Data Processing, Storage Unit Battery Data Acquisition Unit 2003 Goals : Prototyping a zero-footprint metrology wafer with optical detection unit and encapsulated power source.

6 Proposed Architecture Power Management & RF Transmission Unit + - + - Power Self-contained wireless transmitter powered by solar energy (Rabaey, UCB) Measurement Units Integrated excitation/detection Unit (Z.S. Luo, UCB) Power Unit Thin film Battery (Front Edge Tech, Inc.)

7 Progress: Encapsulation of Polymer battery, optical switch, and LED LED Power Off + - + - 1 mah Optical Switch Thin Film Battery Transmission Infrared Images Power On LED

8 Feasibility Test: Thickness Measurement Green LED Blue LED Test Coating Glass Slide LED PD Si 5mm Filter Reflection Intensity (a.u.) -2-4 -6-8 -10-12 -14 Shipley S1818 PR on Glass Slide Excitation λ=525nm -16 1500 1600 1700 1800 1900 2000 2100 2200 PR Thickness (nm) Theoretical Curve Packaging Substrate

9 Summary Demonstrated encapsulating emitter/detector unit and power source Demonstrated feasibility of thickness measurement with emitter/detector unit. 2003-2004 Goals Demonstrate 3x3 pixels wired zero-footprint metrology wafer. Thickness monitoring for etching, resist development, and CMP.

10 Future Goals on Integration Year 1: A wired 3x3 pixels prototype wafer for thickness and endpoint mapping measurements Year 2: Process monitoring demonstration for RIE, CMP, and resist development Year 3: Leverage on other Berkeley wireless chip projects to incorporate RF transmission in metrology wafer Year 4: A full 9x9 pixels metrology wafer

11 Aerial Image Sensor Jing Xue, Prof. Costas J. Spanos, UC Berkeley First Year Objectives Complete the photo-detector technology and electrical parameter design Start the mask aperture layout design and preliminary fabrication test Develop the mathematic model of the sensor system Complete design of transducer capable of nm-scale aerial image resolution

12 The Problem The feature size to be printed: ~ 0.1µm magnitude The minimum window size of practical UV detectors: > 0.3µm UV light SiO2 PD window p+ SiO2 I n+ How can the detector retrieve nanometer scale resolution of the aerial image?

13 Our Approach Mask aperture Poly-silicon mask Photo detector Substrate

14 Moving Aperture Design A periodic sequence of apertures, illuminated by a periodic image, whose spatial period is slightly different from that of the aperture pattern N 1 *p+δ x N 2 *p+2δ x N 3 *p+3δ x

15 A single mask aperture: Near-field Optical Simulation Topography (block) of the simulation domain Mask thickness: 100nm; Aperture size: 100nm; Si wafer: 500nm

16 Near-Field Optical Simulation mask Intensity at the center of the simulation domain

17 Near-field Optical Simulation 4.5 4.0 3.5 intensity flux 3.0 2.5 2.0 t mask =100nm l aperture =100nm 1.5 0 20 40 60 80 100 120 140 160 180 200 deltaψ 0 13 26 39 52 65 78 91 104 117 delta x (nm) Integrated intensity vs. delta(ψ) and delta (x) variation Delta(Ψ)=180 degree corresponds to moving aperture with a half of spatial period

18 Near-field Optical Simulation Intensity Flux 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 l aperture =80nm l aperture =100nm l aperture =120nm t mask =100nm Intensity flux 4.5 4.0 3.5 3.0 2.5 t mask =100nm t mask =120nm t mask =150nm l aperture =100nm 1.5 1.0 2.0 0.5 0 50 100 150 200 deltaψ 1.5 0 50 100 150 200 delta ψ 0 32.5 65 97.5 130 Delta x (nm) 0 32.5 65 97.5 130 Delta x (nm) aperture size 80nm 100nm 120nm thickness 100nm 120nm 150nm contrast 0.3934 0.3698 0.3432 contrast 0.3698 0.324 0.2149 Smaller apertures and thinner masks tend to improve the contrast at the detector.

19 Future Goals for Aerial Image Sensors Complete design of transducer capable of nm-scale aerial image resolution (year I milestone: 1/27/2004 1/26/2005) Integrate prototype transducer for use and development on a wafer (year II milestone: 1/27/2005 1/26/2006) Possible integration with wireless wafer sensor platform after 2006.

20 First Principle-Based State Estimator and Time-Based PEB Modeling for Lithography Process Control Paul Friedberg, Prof. Costas Spanos, UC Berkeley Evaluate the proposed state estimation framework in an empirical setting by 12/15/2003. Complete time-based PEB modeling for optimizing CD distributions by 2/15/2004.

21 Litho Control Background Advanced process control in lithography module will require a means of deriving process input conditions from generated output in real time: 1) Scatterometry allows us to determine the output profile quickly and non-destructively 2) Profile inversion using the profile determined by SSS to derive the input parameter values is required to monitor and control parameter drift

22 Control Flow With Novel Inversion Inversion is accomplished in forward simulation

23 Simulation Experiment Results (from a 27k entry library) Estimated Exp. Estimated Exp. Exposure Fitting Exposure Fitting R 2 = 0.9849 R 2 = 0.9849 30.0 30.0 29.5 29.5 29.0 29.0 28.5 28.5 28.0 28.0 28.0 28.5 29.0 29.5 30.0 28.0 28.5 29.0 29.5 30.0 Actual Exp. Actual Exp. Estimated Foc. Estimated Foc. Foc. Fitting Foc. Fitting R 2 = 0.9955 R 2 = 0.9955 0.5 0.5 0.3 0.3 0.1 0.1-0.5-0.3-0.1-0.1-0.1 0.1 0.3 0.5-0.5-0.3-0.1 0.1 0.3 0.5-0.3-0.3-0.5-0.5 Actual Foc. Actual Foc. Estimated Temp Estimated Temp PEB Temp Fitting R 2 = 0.9868 PEB Temp Fitting R 2 = 0.9868 132 132 131 131 130 130 129 129 128 128 128 129 130 131 132 128 129 130 131 132 Actual Temp Actual Temp Estimated Time Estimated Time PEB Time Fitting R 2 = 0.9733 PEB Time Fitting R 2 = 0.9733 63 63 62 62 61 61 60 60 59 59 58 58 57 57 57 58 59 60 61 62 63 57 58 59 60 61 62 63 Actual Time Actual Time

24 PEB/CD Correlation Example Raw data Average field - = Across-wafer variation (steady state)

25 Spatial PEB/CD Distribution Correlation Plotting both the bake plate temperature trajectory and R 2 from temperature-cd correlation against bake time: Max R 2 during the transient heating period Continued high R 2 during steady state due to poor temperature control in single-zone plate design

26 Future Litho (profile inversion) Control Goals Evaluate the state-estimation framework empirically in an industry fab Repeat PEB/CD correlation for multiple-zone bake plate design; develop time-based model for PEB s impact on resulting CD distribution Unify state estimation framework, PEB-CD timebased model into single process control framework; implement complete framework in fabrication environment

27 CD Uniformity Control Across Litho-etch Sequence Qiaolin(Charlie) Zhang, Prof. Kameshwar Poolla, Prof. Costas Spanos, UC Berkeley Provide a model of post-develop CDU, based on PEB bake plate simulator and a well-tuned PROLITH model (done). Optimize post-develop CDU based on CDU model within PROLITH (done). Verify the approach experimentally at an industrial facility (on-going).

28 The Problem Wafer Litho Etch Processing Tool Poor Across-Wafer CD Uniformity How can we improve the across-wafer CDU? How much can we improve CDU?

29 Our Approach Compensate for systematic spatial non-uniformities across the litho-etch sequence using all available control authority: Exposure step: die to die dose PEB step: temperature of multi-zone bake plate Etch: backside pressure of dual-zone He chuck Exposure PEB / Develop Etch dose temperature He pressure Optimizer Wafer-level CD Metrology Scatterometry/CDSEM

30 Optimization Results in PROLITH Std=1.54 nm Std=5.0 nm Std=2.3 nm CD Map after individual die dose optimization Std=1.87 nm Nominal CD Map (assuming elliptic acrosswafer resist thickness) CD Map after PEB optimization CD Map after grouped die dose optimization

31 Future Work on CDU Control Official milestone: Initial modeling studies for CD uniformity control Goal 1: Assess controllability of various actuator setting in the litho-etch sequence for reduction of CD non-uniformity Goal 2: Select processing sequence and build sensitivity model