FIVE-LEVEL HYBRID CONVERTER BASED ON A HALF-BRIDGE/ANPC CELL R. N. A. L. Silva 1, L. H. S. C. Barreto 2, D. S Oliveira Jr. 3, G. A. L. Henn 4, P. P. Praça 5, M. L. Heldwein 6 and S.A. Mussa 7, Universidade Federal do Ceará 1,2,3,4,5 Grupo de Processamento de Energia e Controle (GPEC) Departamento de Engenharia Elétrica. Caixa Postal 6001 60544-760, Fortaleza, CE, Brasil E-mail: ranoyca@dee.ufc.br 1, lbarreto@dee.ufc.br 2 Universidade Federal de Santa Catarina 6,7 Electrical Engineering Department, Power Electronics Institute, P.O. Box 5119, 88040-970, Florianópolis, SC, Brazil E-mail: heldwein@inep.ufsc.br 6 Abstract This work presents a novel five-level hybrid Half-Bridge/ANPC multilevel inverter. Along with the switching states possibilities, employed modulation techniques, conduction losses analysis, and simulation results from a three-phase topology, it is presented the experimental results from a monophasic structure, operating with 1020Hz switching frequency, output frequency of 60Hz, phase output voltage of 220Vrms, output power of 2.3kW and power factor of 0.92. From the presented results, it can be noticed the reduced losses and better harmonic content. Keywords - Multilevel inverter, THD, losses reduction. I. INTRODUCTION Among the last years, several multilevel inverter topologies and different modulation strategies have been developed and used due to the capability of reducing output voltage harmonics, and semiconductors voltage stress, especially in medium and high power applications, as reactive power compensators and AC motor drives. The main advantages inherent to the multilevel converters are: improved energy quality, reducing the filter components requirements, higher efficiency, especially on lower output power and medium voltage range applications, and lower harmonics distortion. Some hybrid topologies presenting five levels at the output phase voltage were introduced in [5-7], presenting costs, volume, and control complexity reduction when compared with other topologies. An important feature that should be noticed in these topologies is the presence of devices with different blocking voltage ratings and switching at different frequencies. This paper presents a novel three-phase hybrid multilevel inverter topology. To validate the inverter structure, two different modulation techniques were used, and the results presented confirm the converter efficiency. II. FIVE-LEVEL HYBRID CONVERTER BASED ON A HALF-BRIDGE/ANPC CELL The proposed topology is shown in Fig. 1, where some restrictions on the switches driving process can be noticed: switches Sx5 and Sx6 present low frequency operation and cannot be turned-on and turned-off simultaneously; Sx2 and Sx3 (as Sx1 and Sx4) cannot be turned-off simultaneously; at last, Sx4 and Sx8 cannot be turned-on simultaneously (as Sx1 and Sx7), where x = a,b,c. Thus, applying an appropriate modulation, it is possible to obtain five levels on output phase voltage, as presented on Table 1. It can be noticed that there are eight possibilities to obtain the level 0, four to obtain the +Vdc, four to obtain -Vdc, and nine possibilities to obtain Vdc/2, as more nine to obtain -Vdc/2. Fig 2 presents the space vector diagram with 125 switching states, where 61 are redundant states, and 96 triangles on the αβ-plane. III. MODULATION TECHNIQUE In order to validate the multilevel inverter topology proposed, two modulation techniques were applied. The first one is based on a phase disposition PWM (PD-PWM) scheme that was presented in [1] and which basis is observed on Fig. 3(a). The second technique is based on a Centered Space Vector PWM (CSV-PWM) scheme based on [2], as presented on Fig. 3(b). The switching logical states used for both are described as follows, and observed on Fig. 3(d). Fig. 1. Three-phase proposed topology. 978-1-4577-1646-1/11/$26.00 2011 IEEE 898
TABLE I Possible states Sa1 Sa2 Sa3 Sa4 Sa5 Sa6 Sa7 Sa8 Phase A 0 0 1 0 0 1 0 1 -Vdc/2 0 0 1 0 0 1 1 1 -Vdc/2 0 0 1 0 1 0 0 1 Vdc/2 0 0 1 0 1 0 1 1 Vdc/2 0 0 1 1 0 1 0 0 -Vdc 0 0 1 1 0 1 1 0 -Vdc 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 1 1 0 -Vdc/2 0 1 0 0 0 1 1 1 -Vdc/2 0 1 0 0 1 0 1 0 Vdc/2 0 1 0 0 1 0 1 1 Vdc/2 0 1 0 1 0 1 1 0 -Vdc/2 0 1 0 1 1 0 1 0 Vdc/2 0 1 1 0 0 1 0 1 -Vdc/2 0 1 1 0 0 1 1 0 -Vdc/2 0 1 1 0 0 1 1 1 -Vdc/2 0 1 1 0 1 0 0 1 Vdc/2 0 1 1 0 1 0 1 0 Vdc/2 0 1 1 0 1 0 1 1 Vdc/2 0 1 1 1 0 1 0 0 -Vdc 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 1 -Vdc/2 1 0 1 0 1 0 0 1 Vdc/2 1 0 1 1 0 1 0 0 -Vdc 1 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 Vdc 1 1 0 0 1 0 0 1 Vdc 1 1 0 1 0 1 0 0 0 1 1 0 1 1 0 0 0 Vdc 1 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 Vdc Considering phase A, for example, in the positive semicycle: 1) Sa5 is always turned on and, consequently, Sa6 is turned off. 2) For output voltages between the levels Vdc/2 and Vdc: keeping the switch Sa2 always on; switching Sa1 at the carrier frequency to obtain Vdc; switching Sa7 to obtain Vdc/2; the other semiconductors are off. 3) For output voltages between level zero and Vdc/2: keeping the switch Sa3 always on; switching Sa8 to obtain Vdc/2; switching Sa4 to obtain zero; the other semiconductors are off. For the negative semi-cycle, the operation is analogous to the positive one. Thus, the semiconductors Sa2, Sa3, Sa5 and Sa6 present low frequency operation, while the others present high frequency operation. Fig. 2. Space-vector diagram for the proposed three-phase hybrid five-level dc ac converter. Fig. 4(a) presents the voltage, current and fundamental output voltage on phase A waveforms of the inverter using the modulation strategy presented on Fig. 3(a), while Fig. 4(b) presents the same waveforms using the modulation strategy presented on Fig. 3(b). The first simulation result presented a line-to-line voltage with 17.69% THD, while the second one, 17.22% THD. Fig. 5 presents the graphical conduction losses analysis across each switch and intrinsic diode on one inverter leg from the simulated structure results. It must be observed that, for both modulation strategies, the losses distribution is very similar. Also, the total conduction losses in one phase for both modulation techniques is, approximately, 36W for the switches, and 6.9W for the intrinsic diodes. IV. SIMULATION AND EXPERIMENTAL RESULTS The simulation results of a structure powered by a bus voltage of 340 V, switching frequency of 1020Hz, mains output frequency of 60 Hz, line output voltage of 380 V rms, total apparent output power of 7.5 kva and power factor of 0.92 are presented. Fig. 3. Modulations. (a) Proposed by [1]; (b) CSV-PWM derived; (c) Five-levels output voltage obtained using modulation presented on Fig. 3(b); (d) Switching. 899
Figs. 8, 9 and 10 present, respectively, the carriers signals and the switching drive signals employed on both modulation techniques PD-PWM and CSV-PWM for one inverter leg. Fig. 6. Modulators signals, proposed in [1], digitally generated by the FPGA. Fig. 4. Output voltage, current and fundamental voltage waveforms on phase A; (a) Using the PD-PWthe CSV-PWM strategy of Fig. strategy of Fig. 3(a); (b) Using 3(b). Fig. 7. Modulators signals used on CSV-PWM strategy, generated by the FPGA. Fig. 5. Conduction lossess analysis across each switch and respective diodes. The following experimental results are due to the operation of the monophasic structure. The modulation techniques were digitally implemented using a FPGA. Figs. 6 and 7 show the waveforms for the digitally generated modulator signals from both modulation techniques (PD- PWM and CSV-PWM). It must be observed an angle shift of 120º between the modulators, a fixed frequency of 60Hz, and the absence of deformations. Fig. 8. Carriers signals used on both modulation techniques, digitally generated by the FPGA. 900
Figs. 11 and 12 present output voltage and current, and DC bus voltage waveforms for PD-PWM and CSV-PWM, respectively. Fig. 13 presents the frequency spectrum of the phase voltage, employing both modulation techniques, where it can be observed that the output voltage has low harmonic content. The measured output voltage THD was 29%, for the PD-PWM, and 38% for the CSV-PWM. These results show that, when compared to other structures, as proposed in [8], they present lower harmonic content. Fig. 9. Gate signals for the PD-PWM technique. Fig. 11. Output voltage and current, and DC bus voltage waveforms for the PD-PWM technique. Fig. 10. Gate signals for the CSV-PWM technique. Fig. 12. Output voltage and current, and DC bus voltage waveforms for the CSV-PWM technique. 901
Fig. 13. Harmonic content for both modulation techniques. V. CONCLUSION An adapted novel three-phase five-level hybrid multilevel inverter topology operating with two different modulation techniques is proposed in this paper. The simulation results show the output phase voltages presenting five levels for both modulation schemes and, thus, validating the proposed topology. Observing the possible switching states presented, several other modulation techniques can be developed, depending on the proposed goals. Thus, two modulation techniques were implemented: PD-PWM e CSV-PWM. The main advantages of the proposed topology are: low THD and the reduced losses, due to the low frequency operation presented in some switches. As disadvantage, it can be cited the high number of isolated sources, necessary for three-phase applications. At last, experimental results from a monophasic, fivelevels, 2.3kW prototype were presented, validating the proposed topology. Decoder, IEEE Transactions on Power Electronics, vol.22, no.2, pp.508-516, March 2007. [4] G. Carmona, R. Ramos, D. Ruiz-Caballero, S.A. Mussa, T. Meynard, Symmetrical hybrid multilevel Dc-Ac Converters Using the PD-CSV Modulation, in Industrial Electronics, 2008, 34th Annual Conference of IEEE, pp.3327-3332, Nov. 2008. [5] D.A. Ruiz-Caballero, R.M. Ramos-Astudillo, S.A. Mussa, M.L. Heldwein, Symmetrical Hybrid Multilevel DC AC Converters With Reduced Number of Insulated DC Supplies, IEEE Transactions on Industrial Electronics, vol.57, no.7, pp.2307-2314, July 2010. [6] F. Kieferndorf, M. Basler, L. A. Serpa, J.-H. Fabian, A. Coccia, G. A. Scheuer, A new medium voltage drive system based on ANPC-5L technology, in Industrial Technology, 2010 IEEE International Conference on, ICIT 10, no., pp.643-649, March 2010. [7] T. Chaudhuri, P. Steimer, and A. Rufer, Introducing the Common Cross Connected Stage (C3S) for the 5L ANPC multilevel inverter, in Power Electronics Specialists Conference, 2008. PESC 2008. IEEE, pp.167-173, 15-19 June 2008. [8] A. Batschauer, S. Mussa, M. Heldwein, "Three-Phase Hybrid Multilevel Inverter Based on Half-Bridge Modules," IEEE Transactions on Industrial Electronics, vol.pp, no.99, pp.1, 0. [9] Anees Abu Sneineh; Ming-yan Wang;, "Novel Hybrid Flying-Capacitor-Half-Bridge 9-Level Inverter," TENCON 2006. 2006 IEEE Region 10 Conference, vol., no., pp.1-4, 14-17 Nov. 2006 [10] G Carrara, S. Gardella, M. Marchenosi, R. Salutari, G. Sciutto, A new multilevel PWM method: A Theoritical Analysis, IEEE Transactions on Power Electronics, Vol 7, July 1992, pp. 497-505. ACKNOWLEDGEMENT The authors would like to thank to CAPES and CNPq for the financial support (PROCAD 2007 CAPES/UFC/UFSC and CNPq 554598/2010-8) REFERENCES [1] Ding Kai; Zou Yun-ping; Cai Zheng-ying; Wu Zhi-chao; Liu Fei; Xu Xiang-lian;, "A novel single-phase 5-level asymmetric inverter," Power Electronics and Motion Control Conference, 2004. IPEMC 2004. The 4th International, vol.2, pp. 793-798. [2] B. P. McGrath, D. G. Holmes and T. A. Lipo, Optimized space vector switching sequences for multilevel inverters, IEEE Transactions on Power Electronics, vol.18, no.6, pp. 1293-1301, Nov. 2003. [3] B. P. McGrath, T. A. Meynard, G. G. Gateau, D. G. Holmes, Optimal Modulation of Flying Capacitor and Stacked Multicell Converters Using a State Machine 902