An n-level flying capacitor based active neutralpoint-clamped

Transcription

1 University of Wollongong Research Online Faculty of Engineering and Information Sciences - Papers: Part A Faculty of Engineering and Information Sciences An n-level flying capacitor based active neutralpoint-clamped converter Sridhar R. Pulikanti University of Sydney, sridhar@uow.edu.au Georgios S. Konstantinou University Of New South Wales Vassilios G. Agelidis University of New South Wales Publication Details Pulikanti, S. R., Konstantinou, G. S. & Agelidis, V. G. (). An n-level flying capacitor based active neutral-point-clamped converter. nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG (pp ). Australia: IEEE. Research Online is the open access institutional repository for the University of Wollongong. For further information contact the UOW Library: research-pubs@uow.edu.au

2 An n-level flying capacitor based active neutral-point-clamped converter Abstract An n-level flying capacitor (FC) based active neutral point clamped (ANPC) converter is discussed in this paper. The converter is based on an arrangement of a three-level ANPC converter and a number of two-level cells creating an n-level line-to-neutral waveform. The converter is operated under a phase-shifted carrier pulse-width modulation (PWM). The mathematical model for the DC-link capacitors voltage behavior of a three-phase arrangement is also presented. It is shown through simulations and experimental work that the voltage of flying capacitors can naturally balance to the required level in order to generate multilevel waveform. Simulations and experimental work of a single-phase seven-level ANPC converter prototype are also presented. Keywords active, capacitor, flying, n, level, converter, clamped, point, neutral Disciplines Engineering Science and Technology Studies Publication Details Pulikanti, S. R., Konstantinou, G. S. & Agelidis, V. G. (). An n-level flying capacitor based active neutralpoint-clamped converter. nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG (pp ). Australia: IEEE. This conference paper is available at Research Online:

3 nd IEEE International Symposium on Power Electronics for Distributed Generation Systems An n-level Flying Capacitor based Active Neutral-Point-Clamped Converter Sridhar R. Pulikanti Georgios S. Konstantinou and Vassilios G. Agelidis The University of Sydney, Sydney, NSW, 6, Australia The University of New South Wales, Sydney, NSW, 5, Australia Abstract An n-level flying capacitor (FC) based active neutral point clamped (ANPC) converter is discussed in this paper. The converter is based on an arrangement of a three-level ANPC converter and a number of two-level cells creating an n-level line-to-neutral waveform. The converter is operated under a phase-shifted carrier pulse-width modulation (PWM). The mathematical model for the DC-link capacitors voltage behavior of a three-phase arrangement is also presented. It is shown through simulations and experimental work that the voltage of flying capacitors can naturally balance to the required level in order to generate multilevel waveform. Simulations and experimental work of a single-phase seven-level ANPC converter prototype are also presented. Index Terms Active neutral point clamped converter, carrier based pulse-width modulation, flying capacitor converter, multilevel converter I. INTRODUCTION Multilevel converters have become popular in recent years due to their high-voltage and high-power capability []. They have numerous advantages such as lower harmonic distortion and lower electro-magnetic interference (EMI) and reduced stressed of the semiconductor switching devices when compared with the conventional two-level converter. These advantages have made them particularly attractive for industrial applications such as motor drives [], advanced staticcompensators (STATCOMs) [3], high-power high-voltage direct-current (HVDC) power transmission [4], etc. The main multilevel converter topologies are the neutralpoint clamped (NPC), the flying capacitor (FC) converter and the cascaded H-bridge (CHB) converters []. As the number of levels in the output voltage of a multilevel converter increases, the complexity of the neutral point voltage control of the NPC converter, the stored energy components of the FC converter and the number of isolated power supplies of the cascaded H-bridge converter increases. This increase in complexity together with the increase in the number of components affects the reliability and the efficiency of the converter [5]. In recent years, hybrid multilevel converters using different arrangements of conventional multilevel topologies have been introduced. These include the three-level active neutral point clamped converter (ANPC) converter [6] with a FC converter generating a five-level (5L) output waveform, the two-level converter with an H-bridge cell which generates a five-level output waveform and the three-level NPC converter with an H-bridge cell [5] which generates a seven-level (7L) output waveform. Based on the hybrid configuration of a 3L-ANPC converter [6] and a 3L FC converter, a 5L-FC based ANPC converter was developed for motor drive applications [7]. In [8], the experimental validation of the 5L-FC based ANPC converter using carrier based disposition (CBD) pulse-width modulation (PWM) to control the neutral point voltage and FC voltage were presented. In [9], a 5L-FC based ANPC converter for STATCOM application with phase shifted carrier (PSC) PWM using simulation results is verified. Hybrid configurations also provide the advantage of combining high-volume semiconductors such as the integrated gate-commutated thyristor (IGCT) and insulated gate bipolar thyristor (IGBT) in order to decrease the conduction losses []. Optimized pulse patterns with low switching frequency to deal with voltage balancing and switching frequency issues were presented in [] and the control under selective harmonic elimination PWM was proposed in []. The objective of this paper is to discuss a generalized nlevel FC-based ANPC converter operated with PSC-PWM. The PSC-PWM provides natural balancing of FCs [3] and under this modulation scheme both FCs and DC-link capacitors of this converter topology balances to required voltage level. The DC-link capacitors behavior is mathematically derived for three-phase arrangement where the average value of neutral point current over fundamental period is zero when the voltage across the DC-link capacitors and FCs naturally balance. The paper is organized in the following way. Section II describes the topology and operating principles of the n-level FC based ANPC converter. Section III discusses the phaseshifted carrier based modulation technique and the mathematical model of the DC-link capacitors voltage behavior. Section IV provides simulation results and Section V presents experimental results from a single-phase low-power sevenlevel laboratory setup. Finally, the conclusions are summarized in Section VI. II. TOPOLOGY AND OPERATION PRINCIPLES Fig. (a) presents the phase leg of the n-level (FC) based ANPC converter topology. It is the arrangement of a 3L-ANPC converter and z number of two-level cells. The number of output voltage levels in the line-to-neutral waveform is equal to n =z +3 where n is an odd number. The n-level FC //$6. IEEE 553

4 + idc i ic C i O (n-) Vdc ic C - i + (n-) Vdc O O (n-) Vdc - Sx5 Basic two-level cell z capacitor cells Sx6 Sx3 Sxy(n-4) Sxy(n-6) Sxy5 Sxy3 Sxy v rx Cf, xy(n-4) Cf,xy(n-6) Cf,xy5 Cf,xy3 Cf,xy i rx Sx7 Sx4 Sxy(n-3) Sy(n-5) Sxy6 Sxy4 Sxy Sx8 (a) Sx3 Sxy(n-4) Sxy(n-6) Sxy5 Sxy3 Sxy v rx C Cf, xy(n-4) Cf,xy(n-6) Cf,xy5 Cf,xy3 Cf,xy i rx Sx4 Sxy(n-3) Sy(n-5) Sxy6 Sxy4 Sxy Sx3 Sxy(n-4) Sxy(n-6) Sxy5 Sxy3 Sxy v rx C Cf,xy5 Cf,xy3 Cf,xy Cf, xy(n-4) Cf,xy(n-6) i rx Sx4 Sxy(n-3) Sy(n-5) Sxy6 Sxy4 Sxy (c) ANPC converter and the two switching states of each of the two-level cells resulting in a total of 4 z switching states which generate the n different voltage levels at the output. The output phase voltage, v rxo, where x is the phase (a, b or c)is given by: v rxo = [ ] (n ) V dc (S x5 ) + (S x3 + S xy(n 4) S xy ) () The voltage ripple across the FC depends on the amplitude of the load current and the switching frequency of the switches S x3, S x4 and the switches of two-level cells []. The current through the FC C f,xy(n 6) can then be expressed as: i Cf,xy(n 6) =(S xy(n 4) S xy(n 6) ) i rx () The required capacitance of the flying capacitor for a peak output current of I p allowed voltage ripple ΔV Cf and carrier frequency of f s is given by eq. 3 [9]. Fig.. n-level FC based ANPC converter, (a) phase leg, Circuit during first half-period, (c) circuit during second half-period based ANPC converter consists of n +3 switches and n 3 FCs. If the voltage across the DC-link is assumed constant and equal to (n )V dc, where V dc is the voltage across the first FC C f,y, the voltage across each of the two dc-link capacitors is equal to (n ) V dc. Switches S x5, S x6, S x7 and S x8 (outer switches) have to be rated for a voltage equal to (n ) V dc. The requirement for higher voltage ratings of these switches can be a limiting factor to the potential expansion of the topology to large number of levels and higher voltage applications. Switches S x3 and S x4 and the switches of the two-level cells have to withstand a voltage equal to V dc. Each of the two-level cells consists of a FC and a complementary switch pair. If the voltage across the FC is assumed constant then the voltage across the last flying capacitor C f,xy(n 4) is equal to (n 3) V dc and the voltage across the first FC C f,xy is equal to V dc. Since the outer switches operate under fundamental frequency, two distinct half-periods can be identified. In the first half-period the FC circuit is connected to the upper capacitor (C ) of the DC-link as shown in Fig. and during the second half of the period the capacitor is connected to the lower capacitor (C ) (Fig. (c)). The converter is then essentially reduced to an (n + )/ level FC and analytical determination of the voltage balancing of the flying capacitors can be applied [3]. In a three-phase application the complexity of this analysis increases, since more than one of the phase-legs can be connected to one of the DC capacitors. The 3L-ANPC converter has six switching states. In order to decrease the switching frequency of switches S x5 and S x8, only four out of the six switching states are considered. The switching states of the n-level FC based ANPC converter are the combination of the four switching states of the three-level C f = I p (3) ΔV Cf f s The energy stored per phase-leg of the n-level FC based ANPC converter is also presented in [8]. As the number of levels increases, the energy stored in the flying capacitors increases linearly. In order to decrease the energy stored in the FCs as the number of levels increase, a higher switching frequency can be utilized. This, however, increases the switching losses and a trade off between the switching losses and the energy storage of the capacitors has to be made. III. PHASE-SHIFTED CARRIER PWM A. Modulation Strategy The modulation of the n-level FC based ANPC converter is based on a PSC PWM. The PSC-PWM provides natural balancing of the FC converters [3] and can be readily applied to the topology under discussion. Since additional number of levels can be acquired by the fundamental frequency switching of the 3L-ANPC, only n triangular carrier signals are required. The phase shift between these triangular carrier signals is 7 n degrees, or double the phase shift for an equal level FC or CHB topology. The harmonics are positioned as sidebands around (n )fs. This modulation technique fulfills the two basic requirements set in [8] as the voltage balancing of the flying capacitors is provided by the PSC-PWM and the switching frequency of the outer switches of the topology is equal to the fundamental frequency of the output voltage. The modulating signal for the converter is a function of both the desired output voltage and the switching function of the switch S x5 [9] and is given by eqn. (4). v rx = m a sin(ω t) ( 4 π n=,3,5... n sin nω t) (4) where m a is the amplitude modulation index and ω is the angular frequency of the fundamental component. The 554

5 p.u. output frequency. The continuous switching functions for switches of phase a are - p.u Time (sec) Fig.. Modulating signal and triangular carrier of the PSC-PWM ˆS a3 =+m a sin(ω t) + 4 π n=,3... n sin(nω t) ˆS a4 = m a sin(ω t) + 4 π n=,3... n sin(nω t) ω t π (4) ω t π (5) modulating signal and a triangular carrier waveform are shown in Fig.. The value of m a is normalized with the overall number of levels and it ranges between and for any n. The number of levels in the output voltage waveform also depends on the amplitude modulation index and for every n decrease in m a, the number of levels in the output waveform decreases by two. B. Mathematical modeling of the DC-link capacitor voltage behavior for three-phase converter arrangement The analysis of the DC-link capacitor voltage behavior for the n-level FC based ANPC converter using PSC-PWM is discussed in this section. The switching functions of the switches, determine the relation between the AC- and DC-side variables. Voltages of the AC-side of the ANPC converter are given by eq. (): [ ] v rao = V (n ) dc (S a5 ) + (S a S ay ) (5) [ ] v rbo = V (n ) dc (S b5 ) + (S b S by ) (6) [ ] v rco = V (n ) dc (S c5 ) + (S c S cy ) (7) Considering the AC-side three-phase currents as: i a (t) =I p sin(ω t + φ) (8) i b (t) =I p sin(ω t + φ π 3 ) (9) i c (t) =I p sin(ω t + φ + π 3 ) () The currents of the DC-side of the converter are given by i = i a S a5 S a3 + i a S b5 S b3 + i a S c5 S c3 () i = i a (S a5 + S a3 ( S a5 )) + i b (S b5 + S b3 ( S b5 )) + i c (S c5 + S c3 ( S c5 )) () i = i a S a8 S a4 + i a S b8 S b4 + i a S c8 S c4 (3) At any given time, the switching function can be approximated by the instantaneous value of the modulating waveform, given that carrier frequency is much larger than converter ˆS a5 = ˆS a6 = { + 4 π n=,3... n sin(nωt) ω t π π ω t π { ω t π + 4 π n=,3... n sin(nωt) π ω t π (6) (7) Thus the average value of current i over one cycle of modulating waveform is given as i = π π (i a S a5 S a3 +i b S b5 S b3 +i c S c5 S c3 )d(ω t) (8) i = 3m ai p cos(φ) 4 Similarly from the integration of eqn. () and from eqn. (3) i = π π (9) i = () (i a S a8 S a4 +i b S b8 S b4 +i c S c8 S c4 )d(ω t) () i = 3m ai p cos(φ) () 4 Considering the power balance equation between the DC and the AC-side of the n-level ANPC converter, the following are obtained V dc i dc = π π (v ra i a + v rb i a + v rc i c )d(ω t) (3) i dc = 3mI p cos φ 4 (4) i dc is the average value of i dc over one cycle of the modulating waveform. Using the above deduced equations the following are obtained i C = i dc i = (5) i C = i C i = (6) When the voltage across the capacitors naturally balances using PSC-PWM, the average value of the DC-link capacitors current and neutral point current is zero. 555

6 + S 5 TABLE I SWITCHING STATES OF SEVEN-LEVEL FC BASED ANPC CONVERTER C v rx 6 V dc O C f,y3 C f,y i r - C Fig. 3. S 6 S 7 S 8 S 3 S 4 S y3 S y4 S y S y Seven level FC based ANPC converter IV. SIMULATION RESULTS Simulations have been performed based on a seven-level topology (Fig. 3). In this case, charging and discharging of the two flying capacitors C f,y3 and C f,y takes place at p.u and p.u of the output line-to-neutral voltage and depends upon the direction of the output phase current. The switching states for the case of the seven-level topology are shown in Table I. During the switching states V, V 7, V and V 4 both the FCs are connected to the load and one of the capacitors charges while the other discharges. In the remaining states that provide p.u. or p.u. voltage levels, only one of the two FCs is connected to the output. Also during switching states, V 7 and V 4 the neutral point O is connected to the load through the FCs. The switching signals and the intervals where either or both the FCs are connected to the load during a fundamental period are shown in Fig. 4. The system parameters and load configurations for both the simulation and experimental results are summarized in Table II. The behavior of the topology and especially the voltage balancing of the flying capacitors is investigated not only under steady-state operation but also during changes in the DC voltage. Fig. 5 shows the phase output voltage and the voltage across the flying and DClink capacitors and Fig. 6 shows the load current and current through the flying capacitors of the seven-level topology. The dynamic behavior of the converter for a step change in the DC-link voltage is also simulated for the two possible arrangements of the triangular carrier waveforms (leading and lagging). The simulated results are shown in Fig. 7(a) and for leading and lagging arrangements respectively. As expected the leading carrier arrangement results in a faster response from capacitor C f,y and the lagging carrier arrangement results in an initial dip in the voltage of capacitor C f,y and a faster response to the transient change from capacitor C f,y3. These results are in accordance with the behavior of a flying capacitor converter under similar changes in the DC-link voltage [3]. S 3 S 4 S 5 S 6 S 7 S 8 S y S y S y3 S y4 V V V 3 V 4 V 5 V 6 V 7 V 8 V 9 V V V V 3 V 4 V 5 V 6 Switching Signals Voltage (p.u) S5 Sy3.5.5 Sy.5.5 v aro S Time (sec) Fig. 4. Seven-level FC based ANPC converter, (a)-(d) Switching signals, (e) Output voltage and charging periods TABLE II SIMULATION AND CIRCUIT PARAMETERS DC-link voltage DC-link capacitors C and C Flying capacitors Carrier Frequency Fundamental Frequency Load Resistance Load Inductance 3V 47μF μf 5Hz 5 Hz Ω 7mH V. EXPERIMENTAL RESULTS A single-phase laboratory prototype of a seven-level FC based ANPC converter was used to verify the natural balancing (a) (c) (d) (e) 556

7 (a) (c) (d) v ro C f, y3 C f, y V C V C Time (s) Fig. 5. Simulation results, (a) Output phase voltage, Capacitor C f,y3 voltage (c) Capacitor C f,y voltage (d) DC-link capacitors voltage (a) (c) Current (A) Current (A) Current (A) i rx i Cf,y3 i Cf,y Time (s) Fig. 6. Simulation results, (a) load current Capacitor C f,y3 current (c) Capacitor C f,y current phenomenon of the FCs using PSC-PWM. The converter is built using the FUJI MBITA-6 and a dspace 4 R&D DSP board. The laboratory setup employed a controllable DC-supply attained from a three-phase passive front end rectifier and a transformer to maintain the DC-link voltage The steady state performance of the topology is initially investigated. Fig. 8 shows the line-to-neutral phase output of and the corresponding harmonic spectrum of the singlephase circuit for an amplitude modulation index of.85. The measured load current and currents through the two flying capacitors are also shown in Fig. 9. Finally, Fig. shows the DC-link voltage and the voltage of the flying capacitors over v Cf,y Time (s) (a) v Cf,y v Cf,y v Cf,y Time (s) Fig. 7. Simulated response to a DC-link voltage step change (a) leading arrangement, lagging arrangement fundamental periods (.4 sec). The natural balancing of the flying capacitors due to the PSC-PWM method and their corresponding voltage ripple due to the load current can also be observed. The behavior of the single-phase circuit under a step change in the DC-link voltage of V (i.e. from V to 3V) is also investigated for both leading and lagging carrier waveforms. The transient responses for the case of the leading and lagging carrier arrangement are shown in Figs. and respectively. Due to the PSC-PWM of the flying cells of the topology and the fundamental frequency switching of the outer switches, which result in a circuit as shown in Fig. and (c), the transient behavior of the topology for both carrier arrangements is similar to that of a FC converter. The experimental results appear to be over-damped when compared to the simulation results possibly because of the non-linear nature of the load inductance for the specific current range and the variation of the load resistance with frequency. VI. CONCLUSION The topology, operational principles and theoretical considerations of a generalized n-level flying capacitor based, active neutral-point clamped converter has been discussed in this paper. The converter is operated with PSC-PWM providing fundamental frequency switching of the outer switches and voltage balancing of the flying capacitors through the natural balancing property. Simulations results and closely matched experimental results are also provided that verify the operational principles of the topology. REFERENCES [] J. Rodriguez, L.G. Franquelo, S. Kouro, J.I. Leon, R. Portillo, M. Prats, M. Perez, Multilevel converters: An enabling technology for high-power 557

8 Fig. 8. Measured output phase voltage and corresponding harmonic spectrum Fig.. Dynamic response to a V step change in the DC-link voltage, leading carrier arrangement Fig.. Dynamic response to a V step change in the DC-link voltage, lagging carrier arrangement Fig. 9. Measured load and floating capacitor currents Fig.. Measured DC-Link and flying capacitor voltages and flying capacitor voltage ripple applications in Proc. of the IEEE, Vol. 97, No., Nov. 9, pp [] M. F. Escalante, J. Vannier and A. Arzande, Flying capacitor multilevel inverters and DTC motor drive applications, in IEEE Trans. on Ind. Electron., vol. 49, no. 4, pp , Aug.. [3] H. Akagi, H. Fujita, S. Yonetani, and Y. Kondo, A 6.6kV transformerless STATCOM based on a five-level diode-clamped PWM converter: System design and experimentation of a -V -kva laboratory model, in IEEE Trans. on Ind. Appl., vol. 44, no., pp , Mar./Apr. 8. [4] N. Flourentzou V. G. Agelidis and G. Demetriades, VSC based HVDC power transmission systems: An overview, in IEEE Trans. on Power Electr., vol. 4, no. 3, pp. 59-6, 9. [5] M. Veenstra and A. Rufer, Control of a hybrid asymmetric multilevel inverter for competitive medium-voltage industrial drives, IEEE Trans. on Ind. Appl., vol. 4, no., pp , Mar./Apr. 5. [6] T. Bruckner, S. Bernet, and P. Steimer, Feedforward loss control of threelevel Active NPC converters, IEEE Trans. on Ind. Appl., vol. 43, no. 6, pp , Dec. 7. [7] F. Kieferndorf, M. Basler, L. A. Serpa, J. -H. Fabian, A. Coccia, and G. A. Scheuer, A new medium votlage drive system based on ANPC-5L technology, in Proc. of ICIT Conf., pp [8] P. Barbosa, P. K. Steimer, M. Winkelnkemper, J. Steinke, and N. Celanovic, Active-neutral-point clamped (ANPC) multilevel converter technology, in Proc. of EPE Conf. 5, pp.-4. [9] S. A. Gonzalez, M. I. Valla and C.F. Christiansen, Five-level cascaded asymmetric multilevel converter, in IET Power Electr., vol. 3, no., pp. -8,. [] M. Winkelnkemper, F. Wilder, and P. K. Steimer, Control of a 6 MVA hybrid converter for permanent magnet synchronous generator for windpower, in Proc. of IEEE Elect. Mach. Conf, (ICEM), Vilamoura, Portugal, 8, pp.-6. [] J.Meili, S. Ponnaluri, L. Serpa, P. K. Steimer, and J. W. Kolar, Optimized pulse patterns for the 5-level ANPC converter for high speed high power applications, in Proc. of IEEE IECON, 6, pp [] S. R. Pulikanti and V. G. Agelidis, Control of neutral point and flying capacitor voltages in five-level SHE-PWM controlled ANPC converter, in Proc. of IEEE Ind. Electron. Appl. Conf, (ICIEA), 9, pp [3] B.P. McGrath and D.G. Holmes, Analytical modeling of voltage balance dynamics for a flying capacitor multilevel converter, in IEEE Trans. on Power Electron., Vol. 3, No, Mar. 8, pp