MULTILEVEL converters provide significant advantages

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1 4794 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 11, NOVEMBER 2013 Hybrid Seven-Level Cascaded Active Neutral-Point-Clamped-Based Multilevel Converter Under SHE-PWM Sridhar R. Pulikanti, Member, IEEE, Georgios Konstantinou, Graduate Student Member, IEEE, and Vassilios G. Agelidis, Senior Member, IEEE Abstract This paper presents the hybrid seven-level cascaded active neutral-point-clamped (ANPC)-based multilevel converter. The converter topology is the cascaded connection of a three-level ANPC converter and an H-bridge per phase. The voltage of the H-bridge is actively maintained to the required level through selection of the switching states of the converter. The topology is operated under selective harmonic elimination pulsewidth modulation (SHE-PWM), maintaining the switching frequency of the converter to a minimum. The operating principles, voltage balancing methods, and limitations of the converter are analyzed together with extensive simulation results of the topology. Experimental results from a low-power laboratory prototype are presented that verify the operation of the hybrid converter under SHE-PWM. Index Terms Active neutral-point-clamped (ANPC) converter, hybrid converter, selective harmonic elimination pulsewidth modulation (SHE-PWM), voltage balancing. I. INTRODUCTION MULTILEVEL converters provide significant advantages over the typical two-level converters such as improved output waveforms with lower harmonic distortion, lower electromagnetic interference, reduced stress across the semiconductor switching devices, and fault-tolerant operation [1]. However, the increase in the number of levels comes at the cost of increased complexity of the topology and increased component count, including switches, capacitors, and isolated dc sources. An increase in the number of levels further complicates the implementation, requiring voltage balancing of capacitor and neutral point voltages [2], [3]. The three-level neutral-point-clamped (NPC)-based converters are the most widely used in industrial applications [4]. The three-level active NPC (3L-ANPC) can deal with the Manuscript received August 5, 2011; revised November 15, 2011, December 11, 2011, and May 9, 2012; accepted August 14, Date of publication September 12, 2012; date of current version June 6, S. R. Pulikanti is with the University of Wollongong, Wollongong, N.S.W. 2522, Australia ( sridhar@uow.edu.au). G. Konstantinou and V. G. Agelidis are with the Australian Energy Research Institute and the School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, N.S.W. 2052, Australia ( g.konstantinou@unsw.edu.au; vassilios.agelidis@unsw.edu.au). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TIE uneven distribution of semiconductor losses inherent to the NPC converter [5]. The active switches provide redundancies in the zero-voltage level switching states that can be selected through the appropriate modulation process. These properties make it a particularly attractive topology in applications such as motor drives [5], [6], advanced static compensators [7], HVdc transmission [8], and grid-connected photovoltaic systems [9]. In order to eliminate the need for individual dc sources for every converter stage and extend the number of levels of the conventional multilevel inverters, hybrid cascaded converter topologies with H-bridge cells have been proposed. A topology based on the cascaded interconnection of a two-level inverter with individual H-bridge cells for each phase was presented in [10] [13]. An asymmetrical converter based on the cascaded connection of the three-level NPC converter and H-bridge cell for medium drive applications using model predictive control was also proposed in [3]. A carrier-based pulsewidthmodulation (PWM) control was implemented in [14] and [15] to control the voltage across the flying capacitors (FCs) in a cascaded connection of the three-level NPC converter and H-bridge cells. This converter only requires a single dc source for all the three phases. The cascaded connection of the threelevel NPC converter and H-bridge cell was proposed for current waveform conditioning in [16] and [17]. Other arrangements of hybrid multilevel converters include the 3L-ANPC converter with an H-bridge cell [18] (Fig. 1), the four-level ANPC converter with a stacked multicell converter [19], the 3L-ANPC converter with a two-level cell [20] [23] which is known as five-level ANPC converter, and power electronic building block with five-level ANPC converter [24]. For a given switching frequency, selective harmonic elimination PWM (SHE-PWM) offers the potential for improved waveform quality compared to other existing modulation techniques (sinusoidal and space vector PWM). This potential becomes advantageous for applications where low switching frequency is required. The 3L-ANPC converter under SHE-PWM has been studied in [25], while the extension of the method to the five-level FC-based ANPC converter was presented in [26]. Hybrid multilevel converters are derived from various combinations of similar or different converter topologies. The objective of this paper is to discuss the operation of a multilevel converter based on the cascaded interconnection of a 3L-ANPC converter and individual H-bridges for each phase. The configuration of the circuit is shown in Fig. 1. In this /$ IEEE

2 PULIKANTI et al.: HYBRID SEVEN-LEVEL CASCADED ANPC-BASED MULTILEVEL CONVERTER UNDER SHE-PWM 4795 TABLE I SWITCHING STATES OF THE SEVEN-LEVEL HYBRID ANPC-BASED CASCADED CONVERTER Fig. 1. Circuit configuration of the hybrid seven-level ANPC-based multilevel converter. paper, the hybrid seven-level cascaded ANPC-based multilevel converter operational principles are utilized in order to regulate the voltage across the H-bridge floating capacitor under SHE- PWM. The effects and limitations in the voltage regulation of the floating capacitor for various loads and modulation indices under SHE-PWM are also analyzed. Moreover, the extension of the modulation index range, where the charging and discharging periods of FC are varied to enhance the voltage regulation of FC, is considered. This paper is organized as follows. The operational principles of the seven-level cascaded ANPC-based multilevel converter are presented in Section II, and in Section III, the seven-level harmonic elimination PWM is analyzed. The control strategy to regulate the voltages of the FC is discussed in Section IV. Simulation results and experimental validation through a lowpower laboratory prototype are given in Sections V and VI, respectively. Finally, Section VII summarizes this paper. TABLE II EFFECT ON FC DURING DIFFERENT SWITCHING STATES II. OPERATIONAL PRINCIPLES The cascaded ANPC-based multilevel converter is an arrangement of a 3L-ANPC converter stage and an H-bridge stage which are connected in series as shown in Fig. 1. The dc link consists of capacitors C 1 and C 2 providing the midpoint required for the 3L-ANPC converter. Considering a dc-link voltage of 4V dc, each dc-link capacitor voltage is maintained to an average of 2V dc, and the voltage of the H-bridge submodule capacitor (C f ) is maintained at a voltage equal to V dc.the active switches (S 5 and S 6 ) of the ANPC converter clamped to the neutral point ensure the equal voltage sharing between the main switches (S 1 S 4 ) and also create additional zero-voltagelevel switching states. These redundant switching states can be utilized in order to distribute the semiconductor losses of the 3L-ANPC converter. The converter has 20 four switching states as shown in Table I. These switching states generate the seven different voltage levels, namely, 3V dc, 2V dc, V dc,0, V dc, 2V dc, and 3V dc. The switching states are the combination of the six switching states provided by the 3L-ANPC converter and the four switching states of the H-bridge submodule. The voltage across the capacitor of the H-bridge submodule is affected when it is connected to the output terminal and one of the dc-link terminals (positive dc rail, neutral point (O), negative dc rail of Fig. 1). This occurs when the output phase voltage (V ro ) is equal to ±V dc and ±3V dc. The voltage levels of ±3V dc are generated by V 1 and V 24 (Table I), respectively. Since these voltage levels can be acquired by only one switching state and there are no redundant states, the change in the voltage across the H-bridge submodule capacitor is determined only by the direction of the output phase current. Regulation of the submodule voltage to its reference voltage level of V dc is done through utilization of the redundant switching states that generate ±V dc. During these switching states (V 5, V 8, V 9, V 12, V 13, V 16, V 17, and V 20 ), the neutral point (O) is connected to the output through the floating capacitor which influences the neutral point voltage of the converter. The effect of the switching states and the current direction on the deviation of the H-bridge submodule capacitor voltage is summarized in Table II.

3 4796 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 11, NOVEMBER 2013 III. MULTILEVEL SHE-PWM A multilevel SHE-PWM strategy is considered, assuming both quarter- and half-wave symmetries. The formulation of the SHE-PWM problem and acquisition of solutions for seven-level waveforms has been analyzed in [27]. The equations describing the seven-level SHE-PWM are given in (1) for the fundamental frequency component and in (2) for the higher order harmonics N 1 i=1 ( 1) i+1 cos(α i )+ N 1 +N 2 i=n 1 +1 ( 1) i cos(α i ) Fig. 2. SHE-PWM solution trajectories. (a) Three angles per quarter wave. (b) Four angles per quarter wave. N 1 i=1 + ( 1) i+1 cos(nα i )+ N i=n 1 +N 2 +1 N 1 +N 2 i=n 1 +1 ( 1) i+1 cos(α i )=M (1) ( 1) i cos(nα i ) + N i=n 1 +N 2 +1 ( 1) i+1 cos(nα i )=0 (2) where N 1 is the number of switchings between the zero and the first level, N 2 is the number of switchings between the first and the second levels, N 3 is the number of switchings between the second and the third levels in the quarter period of the waveform, M is the modulation index, and α i is the ith switching within the quarter period of the waveform. The additional restrictions imposed are 0 M 3 (3) 0 <α 1 <α 2 < <α N < π (4) 2 and the amplitude of the fundamental component is ˆV 1 = 4 M V dc. (5) π A. Fundamental Frequency Switching The fundamental switching frequency modulation (i.e., stepped voltage output waveform) is initially considered. Here, three angles per quarter period are considered (N 1 /N 2 /N 3 = 1/1/1) which provide control over the fundamental frequency component and elimination of the first two odd and nontriplen harmonics from the output waveform (i.e., fifth and seventh). The two available solutions are shown in Fig. 2(a). In order to increase the maximum modulation index attainable by the PWM waveform and increase the charging period while decreasing the discharging period during the top and bottom levels (V 1 and V 24 ), an additional switching transition is considered between the second and third levels (N 3 =2). This additional switching is calculated by considering the formulation of the multilevel SHE-PWM in order to provide elimination of one additional harmonic. The solution patterns of this formulation are given in Fig. 2(b) [18]. Fig. 3. (a) Seven-level waveform. (b) Modified waveform by injection of a third harmonic frequency square wave. B. Triple Harmonic Injection Alternatively, the additional transition in the top level can be calculated through the injection of a triplen harmonic square wave [28]. The square wave is defined by (6) and modifies the switching angles of Fig. 3 so that the duration of the top level of the waveform is reduced. Additionally, it exhibits quarterwave symmetry so as not to affect the properties of the output waveform 2V dc V triple (θ) = nπ cos(nα 3)sin(3nθ). (6) n=1,3,5,... The injection of the square waveform of (6) modifies the seven-level waveform, as shown in Fig. 3. The switching angles in the waveform are redefined as shown in Fig. 3(b) with the first transition moving from α 1 to (α 3 π/3) and the two transitions on the top level defined by angles α 2 and (2π/3 α 3 ). In order to maintain the full seven levels in the waveform, the limits in this method are that the first and last angles in the seven-level waveform should be greater than 30 and 60, respectively (α 1 π/6 and α 3 π/3). The harmonic injection is again based on angle calculation, and its implementation is identical to the implementation of SHE-PWM with four angles per quarter period and the two additional angles calculated offline through the corresponding formulas. The drawback of this method is that the additional switching in the top level is not optimally calculated in order to eliminate an additional harmonic. C. Multiple Switchings per Quarter Period Finally, a modulated multilevel waveform with N = 11 angles per quarter period and a distribution ratio of

4 PULIKANTI et al.: HYBRID SEVEN-LEVEL CASCADED ANPC-BASED MULTILEVEL CONVERTER UNDER SHE-PWM 4797 Fig. 4. SHE-PWM solution trajectories. (a) Eleven angles per quarter wave (3/5/3). (b) Twelve angles per quarter wave (3/5/4). Fig. 6. H-bridge submodule capacitor voltage control diagram. TABLE III SELECTION OF SWITCHING FUNCTIONS and can be selected based on the requirements of a specific application [27]. Fig. 5. Switching patterns for voltage regulation of the H-bridge capacitor. (a) SF 1.(b)SF 2. N 1 /N 2 /N 3 =3/5/3 is analyzed. Here, the first ten odd nontriplen harmonics are eliminated while controlling the fundamental frequency component to the required level. An additional switching angle is also considered (N = 12) in order to improve the continuity and the range of solutions. For 12 angles, a distribution of 3/5/4 to the three levels of the waveform is considered (Fig. 4). The selection of both the number of transitions N and the distribution ratios is not limited IV. H-BRIDGE SUBMODULE CAPACITOR VOLTAGE CONTROL The regulation of the voltage of the H-bridge submodule capacitor can be performed when the output phase voltage is equal to ±V dc and depends upon the polarity of the output phase current and the selection of the corresponding switching state. Detailed description of the control of the floating capacitor voltage is given in [18] with the two possible switching patterns shown in Fig. 5. The block diagram of the voltage controller is shown in Fig. 6. The measured voltage across the H-bridge capacitor is compared in a hysteresis comparator (S cf ). The selection of the hysteresis band defines the switching frequency variation and is analyzed in the following sections. Additional information required is the polarity of the output phase current that determines the status (S I ) and the polarity of the output phase voltage that determines the voltage status (S V ). Based on these inputs, the switching pattern is selected in order to regulate the capacitor voltage to the reference value. The selection of switching functions based on S cf, S I, and S V is summarized in Table III.

5 4798 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 11, NOVEMBER 2013 A. Calculation of the Floating Capacitor Voltage Ripple The variation of the voltage in the capacitor of the H-bridge is given by ΔV = i Δt. (7) C Considering a load impedance equal to Z, the current in the output is given by i = 4 πz MV dc sin ωt (8) and the voltage variation of (7) can be rewritten as ΔV = 4M πc Z V dc sin(ωt φ)δt (9) Fig. 7. Effect of band selection in the switching frequency [(h 1 ) tight band and (h 3 ) loose band]. where Δt is the time duration between two switchings in the SHE-PWM waveform. Δt is defined by the selection of the switching pattern and, additionally, is a function of the operating point as given by the modulation index M. As the voltage reference for the floating capacitor of the H-bridge is equal to V dc, the normalized voltage ripple can be calculated by ΔV = 4 sin(ωt φ)mδt(m). (10) V dc πc Z For a given load, the variation of the voltage is a function of the displacement angle and the operating point. As the switching patterns in multilevel SHE-PWM are nonlinear functions, closed-form solution for the maximum capacitor voltage ripple cannot be mathematically derived, but (10) needs to be numerically evaluated for each particular solution. B. Effect of Hysteresis Band on Switching Frequency The bands of the hysteresis controller define the limits of the voltage ripple across the floating capacitor and affect the switching frequency of the converter as it changes between patterns SF 1 and SF 2 in order to regulate the voltage within the limits. Selection of tight limits in the bands results in an unreasonably high switching frequency, while selection of loose bands results in high-voltage ripple and subpar harmonic performance from the converter as shown in Fig. 7. The effect of the band selection is shown in Fig. 8 for different operating points of the converter with fundamental switching frequency (three angles per quarter period) and for different selection of the hysteresis band limits. The maximum deviation of the floating capacitor voltage is additionally dependent on the load of the converter and can be calculated from (10). As switching losses are proportional to the switching frequency [29], operation under tight hysteresis bands results in significant switching losses for the converter, decreasing its overall efficiency. The H-bridge experiences higher switching frequency than the ANPC converter but requires lower rated switches (2 : 1 ratio for the seven-level converter) due to the lower dc voltage in the converter. The unequal switching within the H-bridge is due to the suboptimal distribution of the zero- Fig. 8. Number of switching instances versus hysteresis band selection for various operating points of the converter, normalized to the overall highest switching frequency. (a) M =1.5. (b)m =1.7. (c)m =1.85. voltage states, and an additional logic for the selection of the states can be implemented to alleviate this issue. C. Limits of Operation As described in Section IV, the redundant switching states of V ro = ±1 p.u. are utilized to regulate the voltages of the

6 PULIKANTI et al.: HYBRID SEVEN-LEVEL CASCADED ANPC-BASED MULTILEVEL CONVERTER UNDER SHE-PWM 4799 Fig. 10. Limits of floating capacitor voltage regulation with four angles per quarter period. (a) Set 1. (b) Set 2. (c) Set 3. TABLE IV SIMULATION AND EXPERIMENTAL PARAMETERS Fig. 9. Limits of floating capacitor voltage regulation with three angles per quarter period. (a) Set 1. (b) Set 2. H-bridge submodule capacitor, while the voltages are also affected by the ±3-p.u. levels. The charging and discharging periods are shown in Fig. 5(a). The voltage across the capacitors can therefore be maintained to the required voltage level if the overall amount of charge is at least equal to the discharge amount of the FC over a fundamental period. Since the only states that can be used for the regulation of the voltages are those of the ±1-p.u. voltage level, the condition can be simplified by analyzing the waveforms over the half period. The voltage balancing condition is given by π 0 I charging dθ π 0 I discharging dθ > 0 (11) where I charging is the part of the output phase current charging the FC and I discharging is the part of the output phase current discharging the flying capacitor. Based on (11), the operating point of the converter defines the duration of the charging and discharging intervals, while the displacement angle of the load current should also be considered. The calculation of the integrals of (11) can be done for the two previous parameters in order to estimate the limits of operation of the converter. When the total charge during the +V dc interval of the first half period is greater than the discharge in the +3V dc interval, the regulation of the voltage is possible. Fig. 9(a) and (b) shows the evaluation of (11) for the two sets of solutions when three angles are considered in the waveform. Similarly, Fig. 10 shows the evaluation of the three solutions (Fig. 2) for four angles per quarter period of the waveform. Similar calculations with the operating point and displacement angle of the load as parameters can be derived for the operation of the converter under multilevel SHE-PWM with multiple angles per level of the waveform and determine the limits of operation of the topology. Solution patterns that provide significantly larger areas of operation with a positive charge provide regulation of the H-bridge floating capacitor for more operating points and are preferable for converters that operate with a large variety of loads. For a given operating point, or converters operating within a limited range of modulation index and loads, solution patterns that provide curves with larger total charge are preferable, as the floating capacitor voltage can be regulated. V. S IMULATION RESULTS The seven-level hybrid cascaded ANPC-based converter under SHE-PWM is simulated in MATLAB/SIMULINK for the cases presented in Section III. The parameters used in the simulations match those of the laboratory prototype and are summarized in Table IV. A dc source is connected across each of the dc-link capacitors of the converter. A. Fundamental Switching Frequency The fundamental switching frequency considers the staircase seven-level waveform and its extension to four switching angles per quarter period. The solution trajectories for these cases are shown in Fig. 2. For the case of fundamental switching frequency, two sets of solutions are available. As the charging and discharging periods of the H-bridge submodule capacitors depend on the switching angles and the displacement power factor of the load, the voltage of the capacitors cannot be regulated at its reference level for the whole range of available solutions for any given

7 4800 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 11, NOVEMBER 2013 Fig. 11. Simulation results for N =3 and M =1.85 for Load A. (a) Output phase voltage. (b) 3L-ANPC voltage. (c) H-bridge voltage. (d) H-bridge capacitor voltage. (e) Output phase current. Fig. 13. Simulation results for N =11 and M =1.77 for Load B. (a) Output phase voltage. (b) 3L-ANPC voltage. (c) H-bridge voltage. (d) H-bridge capacitor voltage. (e) Output phase current. Additional results for the fundamental frequency modulation and both the cases of four angles per quarter period and third harmonic injection are given in [18]. Fig. 12. Harmonic spectrum of output phase voltage of Fig. 11(a). load. Depending on the displacement power factor of the load, the voltage can be regulated for the whole range of solutions for Set 2 (Fig. 2) and is increasing from 1.48 to 2.48 for Set 1 as the displacement power factor decreases and the load becomes highly inductive. The simulation results for a modulation index of M =1.85 from Set 2 and load A (Table IV) are shown in Fig. 11. Fig. 11(a) shows the output phase voltage (v ro ), while Fig. 11(b) and (c) shows the voltages of the 3L-ANPC output voltage (v wo ) and H-bridge output voltage (v rw ), respectively. As the two switching functions are selected to regulate the voltage of the H-bridge capacitor, the switching waveforms of both the modules (3L-ANPC and H-bridge) are asymmetrical over consecutive periods of operation. The band limits of the hysteresis comparator to which the H-bridge submodule capacitor is regulated are considered to be ±0.5 V of the reference value (5%). The voltage of the H-bridge capacitor, shown in Fig. 11(d), is regulated at the reference voltage level within the band limits. Fig. 11(e) shows the output phase current, and the harmonic spectrum of the output phase voltage (Fig. 11) is shown in Fig. 12. The first two nontriplen harmonics (i.e., fifth and seventh) are eliminated from v ro. B. Multiple Switchings per Quarter Period In order to improve the harmonic performance of the converter and minimize the output filter requirements, additional switchings per period are investigated. Here, 11 and 12 switching angles per quarter period with distribution ratios of 3/5/3 and 3/5/4, respectively, are considered. The solutions obtained for these switching angles and distribution ratios are shown in Fig. 4. Similar to the case of fundamental switching frequency, the voltage regulation depends on the load connected to the output. For the 11 angles, 3/5/3 distribution, the voltage can be regulated up to a modulation index of M =2.29. The simulation results for M =1.77 are shown in Fig. 13. The band limits of the hysteresis comparator are considered to be 0.8 V from the reference value (8%). The harmonic spectrum of the phase voltage is shown in Fig. 14 with the first noneliminated nontriplen harmonic being the 35th. For 12 angles per quarter period and distribution ratio of 3/5/4, voltage regulation was possible for modulation indices up to M =2.16. The simulation results for M =1.97 are shown in Fig. 15. The harmonic spectrum of the output voltage is shown in Fig. 16 with the first noneliminated nontriplen harmonic being the 37th. VI. EXPERIMENTAL RESULTS The operation of the multilevel converter under discussion is validated through a low-power laboratory setup and implemented using a dspace DS1104 board.

8 PULIKANTI et al.: HYBRID SEVEN-LEVEL CASCADED ANPC-BASED MULTILEVEL CONVERTER UNDER SHE-PWM 4801 Fig. 14. Harmonic spectrum of output phase voltage of Fig. 13(a). Fig. 17. Experimental results for N =3, M =1.85, and Load A. Output phase voltage and corresponding harmonic spectrum. Traces: Channel 4 (50 V/div) and FFT (10 V/div). Fig. 15. Simulation results for N =11 and M =1.97 for Load B. (a) Output phase voltage. (b) 3L-ANPC voltage. (c) H-bridge voltage. (d) H-bridge capacitor voltage. (e) Output phase current. Fig. 18. Experimental results for N =3, M =1.85, and Load A. (a) Output phase and 3L-ANPC voltages. Traces: Channels 2 and 4 (50 V/div). (b) H-bridge output voltage. Trace: Channel 2 (20 V/div). (c) H-bridge capacitor voltage. Trace: Channel 4 (5 V/div). (d) Output phase current. Trace: Channel 4 (1.125 A/div). Fig. 16. Harmonic spectrum of output phase voltage of Fig. 15(a). A. Fundamental Switching Frequency Fig. 17 shows the output phase voltage waveform and corresponding spectrum when the converter is operated under fundamental frequency (staircase waveform) and for a modulation index of M =1.85. The first low-order nontriplen harmonic in the spectrum is the 11th (550 Hz). Fig. 18(a) shows the output of the 3L-ANPC submodule, and Fig. 18(b) shows the output voltage of the H-bridge submodule. As discussed in the previous section, the voltage of the two submodules is asymmetrical over consecutive periods due to the selection of the switching patterns that provide the voltage regulation for the H-bridge submodule capacitor. Experimental results for the extended cases of four angles per quarter wave are shown in Fig. 19.

9 4802 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 11, NOVEMBER 2013 Fig. 19. Experimental results and output phase voltage and corresponding harmonic spectrum. Traces: Channel 4 (50 V/div) and FFT (10 V/div). (a) N =4, M =1.94, and Load B. (b) Third harmonic square-wave injection M =2.06 and Load B. Fig. 22. Experimental results for N =12, M =2.1, and Load C. Output phase voltage and corresponding harmonic spectrum. Traces: Channel 4 (50 V/div) and FFT (10 V/div). Fig. 20. Experimental results for N =11, M =2.24, and Load C. Output phase voltage and corresponding harmonic spectrum. Traces: Channel 4 (50 V/div) and FFT (10 V/div). Fig. 23. Experimental results for N =12, M =2.1, and Load C. (a) Output phase and 3L-ANPC voltages. Traces: Channels 2 and 4 (50 V/div). (b) H-bridge output voltage. Trace: Channel 2 (20 V/div). (c) H-bridge capacitor voltage. Trace: Channel 4 (5 V/div). (d) Output current. Trace: Channel 4 (1.125 A/div). Fig. 21. Experimental results for N =11, M =2.24, and Load C. (a) Output phase and 3L-ANPC voltages. Traces: Channels 2 and 4 (50 V/div). (b) H-bridge output voltage. Trace: Channel 2 (20 V/div). (c) H-bridge capacitor voltage ripple. Trace: Channel 4 (5 V/div). (d) Output phase current. Trace: Channel 4 (1.125 A/div). B. Multiple Switchings per Quarter Period The topology is also operated with multiple switchings per quarter period. The experimental results with 11 angles in a distribution of 3/5/3 to the three levels for a modulation index of M =2.24 are shown in Figs. 20 and 21. The output phase voltage harmonic spectrum of Fig. 20 shows that the first harmonic in the output is the 35th (1750 Hz). The range of the modulation index that can be achieved depends on the displacement power factor of the load at the output of the converter. The highly inductive nature of the load results

10 PULIKANTI et al.: HYBRID SEVEN-LEVEL CASCADED ANPC-BASED MULTILEVEL CONVERTER UNDER SHE-PWM 4803 in sinusoidal currents in the output [Fig. 21(d)], while the H-bridge capacitor is maintained to the required level [Fig. 21(c)]. The experimental results closely match the simulations of Section V. One additional angle is considered in the top level (3/5/4 distribution of switchings to the three levels). The experimental results are shown in Figs. 22 and 23. VII. CONCLUSION The hybrid seven-level cascaded ANPC-based multilevel converter under SHE-PWM has been analyzed in this paper. The topology is based on the cascaded connection of a 3L-ANPC converter and individual H-bridge submodules for each phase of the converter. This configuration offers control of the switching losses across the ANPC switches and provides regulation of the voltages across the floating capacitors. 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W. Fuchs, Semiconductor losses in voltage source and current source IGBT converters based on analytical derivation, in Proc. IEEE PESC, 2004, pp Sridhar R. Pulikanti (S 06 M 11) was born in Hyderabad, India. He received the B.Tech. degree in electrical and electronics engineering from Jawaharlal Nehru Technological University, Hyderabad, in 2003, the M.Sc. degree in electric power engineering from Chalmers University of Technology, Gothenburg, Sweden, in 2006, and the Ph.D. degree in electrical engineering from The University of Sydney, Sydney, Australia, in He is currently a Research Fellow with the University of Wollongong, Wollongong, Australia. His research interests include hybrid and multilevel power converters, modulation techniques, and renewable energy conversion technologies.

11 4804 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 11, NOVEMBER 2013 Georgios Konstantinou (S 11) received the B.Eng. degree in electrical and computer engineering from Aristotle University of Thessaloniki, Thessaloniki, Greece, in 2007, and the Ph.D. degree in electrical engineering from the University of New South Wales (UNSW), Sydney, Australia, in From 2008 to 2010, he was with the School of Electrical and Information Engineering, The University of Sydney, Sydney. He is currently a Research Associate with the Australian Energy Research Institute, UNSW. His research interests include multilevel and hybrid converters, modular multilevel converters, renewable energy sources, and selective harmonic elimination pulsewidth modulation for power electronics converters. Vassilios G. Agelidis (SM 00) was born in Serres, Greece. He received the B.Eng. degree in electrical engineering from Democritus University of Thrace, Xanthi, Greece, in 1988, the M.S. degree in applied science from Concordia University, Montreal, QC, Canada, in 1992, and the Ph.D. degree in electrical engineering from Curtin University, Perth, Australia, in From 1993 to 1999, he was with the School of Electrical Engineering and Computing, Curtin University. In 2000, he joined the University of Glasgow, Glasgow, U.K., as a Research Manager for the Glasgow Strathclyde Centre for Economic Renewable Power Delivery. From January 2005 to December 2006, he held the inaugural Chair of Power Engineering at the School of Electrical, Energy and Process Engineering, Murdoch University, Perth. From December 2006 to June 2010, he held the EnergyAustralia Chair of Power Engineering at The University of Sydney, Sydney. He is currently the Director of the Australian Energy Research Institute and a Professor of power engineering with the School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney. He has authored/coauthored several journal and conference papers, as well as the book Power Electronic Control in Electrical Systems (Elsevier, 2002). Dr. Agelidis was a recipient of the Advanced Research Fellowship from the U.K. s Engineering and Physical Sciences Research Council in He was an Associate Editor of the IEEE POWER ELECTRONICS LETTERS from 2003 to 2005 and served as the Power Electronics Society s (PELS) Chapter Development Committee Chair from 2003 to He was the Vice President Operations within the IEEE Power Electronics Society during , an Administrative Committee member of IEEE PELS during , and the Technical Chair of the 39th IEEE Power Electronics Specialists Conference 2008, Rhodes, Greece. Since 2010, he has been an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS.