DTSHEET 8K x 8 synchronous CMOS Static RM FN3005 Rev 2.00 Features Full CMOS Design Six Transistor Memory Cell Low Standby Supply Current............... 100 Low Operating Supply Current............... 20m Fast ddress ccess Time..................150ns Low Data Retention Supply Voltage............ 2.0V CMOS/TTL Compatible Inputs/Outputs JEDEC pproved Pinout Equal Cycle and ccess Times No Clocks or Strobes Required Gated Inputs No Pull-Up or Pull-Down Resistors Required Easy Microprocessor Interfacing Dual Chip Enable Control Ordering Information Description The is a CMOS 8192 x 8-bit Static Random ccess Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RMs. The is ideally suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. The is a full CMOS RM which utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. PCKGE TEMPERTURE RNGE (NOTE 1) 150ns/75 (NOTE 1) 150ns/150 (NOTE 1) 200ns/250 PKG. NO. CERDIP -40 o C to +85 o C - HM1-65642-9 - F28.6 JN# -55 o C to +125 o C 29205BX - - F28.6 NOTE: 1. ccess Time/Data Retention Supply Current. Pinout (CERDIP) TOP VIE NC 12 7 6 5 4 1 2 3 4 5 6 28 27 26 25 24 23 V CC 8 9 11 PIN DQ DESCRIPTION ddress Input Data Input/Output Chip Enable Chip Enable 3 7 22 G rite Enable 2 8 1 9 0 10 DQ0 11 DQ1 12 21 20 19 18 17 10 DQ7 DQ6 DQ5 G NC GND V CC Output Enable No Connections Ground Power DQ2 13 16 DQ4 GND 14 15 DQ3 FN3005 Rev 2.00 Page 1 of 8
Functional Diagram 9 8 12 7 6 5 4 3 RO DDRESS BUFFERS 8 8 RO DECODER 256 256 x 256 MEMORY RRY 256 2 1 0 10 11 COLUMN DDRESS BUFFERS 5 5 COLUMN SELECT (8 OF 256) 8 G 8 DQ 1 OF 8 TRUTH TBLE MODE G Standby (CMOS) X GND X X Standby (TTL) V IH X X X X V IL X X Enable (High Z) V IL V IH V IH V IH rite V IL V IH V IL X Read V IL V IH V IH V IL FN3005 Rev 2.00 Page 2 of 8
bsolute Maximum Ratings Supply Voltage..................................... +7.0V Input or Output Voltage pplied for ll Grades.......GND -0.3V to V CC +0.3V Typical Derating Factor............ 5m/MHz Increase in ICCOP ESD Classification................................ Class 1 Thermal Information Thermal Resistance (Typical) J JC CERDIP Package................ 45 o C/ 8 o C/ Maximum Storage Temperature Range.........-65 o C to +150 o C Maximum Junction Temperature...................... +175 o C Maximum Lead Temperature (Soldering 10s)............ +300 o C Die Characteristics Gate Count................................ 101,000 Gates CUTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range..................... +4.5V to +5.5V Operating Temperature Range -9............................. -40 o C to +85 o C Input Low Voltage............................-0.3V to +0.8V Input High Voltage....................... +2.2V to V CC +0.3V DC Electrical Specifications V CC = 5V 10%; T = -40 o C to +85 o C (-9) LIMITS SYMBOL PRMETER MIN MX UNITS TEST CONDITIONS ICCSB1 Standby Supply Current (CMOS) - 250 = GND, V CC = 5.5V ICCSB2 Standby Supply Current (TTL) - 5 m = 0.8V or = 2.2V, V CC = 5.5V ICCDR Data Retention Supply Current - 150 = GND, V CC = 2.0V ICCEN Enabled Supply Current - 5 m = 2.2V, = 0.8V, V CC = 5.5V, IIO = 0m ICCOP Operating Supply Current (Note 1) - 20 m f = 1MHz, = 0.8V, = 2.2V, V CC = 5.5V, IIO = 0m II Input Leakage Current -1.0 +1.0 VI = V CC or GND, V CC = 5.5V IIOZ Input/Output Leakage Current -1.0 +1.0 = GND, VIO = V CC or GND, V CC = 5.5V VCCDR Data Retention Supply Voltage 2.0 - V VOH1 Output High Voltage 2.4 - V IOH = -1.0m, V CC = 4.5V VOH2 Output High Voltage (Note 2) V CC -0.4 - V IOH = -100, V CC = 4.5V VOL Output Low Voltage - 0.4 V IOL = 4.0m, V CC = 4.5V Capacitance T = +25 o C SYMBOL PRMETER MX UNITS TEST CONDITIONS CI Input Capacitance (Note 2) 12 pf f = 1MHz, ll measurements are CIO Input/Output Capacitance (Note 2) 14 pf referenced to device GND NOTES: 1. Typical derating 5m/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. FN3005 Rev 2.00 Page 3 of 8
C Electrical Specifications V CC = 5V 10%; T = -40 o C to +85 o C (-9) SYMBOL PRMETER MIN LIMITS MX UNITS TEST CONDITIONS RED CYCLE (1) TVX Read Cycle Time 150 - ns (Notes 1, 3) (2) TVQV ddress ccess Time - 150 ns (Notes 1, 3) (3) TLQV Chip Enable ccess Time - 150 ns (Notes 2, 3) (4) THQV Chip Enable ccess Time - 150 ns (Notes 1, 3) (5) TGLQV Output Enable ccess Time - 70 ns (Notes 1, 3) (6) TLQX Chip Enable Valid to Output On 10 - ns (Notes 2, 3) (7) THQX Chip Enable Valid to Output On 10 - ns (Notes 2, 3) (8) TGLQX Output Enable Valid to Output On 5 - ns (Notes 2, 3) (9) THQZ Chip Enable Not Valid to Output Off - 50 ns (Notes 2, 3) (10) TLQZ Chip Enable Not Valid to Output Off - 60 ns (Notes 2, 3) (11) TGHQZ Output Enable Not Valid to Output Off - 50 ns (Notes 2, 3) (12) TXQX Output Hold From ddress Change 10 - ns (Notes 2, 3) RITE CYCLE (13) TVX rite Cycle Time 150 - ns (Notes 1, 3) (14) TLH rite Pulse idth 90 - ns (Notes 1, 3) (15) TLH Chip Enable to End of rite 90 - ns (Notes 1, 3) (16) THL Chip Enable to End of rite 90 - ns (Notes 1, 3) (17) TVL ddress Setup Time Late rite 0 - ns (Notes 1, 3) (18) TVL ddress Setup Time Early rite 0 - ns (Notes 1, 3) (19) TVH ddress Setup Time Early rite 0 - ns (Notes 1, 3) (20) THX rite Recovery Time Late rite 10 - ns (Notes 1, 3) (21) THX rite Recovery Time Early rite 10 - ns (Notes 1, 3) (22) TLX rite Recovery Time Early rite 10 - ns (Notes 1, 3) (23) TDVH Data Setup Time Late rite 60 - ns (Notes 1, 3) (24) TDVH Data Setup Time Early rite 60 - - (Notes 1, 3) (25) TDVL Data Setup Time Early rite 60 - ns (Notes 1, 3) (26) THDX Data Hold Time Late rite 5 - ns (Notes 1, 3) (27) THDX Data Hold Time Early rite 10 - ns (Notes 1, 3) (28) TLDX Data Hold Time Early rite 10 - ns (Notes 1, 3) (29) TLQZ rite Enable Low to Output Off - 50 ns (Notes 2, 3) (30) THQX rite Enable High to Output On 5 - ns (Notes 2, 3) NOTES: 1. Input pulse levels: 0V to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, C L = 50pF (min) - for C L greater than 50pF, access time is derated by 0.15ns per pf. 2. Tested at initial design and after major design changes. 3. V CC = 4.5V and 5.5V. FN3005 Rev 2.00 Page 4 of 8
Low Voltage Data Retention Intersil CMOS RMs are designed with battery backup in mind. Data Retention voltage and supply current are guaranteed over the operating temperature range. The following rules ensure data retention: 1. The RM must be kept disabled during data retention. This is accomplished by holding the pin between -0.3V and GND. 2. During power-up and power-down transitions, must be held between -0.3V and 10% of V CC. 3. The RM can begin operating one TVX after V CC reaches the minimum operating voltage of 4.5V. DT RETENTION MODE V CC 4.5V V IH TVX VCCOR GND FIGURE 1. DT RETENTION Read Cycles TVX (1) DDRESS 1 DDRESS 2 TVQV (2) TXQX (12) Q DT 1 DT 2 FIGURE 2. RED CYCLE I:, HIGH; G, LO FN3005 Rev 2.00 Page 5 of 8
Read Cycles TVX (1) TVQV (2) TLQV (3) TLQX (6) THQZ (9) THQV (4) THQX (7) TLQZ (10) G TGLQV (5) TGLQX (8) TGHQZ (11) Q FIGURE 3. RED CYCLE II: HIGH rite Cycles TVX (13) TVL (17) TLH (14) THX (20) D TDVH (23) THQX (30) THDX (26) TLQZ (29) Q FIGURE 4. RITE CYCLE I: LTE RITE FN3005 Rev 2.00 Page 6 of 8
rite Cycles TVX (13) TVL (18) TLH (15) THX (21) TDVH (24) THDX (27) D FIGURE 5. RITE CYCLE II: ERLY RITE - CONTROLLED BY TVX (13) TVH (19) THL (16) TLX (22) TDVL (25) TLDX (28) D FIGURE 6. RITE CYCLE III: ERLY RITE - CONTROLLED BY FN3005 Rev 2.00 Page 7 of 8
Typical Performance Curve -3 V CC = 2.0V -4-5 LOG (I CC /(1)) -6-7 -8-9 -10-11 -12-55 -35-15 5 25 45 65 85 105 125 T ( o C) FIGURE 7. TYPICL ICCDR vs T Copyright Intersil mericas LLC 2002. ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3005 Rev 2.00 Page 8 of 8