TABLE OF CONTENTS CHAPTER TITLE PAGE DECLARATION ACKNOWLEDGEMENT ABSTRACT ABSTRAK TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS i i i i i iv v vi ix xi xiv 1 INTRODUCTION 1 1.1 Background 1 1.2 Problem Description 3 1.3 Project Objectives 4 1.4 Scope of Project 4 1.5 Proposed Methodology 6 1.6 Outline of the Thesis 8
2 LITERATURE REVIEW 9 2.1 Mobile systems-gprs and EDGE 9 2.2 Wimax Systems 11 2.3 Viterbi Compiler by Altera 14 2.4 MFDA (Modified Feedback Decoding Algorithm) 16 2.5 Other types of Adaptive Viterbi Algorithms 18 2.6 New Developments in Adaptive Coding 21 3 THEORY 22 3.1 Channel Models 22 3.1.1 Multipath fading channel 24 3.1.2 Methods to reduce the effects of fading 25 3.1.3 Combating Distortion 27 3.1.4 Combating Loss in SNR 28 3.2 Convolutional Codes / Viterbi Decoder 29 3.2.1 Encoder Structure 29 3.2.2 Generator representation 31 3.2.3 Tree Diagram representation 31 3.2.4 State Diagram representation 33 3.2.5 Trellis Diagram representation 34 3.2.6 Convolutional Decoding 35 3.2.7 Puncturing and Depuncturing 40 3.3 Fire Codes 41 3.4 Reed Solomon Codes 41 4 DESIGN METHODOLOGY 42 4.1 Introduction 42 4.2 Target FPGA description 43 4.3 Implementation Flow Diagram 44 4.4 RTL Architecture 48 4.5 Shared methodology for the Viterbi Decoder 52
4.5.1 BMC unit description 57 4.5.2 ACS unit description 60 4.5.3 Trace Back Unit / Survivor Memory 65 5 RESULTS 68 5.1 Overview 68 5.2 Approach in selecting candidate configuration 68 5.3 Algorithm / Matlab results Viterbi Performance 69 5.3.1 Trace back length determination 75 5.4 RTL results 77 5.4.1 Test method 77 5.4.2 Timing results 78 5.4.3 Functional coverage 84 5.5 FPGA results 85 5.5.1 FPGA configuration 85 5.5.2 FPGA system simulation 86 6 CONCLUSIONS AND RECOMMENDATIONS 90 6.1 Conclusion and Recommendations 90 6.2 Recommendation for Future Work 91 REFERENCES 92 Appendix A-B 101-127
LIST OF TABLES TABLE NO. TITLE PAGE 2.1 Coding schemes in GPRS 10 2.2 Coding Schemes in EGPRS 11 2.3 Brief Summary of the Code Sets 15 3.1 Conventional Bit Metric Values 39 4.1 Input / Output signal for top level Viterbi 49 Decoder 4.2 Input / Output signal for Viterbi_BMC block 50 (Branch Metric Calculator) 4.3 Input / Output signal for Viterbi_ACS block 50 (Add Compare Select) 4.4 Input / Output signal for Viterbi_MEM block (Memory) 51
4.5 Input / Output signal for Viterbi_traceback 51 block (Traceback) 4.6 Input / Output signal for Viterbi_filo block 51 (First In-Last Out) 4.7 Generator Polynomial of the various Standards 52 and its similarity 4.8 State Table of Constraint length 3 encoder of 53 polynomial G[7,5]. 4.9 State Table of Constraint length 4 encoder of 54 polynomial G[15,11]. 4.10 Rate 1/2 BMC calculation 58 4.11 Rate 1/3 BMC calculation 59 4.12 Pipelined structure of the BMC formula 59 5.1 Test Methodology 69 5.2 Legend explanation 70 5.3 Summary of the plots in Figure 5.1,5.2 and 5.3 72 5.4 PER values of packet size N=500 and N=1000 74 respectively 5.4 Statement coverage and Branch coverage from 84 Modelsim 5.6 Summary of APEX20K200E features 85 5.7 LE used in the adaptive Viterbi design 86
LIST OF FIGURES FIGURE NO. TITLE PAGE 1.1 Tx Rx modules 5 1.2 Conventional method for GPRS and EDGE 6 1.3 Shared Hardware approach GPRS and 7 EDGE 1.4 Internal Viterbi blocks 7 2.1 Convolutional encoder constraint length 7 12 and rate ½ 2.2 BTC and shortened BTC codes 13 2.3 CTC encoder 13 2.4 Configurability of the Viterbi on Altera s MegaCore 15
2.5 Block diagram of a MFD 17 3.1 Channel Modeling 23 3.2 The Three major performance categories in 26 terms of BER vs EB/No. 3.3 Methods of Mitigating Frequency selective 27 and Fast Fading. 3.4 Methods to combat loss in SNR 28 3.5 General structure of convolutional encoder 29 3.6 K=3, r = ½, m=2 convolutional encoder 29 3.7 Tree diagram representation for four input bit 32 intervals 3.8 State machine of the convolutional encoder 33 in figure 3.6. 3.9 Trellis diagram of the encoder of figure 3.6 34 3.10 Trellis path for the input sequence of x = 35 {1,0,1,1} 3.11 Soft Decision and Hard Decision example 36 3.12 Convolution Encoder + Viterbi decoder 37 system 3.13 BSC Channel, where p is the crossover probability 38 3.14 System showing puncturing and 40 depuncturing blocks 3.15 Example of data structure after puncturing 40 3.16 Example of data structure after depuncturing 41 4.1 FPGA integration 42 4.2 Flow Diagram of Viterbi Decoder 44 4.3 Behavioral structure of the branch metric 45 computation 4.4 Behavioral structure of the Add Compare 46 Select unit 4.5 FSM structure of the Traceback unit 48 4.6 Top Level RTL Architecture of Viterbi 48
Decoder 4.7 Viterbi Flow Structure 53 4.8 Trellis Diagram for a constraint length 3 over 55 1 time period 4.9 Trellis diagram for constraint length 4 and 3 56 over 1 time period 4.10 Branch Metric Unit 58 4.11a Trellis of K=3, 4 states 60 4.11b Trellis structure for K=4, 8 states 61 4.12 ACS Unit 62 4.13 2 ACS units showing the shared multiplexer 63 4.14 Sample Merging Paths and its selection 64 4.15 Numerical Example of how the ACS works 65 4.16 Memory structure for a traceback length of 66 50 5.1 BER under AWGN channel 70 5.2 BER under fast fading with AWGN channel 71 5.3 BER under Slow fading with AWGN 71 channel 5.4 Simulation curve of 3 different convolutional 73 encoder 5.5 BER of various traceback length MCS9 P1 75 5.6 BLER of various traceback length MCS9 P1 76 5.7 Functional RTL test methodology 77 5.8 Timing Diagram showing the Code Rate 1/2 78 input mechanism 5.9 Timing Diagram showing the Code Rate 1/3 78 input mechanism 5.10 Timing diagram for configuration of K=5, 79 rate ½ 5.11 Timing diagram for configuration of K=7, 79 rate ½ 5.12 Timing diagram for configuration of K=7, 80
rate 1/3 5.13 Timing diagram of the BMC block 81 5.14 Timing diagram of the ACS block 81 5.15 Timing diagram of the Memory block 82 5.16 Timing diagram of the Trace Back Block 82 5.17 Timing diagram of the FILO Block 83 5.18 FPGA simulation setup 87 5.19 HyperTerminal settings 88 LIST OF ABBREVIATIONS GPRS - General Packet Radio Service EDGE - Enhanced Data Rates for GSM Evolution 3G - Third Generation WiMAX - Worldwide Interoperability for Microwave Access MIPS - Millions of Instructions per Second DSP - Digital Signal Processor FPGA - Field Programmable Gate Array BPSK - Binary Phase Shift Keying TX - Transmitter RX - Receiver FEC - Forward Error Control BER - Bit-Error Rate
Eb/No - Energy per Bit over Spectral Noise Density SNR - Signal to Noise Ratio CRC - Cyclic Redundancy Check WLAN - Wireless Local Area Network GSM - Global System for Mobile communication EGPRS - Enhanced GPRS TB-CC - Tail Biting Convolutional Codes BTC - Block Turbo Codes CTC - Convolutional Turbo Codes LDPCC - Low Density Parity Check Codes ZT-CC - Zero Tail Convolutional Code OFDM - Orthogonal Frequency Division Multiplexing OFDM A - Orthogonal Frequency Division Multiplexing Access RS - Reed Solomon CS - Coding Scheme MCS - Modulation Coding Scheme BCH codes - Bose-Chauduri-Hocquenghem codes GF - Galois Field XOR - Exclusive OR CPLD - Complex Programming Logic Device JTAG - Joint Test-Action Group ROM - Read Only Memory RAM - Random Access Memory PSK - Phase Shift Keying GMSK - Gaussian Minimum Shift keying TDD - Time Division Muliplexing FDD - Frequency Division Muliplexing BPS - bits per second MFDA - Modified Feed back Decoding Algorithm FDA - Feed Back Decoding BSC - Binary Symmetric Channel TB - Trace Back