CMOS VLSI Design (A3425) Unit III Static Logic Gates Introduction A static logic gate is one that has a well defined output once the inputs are stabilized and the switching transients have decayed away. Static CMOS logic gates are relatively easy to design and use. This chapter deals with the static logic gates, from simple NAND and NOR operations to complex functions that are quite large and powerful. Communication Engineering 1
General Structure Static CMOS logic gates are constructed using completely symmetric nmos and pmos transistor arrays. Complex logic gates are constructed using the CMOS inverter as a basis. In order to construct a complex logic gate, let us replace the single inverter nfet by an array of nfets that are connected to operate as a large switch. Similarly, we will substitute an array of pfets for the single pfet used in the inverter, and view the pfet array as a giant switch. Steps to Create Complex Gates The general structure of a complex logic gate can be created by the following steps. Provide a complementary pair (an nfet and a pfet with a common gate) for each input; Replace the single nfet with an array of nfets that connects the output to ground; Replace the single pfet with an array of pfets that connects the output to V DD ; Design the nfet and pfet switching network so that only one network acts as a closed switch for any given input combination. Communication Engineering 2
General Structure of a Static Logic Gate Communication Engineering 3
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Transient Analysis When analyzing the output transients, nfet and pfet to Logic Gate Equivalence Communication Engineering 7
Exclusive OR and Equivalence Gates Exclusive OR and Equivalence Gates Communication Engineering 8
Mirror Circuits The XOR operation is used extensively in several types of logic networks including adder circuits and parity checkers. The philosophy of mirror circuits can be better understood by considering a 2 variable gate. The possible input combinations are Since the XOR function has the form Mirror Circuits Since the XOR function has the form This means that the combinations should provide the connections from the output to the power supply, while should connect the output to ground. Similarly, the function for XNOR (Equivalence Gate) is Communication Engineering 9
Mirror Circuits Uses the same transistor topology for the nfet and pfet networks. When there are equal numbers of input combinations producing 0s and 1s. XOR XNOR Advantages: More symmetric layouts Shorter rise and fall times Mirror Circuits Communication Engineering 10
Mirror Circuits Mirror Circuits Communication Engineering 11
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Full Adder Circuits Communication Engineering 13
NOR Based SR Latch NOR Based SR Latch Communication Engineering 14
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SRAM Communication Engineering 16
SRAM Tri-State Output Circuits Static logic gates provide logic 0 and logic 1 output values by connecting the output node to either ground or to the power supply. Static Logic Two States - 0 and 1 A tri-state output circuit is designed to give these two logic states, but also provides for a third highimpedance (Hi-Z) state in which the output node is floating. Tri-State Output Logic Three States 0, 1 and Hi-Z Communication Engineering 17
Tri-State Output Circuits Figure shows tri-state circuit that uses the enable signal En to switch between normal and Hi-Z operation. pfet is controlled by the function nfet is controlled by the function If En=0, then fp=1, fn=0 which drives both FETs into cutoff, producing the Hi-Z state. If En=1, then fp=d, fn=d which allows the input D to control the transistors Tri-State Output Circuits Figure below reverses the roll of the tri-state control by moving the location of the inverter. The FET inputs are controlled by This results in the circuit that gives a Hi-Z output state when the control bit Hi is 1 and normal operation with Hi=0. Communication Engineering 18
Tri-State Output Circuits Figure below shows another tri-state circuit. In the circuit, the Hi-Z control variable X is applied directly to the tri-state pfet MpX while X is applied to MnX. If X=0, then both FETs are active and the gate produces an output of D. A Hi-Z state is achieved with X=1, since this turns both tri-state FETs OFF. Psuedo-nMOS Logic Gates nmos logic family uses only nfets Pseudo-nMOS logic resemble the nmos logic with active pull-up (pfet). Figure shows a basic nmos inverter A single nfet MD is a driver device that controls the circuit. The output node is connected to the power supply through a load resistor R L that acts as a pull-up device Communication Engineering 19
Psuedo-nMOS Logic Gates Operation For Vin<V Tn, the driver MD is in cutoff giving I D =0 Since the load current is equal to the driver current, the voltage across the load resistor is V L =I L R L = 0V The output voltage is given by Psuedo-nMOS Logic Gates Operation When a high input voltage V in = V DD is applied MD conducts but the resistor still tries to pull up the output voltage. This keeps V out from ever reaching 0V so that the output low voltage V OL is always greater than zero: V OL > 0. Psuedo-nMOS logic gate replaces the resistor with a biased-on pfet as shown in figure below. Communication Engineering 20
Psuedo-nMOS Logic Gates DC Characteristics and Operation pfet voltages are given by pfet is always biased into active region and cannot be turned off. For V in <V Tn, nfet is cutoff and V out = V DD = V OH For V in >V Tn, Mn turns into conduction, V in = V DD = V OH V OL is small Mn is non-saturated V OL < V Tp, Psuedo-nMOS Logic Gates driver-to-load ratio Communication Engineering 21
Complex Logic in Psuedo-nMOS Simplified XNOR Gate Communication Engineering 22
Compact XOR and Equivalence Gates Alternate XOR and XNOR Gates Communication Engineering 23
Alternate XOR and XNOR Gates Schmitt Trigger Circuits VTC exhibits hysteresis Forward characteristics are different from the reverse characteristics When Vin = 0V DD, the transition takes place at the forwardswitching voltage V +. When Vin = V DD 0, the transition takes place at the reverse switching voltage V -. The hysteresis voltage V H = V + -V - Communication Engineering 24
Schmitt Trigger Circuits A symmetrical CMOS Schmitt trigger circuit is shown in figure below. pfet circuit is the mirror image of the nfet circuit. The forward switching is controlled by the nfets while the reverse switching is determined by the pfets. Schmitt Trigger Circuits Forward switching voltage V + : Mn2 is the main switching device. Mn1 and Mn3 acts as feedback network which controls the value of V+. Assume that the input is set to Vin = 0 and then increased; all of nfets are initially in cutoff. Conduction depends on the gate-source voltages Mn1 turns ON when V GS1 =V T1 Mn2 requires an input voltage of Communication Engineering 25
Schmitt Trigger Circuits V+ can be estimated by ignoring body bias effects. To turn on Mn2 requires a drain-source voltage of Mn1 is in saturation with a current of Mn3 is also saturated (since V GS3 =V DS3 ) with a current of Equating current I 1 =I 3 and rearranging gives Similarly, the reverse trigger voltage V- is given by Schmitt Trigger Circuits Reverse switching voltage V - : Mp4 is in saturation with a current of Mp6 is also saturated with a current of Where V = V V γ Tp Equating I 4 =I 6 and rearranging gives I β 2 ( V ) 2 DD V VTp 4 4 = β 2 ( ) 2 γ 6 I6 = V V Tp Communication Engineering 26
Schmitt Trigger Circuits This CMOS circuit allows for designing a symmetric trigger where Hysteresis voltage is given by Alternate Schmitt Trigger Communication Engineering 27