ISSN 2348 2370 Vol.06,Issue.05, August-2014, Pages:347-351 www.semargroup.org www.ijatir.org PG Scholar, Dept of ECE, Sreenidhi Institute of Science and Technology, Hyderabad, India. Abstract: This paper discusses a technique which reduces the power consumption in CMOS digital circuits and to introduce a new technology CNFET which consumes less power and provides better performance than CMOS. The transistor size has been scaled down to achieve the exponential growth in transistor counts, but the scaling will soon end CNTs can be used to develop Carbon Nano-tube Field Effect Transistors (CNFETs) whose conducting channel is made of carbon nano-tubes. The CNFET, which is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. The CNFETs are about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15 20 times lower than silicon CMOS devices. D-type flip-flops are implemented using the Silicon MOSFETs and CNFETs and performance is evaluated for both. CNFETs implementation shows better performance and consumes less energy than MOSFETs. Keywords: CNFET, CMOS, Carbon Nano-Tubes, DFF, Sub-Threshold Voltage. I. INTRODUCTION Power consumption has increased substantially with the increase of speed and number of transistors per unit chip area. The important design constraint along with area and speed in modern VLSI design is Power. The equation which represents Power consumption of a digital CMOS circuits is shown below: (1) The first term dynamic power consumption is the dominating term, which is due to logic switching. Where CL is the load capacitance, α is the switching activity, V dd is the supply voltage, and f is the switching frequency. The power dissipated due to the short circuit current, Isc, generated when both NMOS and PMOS transistors are simultaneously active is shown by the second term. The term I leak V dd is due to leakage current, I leak, which varies with processing technology. consumption in digital systems. These circuits are very useful where battery life is more important than the speed like in health and environment, where data monitored changes slowly. The reduction of the supply voltage and transistor size of MOSFET came to an end since scaling faces serious problem in fabrication and device performance. The device scaling results in quantum mechanical tunneling of carriers through the thin gate oxides, quantum mechanical tunneling of carriers from source to drain and from drain to body, control of the density and location of do pant atoms in the MOSFET channel and source drain region to provide high on off current ratio, the finite sub-threshold slope. As scaling towards nm technology, due to the random nature of manufacturing process, various effects such as ion implantation, diffusion and thermal annealing have induced significant fluctuations of electrical characteristics. To overcome these limitations many solutions are propose. Some alternatives which would enable continued improvement in the performance of electronics systems are high dielectric constant (High K), metal gate electrode, double gate FET[1]. Reducing direct tunneling leakage currents and efficient charge injection are provided by the High-K dielectric materials. The technologies that could replace the MOSFET as the basic logic device, are negative differential resistors, nano-wire or carbon nano tube FET, quantum cellular automata, and reconfigurable switches. The best way to reduce power consumption is to lower the supply voltage level of a circuit. As voltage is quadratically related with dynamic power, a small reduction in the supply voltage results in a moderate reduction in the dynamic power consumption. However, that the reduction in the supply voltage causes an increase in the circuit delay and consequently a reduction in the throughput. Second method is to reduce the size of the transistor which reduces the load capacitance results in decrease of dynamic and the leakage power. The digital and analog circuits can operate at ultralow voltages (<0.4V). This region is considered as the subthreshold voltage region. Sub-threshold circuits are those A. Sub-threshold Operation for Ultimate Low Power II. SUBTHRESHOLD OPERATION whose supply voltage V DD less than the threshold voltage Vt Logic of the MOS transistor. The power is related quadratically to The design of medium power and medium performance the supply voltage, reducing the voltage to ultra-low levels circuits has given attention. The well known methods - results in a dramatic reduction in both power and energy include voltage scaling, switching activity reduction, Copyright @ 2014 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.
architectural techniques of pipelining and parallelism, issues of device sizing, interconnect and logical optimization. These methods are not sufficient in many applications such as portable computing gadgets, medical electronics etc., where low power consumption is the primary requirement. The design of digital sub-threshold logic is investigated with the devices operated in sub-threshold region. Fig.1 shows the sub-threshold region of interest. In conventional CMOS the circuits are operated with the voltage greater than threshold voltage. This region is known as strong inversion or super threshold. If the supply voltage is less than the threshold voltage the transistor can be operated in ultra low power consumption. This is called sub-threshold and current flows is sub-threshold current[6]. logic can operate the circuit at higher frequencies while still maintaining the same energy/ switching with enhanced robustness com- pared to static CMOS. 4. Sub-threshold Domino Logic: It is similar to conventional domino logic except the transistors are operated in sub-threshold region. Sub- domino outweighs Sub-CMOS by about 32% in terms of power consumption. The Sub-domino logic is 32% faster than sub- CMOS logic. III. CARBON NANOTUBES: FUTURE TECHNOLOGY FOR SUB-THRESHOLD REGIME The sub-threshold circuits are very promising for ultra-low power applications. However, operating circuits at very low values of supply voltages raises robustness issues such as sensitivity to process, voltage and temperature (PVT) variations. High performance carbon nano tube field effect transistors (CNFETs) with very high on - currents have been reported in literature and are a promising solution for VLSI requirements[11]. Fig.1. Region of operation of digital sub-threshold logic[6]. B. Optimal Logic Families for Sub-threshold Operation They operate at very low values of supply voltage. The low supply voltages raise the robustness issues. Design of robust sub-threshold logic circuits exploring logic families is another area for research. The following logic families are optimal for sub-threshold operation operation. A. Overview of the CNFET Structure Fig.2 shows carbon nano-tube Field Effect Transistors (CNFETs) who s conducting channel is made of carbon nanotubes. Nano-tubes have electrical properties that make them attractive as nano-electronics wires and devices: they can behave as metallic wires or as semiconductors, depending on their structure. The channel can contain single nano tube (called SWCNFET) or multiple nano tubes(mwcnfet). The MWCNFET has more structural faults when compared to the SWCNFET. SWCNFET replaces the MOSFET. 1. Sub-threshold CMOS Logic: CMOS logic operated in the sub- threshold region is know as sub-threshold CMOS logic. The voltage transfer characteristics (VTC) of the CMOS gates in sub-threshold region are closer to ideal compared to the VTC in normal strong inversion region. The ideal VTC yields better noise margins. Drain current ID and gate-source voltage VGS exhibit exponential relationship in sub-threshold. This gives rise to an extremely high trans-conductance. 2. Sub-threshold Pseudo-NMOS Logic: It is more robust than its strong inversion counter- part. It operates 6 times faster than conventional CMOS. The PDP of pseudo-nmos is better and possess comparable robustness to static CMOS in sub- threshold region[6]. 3. Sub-DTMOS logic: It uses transistors whose gates are tied to their substrate. The substrate voltage in sub-dtmos logic changes with the gate input voltage, the threshold voltage is dynamically changed. The PDP of DTMOS is comparable to the PDP of regular CMOS. The DTMOS Fig.2. Carbon nano-tube that can be formed by rolling up grapheme. The CNFET is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices[3].the intrinsic delay is very low, show higher electron mobility compared to bulk silicon. CMOS circuit blocks can be realized using CNFETs since their operation principle is similar. Single walled carbon nano-tubes (SWCNTs) has many in electronics because of both their metallic and semiconducting properties and their ability to carry high current. CNTs are capable to carry current density of the order 10 μa/nm2, while standard metal wires have a current carrying capability of the order 10 na/nm2. SWCNT can be made to act as either conductor or semiconductor depending on the angle of atom alignment along the tube[8]. This is known as
the chirality vector and is represented by the integer pair (n, m). Based on them we can determine whether it is metal or semiconductor. When n=m or n-m=3i (I is an integer) then the tube is metallic, otherwise it is semiconducting [9]. The diameter of tube is given by (2) CNFET diameter determines the band gap energy of the tube. The relationship between the diameter and band gap energy is shown below (3) B. Geometry Dependent CNTFET 1. Back-gate CNTFET: The CNTs which is semiconducting is made to fall across two metal strips. One of them is the "source" contact while the other is the "drain" contact. The gate oxide is the silicon oxide substrate and adding a metal contact on the back makes the semiconducting CNT gateable. There are some limitations of this one of it was the metal contact, which actually had very little contact to the CNT, since the nano-tube just lay on top of it and the contact area was therefore very small and also due to the semiconducting nature of the CNT, a Schottkey Barrier forms at the metal-semiconductor interface increasing the contact resistance. The second disadvantage was due to the back-gate device geometry. Its thickness made it difficult to switch the devices on and off using low voltages, and the fabrication process led to poor contact between the gate dielectric and CNT[7] as shown in Fig.3. Fig.4.Top Gate CNFET. Table I: Comparison between Back Gate CNTFET and Top gate CNTFET C. Based on the Type Electrode CNTFETs are classified into three categories. (a) Schottkybarrier (SB) CNTFET (b) Partially gated (PG) CNTFET and (c) doped-s/d CNTFET. 1. Schottky-barrier (SB) CNTFET: In this type of CNTFET an intrinsic CNT is used in the channel region. The intrinsic CNT is connected to metal Source/Drain and forms Schottky barriers at the junctions. They operate as unconventional Schottky barrier transistors in which transistor action occurs primarily by varying the contact resistance rather than the channel conductance. Fig.3.Back Gate CNFET. Top gate CNTFET: The fig.4 shows the schematic diagram of a top-gated CNTFET with Ti source, drain, and gate electrodes. The gate oxide used was 15-nm SiO 2 film. In this gate is placed over the CNT. The table 1 below shows the advantages of top gated CNTFET over back gated CNTFET. The top gate CNFET is more advantageous over back gate CNFET. The current on off ratio is better for top gate CNFET. It has better trans-conductance over the back gate CNFET[7]. 2. Partially gated (PG) CNTFET: It is a depletion mode CNTFET in which the nano-tube is uniformly doped or uniformly intrinsic with ohmic contacts at their ends. They can be of n-type or p-type when respectively n-doped or p- doped. In these devices the gate locally depletes the carriers in the nano-tube and turns off the p-type (n-type) device with an efficiently positive (negative) threshold voltage that approaches the theoretical limit for room-temperature operation. The on-current of such devices is given as I D (on) =qρvt where ρ is the carrier density per unit length and v t is the uni-directional thermal velocity. 3. Doped- source or drain (S/D) CNTFET: Doped-S/D CNTFETs are composed of three regions. The region below the gate is intrinsic in nature and the two un-gated regions are doped with either p-type or n-type. In this CNFET the ON-current is limited by the amount of charges that can be induced in the channel by the gate and not by the doping in the source. They operate in a pure p- or n-type
enhancement-mode or in a depletion-mode, based on the principle of barrier height modulation when applying a gate potential [2] as shown in Fig.5. Out of three, doped S/D CNTFETs are promising because (1) they show uni-polar characteristics unlike SB-CNTFETs; (2) the absence of SB reduces the OFF leakage current; (3) they are more scalable compared to their SB counterparts; (4) in ON-state, the source-to-channel junction has a significantly higher ON current. taken as 3 (minimum) and increased for the transistors requiring larger current driving capability. CNFET SDFF achieves 8 times better speed, 3 times less power and 24 times better PDP compared to silicon CMOS version. CNFET SDFF operates less than one third of the voltage silicon SDFF operates shown in [10]. Fig.6. SDFF, Simple D Flip-Flop. Fig.5.(a) SBCNFET (b) CNTFET (c) Tunneling CNFET[2]. Depending on the doping profile doped S/D CNTFETs can again be classified into two groups. Conventional CNTFET (C-CNTFET): This comprise of CNTFETs with p/i/p or n/i/n doping scheme that is both S/D are doped with either p-type or n-type material. Tunneling CNTFET (T-CNTFET): CNTFETs with n/i/p doping scheme (source and drain are oppositely doped) comes under this group. The above CNTFETs discussed are of planer structure. Besides these one more structure is also developed which is known as vertical CNTFET (V-CNTFET) or coaxially gated CNTFET. This consists of a SWCNT with a coaxial gate. The advantage of V-CNTFET is that vertical growth in CNT is easier and aligned than horizontal growth[4]. IV. COMPARISON BETWEEN MOSFET AND CNFET A. Design of D Flip-Flop Flip-Flops are major components of digital circuits. Two popular DFFs based on master-slave latch-pairs have been used for the design and optimized in terms of power. The first design uses simple and area efficient flip-flop circuit (SDFF) shown in Fig6. BSIM 32nm predictive model has been used for simulation. Transistor sizes have chosen as small as possible to achieve the lowest power. The same SDFF is implemented using the CNFET as shown in [10]. The design requires width to length ratio as 1 for carbon nano-tube PCNFET and NCNFETs since current driving capacity is the same for both transistors. Number of tubes are V. CONCLUSION In this paper an overview of the subthreshold operation of MOSFET is presented briefly. A simple DFF is built using the CMOS and the CNFETs and their performance is evaluated. The CNFET circuits shows the better performance than the CMOs circuits. One of the major challenges faced by the CNFET is the presence of unwanted metallic tubes that has an unfavourable impact on the delay, power, and functional yield of carbon nanotube based circuits. The unwanted growth of metallic tubes during the fabrication of CNTs is a major challenge that will affect the fabrication of robust CNT-based circuits. VI. REFERENCES [1] CNFET based Logic circuits, Sanjeet Kumar Sinha, Saurabh Choudhury, IJETAE, ISSN 2250-2459. [2] Comparing Carbon Nanotube Transistors-The Ideal Choice: A Novel Tunneling Device Design, Joerg Appenzeller, Zhihong Chen, Vol.52, IEEE. [3] Comparison of variations in MOSFET versus CNFET in Gigascale Integration, Ali Arabi M. Shahi, Payman Zarkesh-Ha, Mirza Elahi, 978-1-4673-1036-9, IEEE. [4] Design and Analysis of High performance CNFET based Fulladder, Mohammad Hossein Moaiyeri, RezaFaghih Mirzaee, Keivan Navi, AmirMomeni. [5] Emerging research devices: A study of CNFET and SET as replacement for SiMOSFET, Mahmoud Lababidi, Krishna Natarajan, Guangyu Sun. [6] Subthreshhold Circuit Design Techniques for ultra low power logic, Rohit Dhiman, Rajeevan Chandel and R.P. Agarwal. [7] Simulations of Carbon Nano tube Field Effect Transistor, Rasmita Sahoo and R. R. Mishra, IJEER,ISSN 0975-6450. [8] CNFET based Basic Gates and a novel full adder cell, Fazel Sharifi, Amir Momeni,keivan Navi, International Journal of VLSI design & Communication Systems, Vol.3. [9] Comparitive performance Evaluation of Large FPGA with CNFET and CMOS based switches in Nanoscale, Mohammad Hossein Moaiyeria,, Ali Jahaniana,, Keivan Navia,.
[10] Design and Analysis of Lowpower Carbon Nanotube Field Effect Transistor DFF, Ovunc Polat,Ali Manzak,978-1-61284-840-2/11,IEEE,2011. [11] Assessment of Silicon MOS and carbon Nanotube FET performance limits using a General theory of Ballistic Transistor,Jing Guo, Supriyo Datta, and Mark Lundstrom.