Sony IMX046 8.11 Megapixel, 1.4 µm Pixel 1/3.2 Optical Format CMOS Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metals 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Isolation 3.8 Wells, Epi, and Substrate 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 4.4 Light Pipe, Color Filters, and Microlenses 5 Critical Dimensions 5.1 Package and Die 5.2 Vertical Dimensions 5.3 Horizontal Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 Samsung M8800 Cell Phone Front View 2.1.2 Samsung M8800 Cell Phone Back View 2.1.3 Samsung M8800 Cell Phone Side View 2.1.4 Samsung M8800 Cell Phone Bottom View 2.1.5 Inside Samsung M8800 Cell Phone 2.1.6 Camera Main Board 2.1.7 IMX046 Image Sensor Module Top 2.1.8 IMX046 Image Sensor Module Bottom 2.1.9 IMX046 Image Sensor Module Tilt View 2.1.10 IMX046 Image Sensor Module Side View 2.1.11 IMX046 Image Sensor Module X-Ray Bottom 2.1.12 IMX046 Image Sensor Module X-Ray Side 2.1.13 IMX046 Package Top View 2.2.1 Die Photograph Intact 2.2.2 Die Photograph Organic Lenses and Filters Removed 2.2.3 Die Markings 2.2.4 IMX046 Annotated Metal 1 Die Photograph 2.2.5 Analysis Sites 2.3.1 Die Corner A 2.3.2 Die Corner B 2.3.3 Die Corner C 2.3.4 Die Corner D 2.3.5 Alignment Pattern 2.3.6 Pixel Count Marker Organic Lenses and Color Filters Removed 2.3.7 Minimum Pitch Bond Pads 2.3.8 Test Pads 2.3.9 Pixel Array Corner A 2.3.10 Pixel Array Corner C 2.3.11 NAND Cell 3 Process 3.1.1 Pixel Array General Structure 3.1.2 Peripheral General Structure 3.1.3 Die Edge Overview 3.1.4 Die Edge Detailed View 3.1.5 Die Seal 3.2.1 Bond Pad 3.3.1 Passivation and ILD 4 in Periphery 3.3.2 Passivation and ILD 4 in Pixel Region 3.3.3 ILD 3, ILD 2, and ILD 1 3.3.4 PMD in Periphery
Overview 1-2 3.3.5 PMD in Pixel Array 3.4.1 Minimum Pitch Metal 5 3.4.2 Minimum Pitch Metal 4 and Metal 2 3.4.3 Metal 2 Composition TEM 3.4.4 Minimum Pitch Metal 3 3.4.5 Minimum Pitch Metal 1 3.4.6 Metal 1 Composition TEM 3.4.7 Detail of Metal 1 TEM 3.5.1 Minimum Pitch Via 4s 3.5.2 Minimum Pitch Via 3s 3.5.3 Minimum Pitch Via 1s and Via 2s, and Contacts to Diffusion in Periphery 3.5.4 Minimum Pitch Contact to Diffusion in Pixel Array 3.5.5 Minimum Pitch Via 1 Contact to Poly 3.6.1 Minimum Gate length MOS Transistor TEM 3.6.2 Logic Gate Dielectric TEM 3.6.3 Logic NMOS (Si Etch) 3.6.4 Logic PMOS (Si Etch) 3.6.5 Minimum Contacted Gate Pitch 3.6.6 Peripheral Poly 3.7.1 Minimum Width STI Periphery 3.7.2 Poly Over STI Periphery 3.7.3 STI in Pixel Array TEM 3.7.4 Poly Over STI Pixel Array 3.8.1 SCM of Peripheral Wells 3.8.2 SCM of Peripheral Wells in Detail 3.8.3 Peripheral N and P-Well SRP 3.8.4 Peripheral P-Well SRP 3.8.5 SRP in Pixel Array 4 Pixel Array Analysis 4.1.1 Pixel Schematic Circuit 4.2.1 Pixel Array Corner Optical 4.2.2 Pixel Array Organic Microlenses Corner 4.2.3 Pixel Array Organic Microlenses in Detail 4.2.4 Pixel Array Organic Microlenses Tilt View 4.2.5 Pixel Array at Metal 4 4.2.6 Pixel Array at Metal 3 4.2.7 Pixel Array at Metal 2 4.2.8 Pixel Array at Metal 1 4.2.9 Pixel Array at Poly 4.2.10 Pixel Array at Substrate 4.2.11 Pixel Array at Substrate Detail 4.2.12 Pixel Array at Substrate SCM 4.2.13 Pixel Array at Substrate Detail SCM
Overview 1-3 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan View 4.3.2 Transfer Gate (T3/T4) and Pixel Overview (C) 4.3.3 Detail of P-pinning Layer (Si Etch) Parallel to Column Out Line (I) 4.3.4 Detail of Transfer Gates and Floating Diffusion (A) TEM 4.3.5 Transfer Gate Detail TEM (A) 4.3.6 Transfer Gate Edge Facing the Photocathode TEM (A) 4.3.7 Transfer Gate Edge Facing FD TEM (A) 4.3.8 Silicon Nitride AR Layer Stack (A) 4.3.9 Pixel Array Gate Oxide TEM (A) 4.3.10 SCM of Pixel Array (A) 4.3.11 SCM of Photocathode (A) 4.3.12 General Structure of T5, T6, and T7 Transistors (G) 4.3.13 Reset Transistor T5, Source Follower T6, and Row select T7 Detail (G) 4.3.14 General Structure of T5, T6, and T7 Transistors V DD Line (K) 4.3.15 T5 Gate Width (I) 4.3.16 T6 Gate Width (J) 4.4.1 General Structure Near Pixel Array Center (D) 4.4.2 General Structure (K) 4.4.3 Pixel at Array Edge Parallel to Row Select (D) 4.4.4 Active to Dark Pixels Transition Parallel to Column Out (H) 4.4.5 Blue Filter Edge 4.4.6 Edge of Organic Spacer and Optical Pad Layer 4.4.7 Top of Light Pipe TEM 4.4.8 Between Two Light Pipes TEM 4.4.9 Bottom of Light Pipe TEM 4.4.10 Red and Green Color Filters TEM 4.4.11 Red Color Filter TEM 4.4.12 Blue Color Filter
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Sample Markings 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2 Package and Die 2.2.1 Functional Block Sizes 2.3.1 Package and Die Dimensions 3 Process 3.3.1 Dielectric Composition and Thicknesses 3.4.1 Metallization Composition and Thicknesses 3.4.2 Minimum Metal Horizontal Dimensions 3.5.1 Via and Contact Horizontal Dimensions 3.6.1 Transistor and Polysilicon Horizontal Dimensions 3.6.2 Transistor and Polysilicon Vertical Dimensions 3.7.1 Periphery and Pixel Array Isolation Critical Dimensions 3.8.1 Wells, Epi, and Die Vertical Dimensions 4 Pixel Array Analysis 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Transistor Dimensions in Pixel Array 4.4.1 Pixel Elemental Analysis 5 Critical Dimensions 5.1.1 Package and Die Dimensions 5.2.1 Dielectric Composition and Thicknesses 5.2.2 Metallization Composition and Thicknesses 5.2.3 Transistor and Polysilicon Vertical Dimensions 5.2.4 Wells, Epi, and Die Vertical Dimensions 5.2.5 Isolation Composition and Thicknesses 5.2.6 Pixel Vertical Dimensions 5.3.1 Minimum Metal Horizontal Dimensions 5.3.2 Via and Contact Horizontal Dimensions 5.3.3 Transistor and Polysilicon Horizontal Dimensions 5.3.4 Isolation Horizontal Dimensions 5.3.5 Pixel Horizontal Dimensions 5.3.6 Transistor Dimensions in Pixel Array
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