Politecnico di Torino - ICT school Group B: Digital circuits and devices DIGITAL ELECTRONICS B DIGITAL CIRCUITS B.1 Logic devices B1 B2 B3 B4 Logic families Combinatorial circuits Basic sequential circuits Counters and x-stable circuits» Static and dynamic parameters» Interfacing and compatibility» Power consumption» BJT and CMOS logic circuits» Examples of data sheets 28/04/2009-1 DigElnB1-2009 DDC 28/04/2009-2 DigElnB1-2009 DDC Lesson B1: logic devices Power consumption Static power consumption Dynamic power consumption Pass gates Bipolar logic families MOS logic families Interfacing Examples of data sheets Reference 1: Storey chap 14 Reference 2: The operation of any module requires some energy Part is used for internal operations» Useful Part is used for external output signals» Part useful (Shannon theorem!), part wasted (EMI) Part becomes heat» Wasted The energy comes from the power supply systems Usually a fixed power supply voltage (Val), such as 5 V, 3,3 V, 2,5 V, The measure or power consumption is the current sink from the power supply system 28/04/2009-3 DigElnB1-2009 DDC 28/04/2009-4 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 1
Why should we care of power? Static power: P S High currents involve: Thick wires/tracks (with large size, weight) Generation of electromagnetic interferences (EMI) Large power supply units Fixed sets: weight, size, cost Portable sets: reduced duration of batteries More heat to dissipate in the environment A major limit for integration density Need for special packaging and cooling Environment ecology issues (marginal) IN Power used with no state change Almost constant current from power supply Changes with temperature and supply voltage Val Modeled as a DC current (Idc) from Val to GND Idc DIGITAL MODULE GND OUT GND 28/04/2009-5 DigElnB1-2009 DDC 28/04/2009-6 DigElnB1-2009 DDC Dynamic power: P D Evaluation of dynamic power Power used to get a state change (H L o L H) Current I L, to charge/discharge the output capacitor Flows only on state changes IN DIGITAL MODULE GND I L GND OUT C L H H L Charge in a capacitor: Q = C*V Current I = charge moved in 1 If the capacitor is charged/discharged F times per second, that corresponds to a current flow I = F*C*V Power P D = V*I Change the voltage V on a capacitor C F time/sec requires a power P D = V*I = F*V*V*C P D = F C V 2 depends from V and C (technology!) In Val Gnd IL Gnd Out C 28/04/2009-7 DigElnB1-2009 DDC 28/04/2009-8 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 2
Static and dynamic power How to reduce power? Static power P S depends on device technology and resistive loads Low power structures: almost 0 power consumption in static conditions (no state change) Dynamic power P D depends mainly on capacitive loads (and, to a smaller exent, on device technology) Low power integrated circuits Mainly static power High speed integrated circuits Mainly dynamic power Power: P D = F C V 2 Reduce switching rate F Same number of state changes, more time» No benefit in terms of dynamic power» Actually worse: static power needed for more time Algorithms with less logic state changes Reduce capacitance C Technology improvements (smaller devices) Reduce the logic excursion V H V L A square term, heavy impact Keep noise margins (LV logic families, differential signalling) 28/04/2009-9 DigElnB1-2009 DDC 28/04/2009-10 DigElnB1-2009 DDC The speed * power product P D x T P and technology An ideal logic circuit: No power dissipation: P D = 0 No delay: T P = 0 A real logic circuit: Power and delay as low as possible P D and T P depends on parasitic capacitance C and on the charge/discharge currents of capacitors C depends on technology I is a designer s choice» High currents: high speed, high power» Low currents: low speed, low power For a given technology P D * T P product (of a single gate) is fixed» Hyperbole in the (P D, T P ) diagram The actual quality parameter for a technology is power * delay product (P D * T P ) Improving the technology Reduced C Reduced V (without impact on noise margin) Lower power dissipation Lower delay 28/04/2009-11 DigElnB1-2009 DDC 28/04/2009-12 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 3
P D x T P vs technology Power consumption in R/SW gates T P Slow circuits (high T P ) Fast circuits (low T P ) Hyperboles T P * P D = K Technology improvements Static condtitions, no load H state : SW open current = 0, power = 0» Only small leakage current L state : current = /R PU, power P S = 2 /R PU Duty cycle 50%» Current flows for 50% of the time» Average static power P S = 2 /2R PU Duty cycle D (between 0 and 1)» Average static power P S = D 2 /2R PU Slow, low power (low P D ) Fast, high power (high P D ) P D Total power consumption P T = P S + P D 28/04/2009-13 DigElnB1-2009 DDC 28/04/2009-14 DigElnB1-2009 DDC Power consumption in CMOS gates Power vs switching rate Static conditions, no load H state, L state : current = 0, power = 0» Real devices have small leakage currents Dinamic conditions P D = C F 2 Simple circuits: most of the power consumption comes from switching dynamic power Dynamic power can be limited by blocking the clock, or lowering the clock rate power Dynamic power consumption, proportional to clock rate Total power consumption Complex, last generation circuits: most of the power consumption comes from leakage (static) Strictly related to technology 0 Static power; independent from clock rate Clock rate 28/04/2009-15 DigElnB1-2009 DDC 28/04/2009-16 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 4
Power consumption trend Pass Gate - structure Logic functions which use switches in the signal path (not towards GND or Vsu) Example: 2-input multiplexer SWn closed by a 1, SWp closed by a 0» S U 0 A 1 B U = A S* + B S S A B SWp SWn U If B = A*, the logic operation is exclusive OR (XOR) 28/04/2009-17 DigElnB1-2009 DDC 28/04/2009-18 DigElnB1-2009 DDC Multiplexer with Pass Gate XOR with pass Gate pass gate 2 MOS 1 inverter Total 4 MOS B A S U = A x S + B x S* Pass gate 2 MOS 2 inverters Total 6 MOS A S U = A xor S Standard gate structure 3 x 2-input NANDs 1 inverter Total 14 MOS S B A U Standard gate structure 3 x 2-input NANDs 2 inverters Total 16 MOS A S U 28/04/2009-19 DigElnB1-2009 DDC 28/04/2009-20 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 5
Problems with pass-gate Lesson B1: logic devices Switches use pmos and nmos in parallel Lower and more linear R ON Doubles the number of devices A pass gate does not rebuild the logic levels Reduced noise margin Can be used on a single (or very few) level Interleave standard gates to rebuild logic levels Allow lower device count for some functions (see previous examples) Static power consumption Dynamic power consumption Pass gates Bipolar logic families MOS logic families Interfacing Examples of data sheets Reference 1: Storey chap 14 Reference 2: 28/04/2009-21 DigElnB1-2009 DDC 28/04/2009-22 DigElnB1-2009 DDC Logic families We have seen that different devices use different voltages ranges for their logic levels. They also differ in other characteristics. In order to assure correct operation when gates are interconnected they are produced in families. 14.3 We will look briefly at a range of logic families, then concentrate on the most important ones, namely TTL and CMOS. B1.23 Logic families The switches are built with MOS or BJT devices Logic circuits are grouped in families ICs within a family has same/compatible electrical parameters Current technology focused on C-MOS families: High speed HC Low voltage LV TTL compatible HCT ACT BCT LVT Bipolar families (LS, F, ) are becoming obsolete Mix of technologies in BiCMOS for highest speed 28/04/2009-24 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 6
74/54 logic families Examples of 74 devices COTS SSI MSI functions Label structure 74 XX NNN or 54 XX NNN 74 XX NNN standard temperature range (0-85 C, office and consumer applications) 54 XX NNN extended temperature range (-55-125 C, automotive and space applications) XX identifies sub-family (LS, F, C,...) NNN identifies the function (OR, NAND, register, ) 74F00 TTL Fast family, 4 x 2-in NAND gates 54LS04 TTL-Lowpower Shottky, 6 x inverters, extented temperature range 74ACT245 C-MOS Advanced Cmos Ttl compatible, 8 x bidirectional buffer, 74F245 Fast family, same functions and pinout as above, 28/04/2009-25 DigElnB1-2009 DDC 28/04/2009-26 DigElnB1-2009 DDC Examples of logic device pin-outs B1.27 CMOS families 14.5.4 Standard CMOS (4000B) oldest form of CMOS now largely obsolete Slow, Vdd 3-18, Very high noise immunity CMOS with TTL pin-out (74C/HC/HCT/AC/ACT/LV/ALVC/ ) High-speed CMOS (74HC) / TTL compatible inputs (74HCT) Low-voltage CMOS (74LV) Advanced, low-voltage CMOS (74ALVC) supply voltages between 1.65 and 3.6 V considerable speed advantage compared to the 74LV series BiCMOS (74BCT), low-voltage BiCMOS (74LVT) B1.28 2009 DDC - 2006 Storey 7
CMOS inputs CMOS gate protection circuitry CMOS inputs must not be left unconnected unused inputs should be tied to ground (logic 0) or to the positive supply rail (logic 1) unused inputs to an AND or NAND gate should be tied high unused inputs to an OR or NOR gate should be tied low. Input threshold depends on W/L of input MOS transistors Supply voltage Two different devices (nmos, pmos) Different processing steps Difficult to get precise parameters Wide spreading of thresholds To get precise threshold Differential inputs CMOS input threshold V I GND B1.29 28/04/2009-30 DigElnB1-2009 DDC NAND CMOS structure Complex logic nmos switches in series towards GND Output = 0 all SWn closed» Both inputs = 1 pmos switches // towards Output = 1 one SWp closed» At least one input = 0 Logic function: NAND I1 I2 U 0 0 1 0 1 1 1 0 1 1 1 0 I 1 I 2 SW P1 SW P2 SW N1 SW N2 U Get the logic function OUT = ( A* B* ) + C* + D* Apply De Morgan s OUT* = (A + B) C D Closed SW bring OUT to 0 OR (+) parallel connection AND ( ) series connection A B C D OUT A B C D H = closed 28/04/2009-31 DigElnB1-2009 DDC 28/04/2009-32 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 8
CMOS 14.5 A comparison of CMOS families CMOS part of a typical CMOS data sheet B1.33 Family Standard Standard, TTL pin-out High-speed High-speed, TTL compatible Advanced Advanced, TTL compatible Low-voltage Advanced, low-voltage BiCMOS Low-voltage BiCMOS Descriptor 4000B 74CXX 74HCXX 74HCTXX 74ACXX 74ACTXX 74LVXX 74ALVCXX 74BCTXX 74LVTXX T PD (ns) 3.5 400 B1.34 75 50 8 12 4 6 9 3 4 Static power per gate (µw) 50 50 25 25 25 25 50 50 600 Diode logic family Diode-transistor logic family A DTL NAND gate Add an active element to Diod Logic B1.35 B1.36 2009 DDC - 2006 Storey 9
Transistor-transistor logic family TTL two-input NAND gate Replacing the diodes of a DTL gate with transistors B1.37 B1.38 TTL data sheet Standard TTL part of a typical TTL data sheet 14.4 Which input voltage to turn ON T4? Follow the path from Va to GND How many junction drops? EB(T1)+BC(T1)+BE(T2)+BE(T4) total 3 1 = 2 junctions ON if Va > 1.2 V Independent from supply voltage Small spreading TTL input threshold B1.39 28/04/2009-40 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 10
TTL noise immunity Minimum Typical Maximum V IL 0.8 V IH 2.0 V OL 0.2 0.4 V OH 2.4 3.6 TTL Open Collector output use of an open collector gate with an external load noise immunity in logic 1 (high) V NIH = V OH(min) - V IH(min) = 2.4 2.0 = 0.4 V noise immunity in logic 0 (low) V NIL = V IL(max) - V OL(max) = 0.8 0.4 = 0.4 V B1.41 B1.42 Low-power TTL (74L) a 74L00 two-input NAND gate 14.4.5 High-speed TTL (74H) 74H00 two-input NAND gate Same structure as standard TTL, but higher resistor values lower currents lower power cons. lower speed Same structure as standard TTL, but lower resistor values higher currents higher power cons. higher speed B1.43 B1.44 2009 DDC - 2006 Storey 11
Schottky diodes and transistors Fast diodes and transistors, with low drop (.3 V) Schottky TTL (74S) 74S00 two-input NAND gate Same structure as standard TTL, but uses Schottky devices faster switching B1.45 B1.46 Low-power Schottky TTL (74LS) A comparison of TTL families 74LS00 two-input NAND gate Same structure as standard TTL, but combines Schottky devices with high value resistors low currents low power cons. fast switching Family Standard Low-power High-speed Schottky Advanced Schottky Low-power Schottky Advanced low-power Schottky FAST Descriptor 74XX 74LXX 74HXX 74SXX 74ASXX 74LSXX 74ALSXX 74FXX T PD (ns) 9 33 6 3 1.5 9.5 4 2.7 Power per gate (mw) 10 1 22 19 8.5 2 1 4 B1.47 B1.48 2009 DDC - 2006 Storey 12
TTL vs C-MOS Input currents: Practically 0 for MOS / CMOS circuits (only leakage; < µa) Not 0 and asymmetric for bipolar/ttl Output stage: Symmetric for CMOS Asymmetric for TTL Power consumption: Mainly dynamic for CMOS circuits (depends on switching frequency) Dynamic + static for TTL Interfacing TTL and CMOS The pullup resistor provides the proper High level Same technique for any interface with different V H 14.6 28/04/2009-49 DigElnB1-2009 DDC B1.50 TTL inputs vs CMOS inputs Emitter Coupled Logic (ECL) Unused TTL inputs left unconnected float to logical 1 If left floating, they are then very susceptible to noise Unused inputs should be tied to ground (logic 0) or to the positive supply rail (logic 1), depending on the logic function To limit input current, connect to Vcc through a resistor Unused CMOS inputs left unconnected pick static E-field, and can float to unknown state Input voltages in the transition region may damage CMOS devices (both transistors go in almost-on state high current) Even if within correct range, the logic state is undefined Never leave CMOS inputs floating Tie unused inputs to 0V or Vdd, depending on the logic function 28/04/2009-51 DigElnB1-2009 DDC A non-saturating logic gate. B1.52 2009 DDC - 2006 Storey 13
ECL gate A comparison of logic families three-input ECL OR/NOR gate Parameter TTL ECL CMOS Basic gate NAND OR/NOR NAND-NOR Fan-out 10 25 >50 Power per gate (mw) 1 22 4 55 1@1 MHz Noise immunity Very good Good Excellent T PD (ns) 1.5 33 1 4 1.5 200 B1.53 B1.54 Integration glossary Integration level Zero scale integration (ZSI) Small scale integration (SSI) Medium scale integration (MSI) Large scale integration (LSI) Very large scale integration (VLSI) Ultra large scale integration (ULSI) Giga-scale integration (GSI) Tera-scale integration (TSI) Number of transistors 1 2 30 30-10 3 10 3-10 5 10 5 10 7 10 7 10 9 10 9 10 11 10 11 10 13 Lesson B1: final test Describe static power dissipation in logic circuits. Discuss how a high speed clock can reduce power consumption. Explain the meaning of logic family Which parameters influence the threshold of CMOS logic circuits? Which parameters influence the threshold of BJT logic circuits? Which are the differences between TTL and CMOS families? B1.55 28/04/2009-56 DigElnB1-2009 DDC 2009 DDC - 2006 Storey 14