Olympus EVOLT E-410/Matsushita Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Isolation 3.8 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan View Analysis 4.3 Pixel Cross-Sectional Analysis 5 Critical Dimensions 5.1 Die 5.2 Vertical Dimensions 5.3 Horizontal Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Olympus EVOLT E-410 Camera Body 2.1.2 Olympus EVOLT E-410 Rear View 2.1.3 Olympus EVOLT E-410 Top View 2.1.4 Olympus EVOLT E-410 Bottom View 2.1.5 Olympus EVOLT E-410 Main Board 2.1.6 Olympus EVOLT E-410 Teardown View, Main Board 2.1.7 Olympus EVOLT E-410 Teardown View, LiveMOS Sensor Assembly 2.1.8 39963 LiveMOS Sensor Assembly Side View 2.1.9 39963 LiveMOS Sensor Assembly Side View X-Ray 2.1.10 39963 SSWF Dust Removal Assembly Perspective View 2.1.11 39963 LiveMOS Sensor Assembly Top 2.1.12 39963 LiveMOS Sensor Assembly Top, IR Filter Removed 2.1.13 39963 LiveMOS Sensor Assembly Bottom 2.1.14 39963 LiveMOS Sensor Assembly Top View X-Ray 2.1.15 39963 LiveMOS Sensor Assembly Top View X-Ray (IR Filter Removed) 2.1.16 39963 Die Photograph Color Filters and Microlenses Intact 2.1.17 39963 Die Photograph Color Filters and Microlenses Removed 2.1.18 Die Marking 2.1.19 39963 Die Photograph Analysis Sites 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Die Corner A Detail 2.2.6 Die Corner B Detail 2.2.7 Die Corner C Detail 2.2.8 Die Corner D Detail 2.2.9 Test Patterns A 2.2.10 Test Patterns B 2.2.11 Test Patterns C 2.2.12 Test Patterns D 2.2.13 Ribbon Cable Attachment to Bond Pads 2.2.14 Minimum Pitch Bond Pads 2.2.15 Detail of Bond Pad 2.2.16 Shift Registers 2.2.17 MOS Device
Overview 1-2 2.2.18 NOR Gate 2.2.19 RGB Bayer Patterned Color Filters Corner of Array 2.2.20 Detail of RGB Bayer Patterned Color Filters Bottom Edge of Array 2.2.21 Pixel Array Corner A 2.2.22 Pixel Array Corner B 2.2.23 Pixel Array Corner C 2.2.24 Pixel Array Corner D 3 Process Analysis 3.1.1 General View of the 39963 Periphery 3.1.2 General View of the 39963 Pixel Array 3.1.3 Die Edge 3.1.4 Die Edge SCM 3.1.5 Die Seal Ring 3.2.1 Au Stud Bond on a Bond Pad 3.2.2 Bond Pad Left Edge 3.2.3 Bond Pad Right Edge 3.3.1 Passivation 3.3.2 Passivation TEM of Five Sub Layers 3.3.3 IMD 3.3.4 PMD 3.4.1 Minimum Width Metal 2 3.4.2 Metal 2 Cap Layer Composition TEM 3.4.3 Metal 2 Barrier Layer Composition TEM 3.4.4 Minimum Pitch Metal 1 Periphery 3.4.5 Metal 1 Cap Layer Composition TEM 3.4.6 Minimum Pitch Metal 1 Pixel Array 3.5.1 Minimum Pitch Vias 3.5.2 Contacts to Poly 3.5.3 Minimum Pitch Contacts 3.6.1 Minimum Gate Length PMOS Logic Transistors 3.6.2 Minimum Gate Length NMOS Logic Transistors 3.6.3 MOS Logic Transistors (Glass Etch) 3.6.4 Minimum Width Poly (Glass Etch) 3.6.5 Minimum Gate Length NMOS Pixel Transistors 3.7.1 Minimum Width STI 3.7.2 Poly Over STI 3.8.1 Wells and Substrate SEM Cross Section 3.8.2 SCM of Peripheral N-Well, P-Wells, and N-Epi 3.8.3 SCM of Peripheral P-Wells and N-Epi 3.8.4 SRP Profile of N-Epi and N-Doped Substrate 3.8.5 SRP Profile of Peripheral P-Well Structure 3.8.6 SRP Profile of Array Well Structure
Overview 1-3 4 Pixel Analysis 4.1.1 Pixel Schematic Circuit 4.2.1 Pixel Array RBG Bayer Patterned Color Filters 4.2.2 Plan View of Pixel Array Lenses 4.2.3 Tilt View of Microlenses 4.2.4 Plan View of Pixel Array Color Filters 4.2.5 Tilt View of Pixel Array Color Filters 4.2.6 Pixel Array at Metal 2 4.2.7 Pixel at Metal 1 4.2.8 Pixel at Poly 4.2.9 Pixel at Diffusion 4.2.10 Dark Pixel Array at Metal 2 4.2.11 Dark Pixel at Metal 1 4.2.12 Dark Pixel at Poly 4.2.13 Dark Pixel at Diffusion 4.2.14 Dark Pixel to Periphery Transition at Poly 4.2.15 Plan View SCM of Buried Photocathode 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan View 4.3.2 Pixel Array Overview Away from the Edge of the Array 4.3.3 Pixel Array Away from the Edge of the Array TEM Image 4.3.4 Pixel Array Near Array Edge 4.3.5 Optical Pad Layer In Periphery 4.3.6 Lenses and Red Color Filters (P2S1) 4.3.7 Lenses and Green Color Filters (P2S1) 4.3.8 Lenses and Blue Color Filters (P2S1) 4.3.9 TEM of General Structure of Pixel ( 4.3.10 General Structure Transfer Transistor T1/T2 (P2CS1 4.3.11 General Structure T3 (P2CS1 4.3.12 General Structure T4 (P2CS1 4.3.13 General Structure T5 (P2CS1 4.3.14 T1/T2 Transfer Transistor in Detail (P2CS1 4.3.15 TEM of T1/T2 Transistor Gate, N + S/D Contact, and Metal 1 Strap (P2CS1 4.3.16 TEM of Dielectric Layer Stack Over Substrate Diffusion 4.3.17 TEM of T1/T2 Transfer Transistor Gate in Detail (P2CS1 4.3.18 TEM of Seal Layer Over STI (P2CS1 4.3.19 TEM of N + S/D Contact in Detail 4.3.20 TEM of Gate Oxide 4.3.21 T1/T2 Transfer Transistor Minimum Width (P2CS3 4.3.22 Pixel Through Transfer Transistors SCM (P2CS1 4.3.23 Pixel Through Transfer Transistors in Detail SCM
Overview 1-4 4.3.24 T3 Reset Transistor Minimum Length (P2CS1 4.3.25 T3 Reset Transistor Minimum Width (P2CS3 Parallel to Column Out) 4.3.26 T4 Source Follower Transistor Minimum Length (P2CS1 4.3.27 T4 Source Follower Transistor Minimum Width (P2CS3 Parallel to Column Out) 4.3.28 T5 Row Select Transistor Minimum Length (P2CS1 4.3.29 T4 Source Follower Transistor Minimum Width (P2CS3 Parallel to Column Out) 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 LiveMOS Image Sensor Device Summary 1.6.1 LiveMOS Image Sensor Process Summary 2 Device Overview 2.2.1 Bond Pad Dimensions 3 Process Analysis 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Minimum Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polycide Dimensions 3.7.1 STI Observed Critical Dimensions 3.8.1 Die Thickness and Well Depth 4 Pixel Analysis 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Pixel Transistor Dimensions 5 Critical Dimensions 5.1.1 Die and Bond Pad Dimensions 5.2.1 Dielectric Composition and Thicknesses 5.2.2 Metallization Composition and Thickness 5.2.3 Transistor and Polysilicon Vertical Dimension 5.2.4 STI Observed Vertical Dimension 5.2.5 Wells and Epi Vertical Dimension 5.2.6 Pixel Array Vertical Dimensions 5.3.1 Minimum Metallization Horizontal Dimensions 5.3.2 Via and Contact Horizontal Dimensions 5.3.3 Peripheral Transistor and Polycide Horizontal Dimensions 5.3.4 STI Observed Horizontal Dimensions 5.3.5 Pixel Array Horizontal Dimensions
About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: 1.613.829.0414 F: 1.613.829.0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com