Faculty of Information Engineering & Technology Electrical & Electronics Department Course: Microelectronics Lab ELCT605 Spring 2018 Dr. Eman Azab Eng. Samar Shukry Analog Report 1, 2 DC, TRANSIENT, AND AC ANALYSES ON CADENCE Submission date: Wednesday 21/3/2018 Name ID Group number Grade: 1
1) Exercise 1: Given that: R 1 = 0.7MΩ, R 2 = 0.7MΩ, R S = 4kΩ, and R D = 3kΩ, W P = 2u and L P = 900n, the bulk terminal is connected to the supply terminal. Using Cadence tool: 1. Calculate the DC operating point (I SD, V SG, V SD, V SD sat and the mode of operation) for the PMOS transistor in the above circuit. 2. Sketch the curve between the current I SD vs. the load resistance R S as a design variable. 3. Repeat step 2 but with a parametric analysis for different widths of the PMOS transistor. 2
2) Exercise 2: A C OUT B Given that: W P = W n = 6u and L P = L n = 600n, the supply voltage for the circuit above is 1.2V. The bulk terminal of all nmos devices is connected to the ground while that of all pmos devices is connected to the supply voltage terminal. 3
Using Cadence tool: 1. Build the schematic of the inverter circuit shown in the above Figure using the same width and length criteria for its nmos and pmos devices. 2. Generate the symbolic view of the inverter schematic design. 3. Use the created symbol in a new cell view and build the schematic view of the shown circuit. 4. Choose the appropriate sources for A, B, and C signals, Run the suitable analysis to extract the full truth table of the shown logic gate. Note: include the result truth table in your report. 5. Sketch the three input signals, A, B, and C together with the Out signal to verify the function implemented by the above gate. 3) Exercise 3: Using Cadence tool: 1. Use the appropriate input source to measure the gain of the above amplifier circuit. 2. Calculate its total power consumption. 4
4) Exercise 4: Vin A1 A2 A3 A4 Vout C1 C2 C3 Given that: C 1 = 1.592nF, C 2 = 198.9pF, C 3 = 79.58pF, V in is a sine source with Amplitude 1V and Frequency 1 KHz. Using the Cadence Tool: 1. Replace each of the Opamp symbol in the above circuit with its equivalent practical model where: For Opamp1: R in = 1M ohm, A 1 = 1, R out = 100 ohm For Opamp2: R in = inf., A 2 = 1, R out = 100 ohm For Opamp3: R in = inf., A 3 = 1, R out = 100 ohm For Opamp4: R in = inf., A 4 = 10000, R out = 20 ohm 2. Design the schematic view of the above circuit. 3. Generate the symbol view of the 4-stages operational amplifier design shown in Figure. 4. Create a new cell view, use the generated symbol with the given input to test the performance of the design as follows: Sketch the time domain signals of V in and V out. Use the Calculator tool to calculate the phase difference between them. 5
Sketch the gain response of the amplifier design vs. frequency. Use the Calculator to get the maximum gain provided by that amplifier. Sketch its transfer function in db. Mark its cut-off frequency/s. Measure its bandwidth. Sketch its phase response. Mark the gain crossover and phase crossover frequencies. Use the calculator to calculate the phase and gain margins of the above amplifier circuit. Note: captions are needed for all the schematic and symbolic views of the given designs throughout this report, every step on the calculator tool, and every resulting response. 6