JDT-003-2013 LOW POWER FIR FILTER ARCHITECTURE USING ACCUMULATOR BASED RADIX-2 MULTIPLIER 1 Geetha.R, II M Tech, 2 Mrs.P.Thamarai, 3 Dr.T.V.Kirankumar 1 Dept of ECE, Bharath Institute of Science and Technology 2 Asst.Professor, Dept of ECE, Bharath Institute of Science and Technology 3 HOD, Dept of ECE,Bharath Institute of Science and Technolgy geetha2004128@yahoo.co.in Abstract In this paper we present the low power FIR filter using accumulator based Radix-2 multiplier. It is mandatory for any filter designer to propose a low power multiplier as most of the power consumption of the filter occurs in multiplier unit. Hence, in this paper accumulator based Radix-2 multiplier has been proposed. Even though designing a FIR Filter is a traditional trend, achieving a low power in FIR Filter using enhanced low power technique is most concerned. The proposed multiplier achieves less power and critical path delay is low than conventional multiplier architecture. The power consumed by the adder structure is also very significant while designing a low power filter. It is found that for a 8 bit input the ripple carry adder consumes more power than carry look ahead adder. With proposed accumulator based radix-2multiplier unit and carry look ahead adder, the designed FIR Filter consumes low power than the conventional filter.the design is implemented on Altera cyclone II EP2C35F672C6. Keywords - FIR filter design. Low Power, Multiply and Accumulate. INTRODUCTION Multiplier is one of the very important hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. In this project, we worked on an efficient implementation of high speed multiplier using Radix_2, modified Booth multiplier algorithm[6][7].in this project we compare the working & the characteristics of the three multiplier by implementing each of them separately in FIR filter. The parallel multipliers like radix 2 modified booth multiplier perform the computations using lesser adders and lesser iterative steps. As a result of which they cover lesser space as compared to the serial multiplier. This is a very important criterion because in the fabrication of chips and high performance system requires components which are as small as possible. In this paper, after making comparison on power consumption between different multipliers we find that serial multipliers consume more power. So power is an important criterion there we should prefer parallel multipliers like booth multipliers to serial multipliers. The low power consumption quality of booth multiplier makes it a preferred choice in designing different circuits In this we first designed three, radix 2 modified booth multiplier algorithm.[1] We used 16 bit carry look ahead adder used for designing that multiplier. Then we designed a 4 tap delay FIR filter and in place of the multiplication and additions we implemented the components of different multipliers and adders. 95
Then we compared the working of conventional multiplier by comparing the power consumption by each of them. The result of this paper helps us to choose a better option between serial and parallel multiplier in fabricating different systems. Multipliers form one of the most important components of many systems. Analyzing the working of different multipliers helps to frame a better system with less power consumption and lesser area. The result of this paper helps us to make a proper choice of different multipliers in fabricating in different arithmetic units as well as making a choice among different adders in different digital applications according to requirements.[3] All the programs and results have been given in the following sections. OVERVIEW OF MAC In this section, basic MAC operation is introduced. A multiplier can be divided into three operational steps. The first is radix-2 Booth encoding in which a partial product is generated from the multiplicand and the multiplier. The second is adder array or partial product compression to add all partial products and convert them into the form of sum and carry. The last is the final addition in which the final multiplication result is produced by adding the sum and the carry. General hardware architecture of this MAC is shown in Fig 1. It executes the multiplication operation by multiplying the input multiplier and the multiplicand. This is added to the previous multiplication result as the accumulation[11] Fig.1. MAC Architecture PROPOSED MAC ARCHITECTURE In the majority of digital signal processing (DSP) applications the critical operations usually involve many multiplications and/or accumulations. For real-time signal processing, a high speed and high throughput Multiplier-Accumulator (MAC) is always a key to achieve a high performance digital signal processing system. In the last few years, the main consideration of MAC design is to enhance its speed. This is because; speed and throughput rate is always the concern of digital signal processing system. But for the epoch of personal communication, low power design also becomes another main design consideration. This is because; battery energy available for these portable products limits the power consumption of the system[4]. Therefore, the main motivation of this work is to investigate various Pipelined multiplier/accumulator architectures and circuit design techniques which are suitable for implementing high throughput signal processing algorithms and at the same time achieve low power consumption. A conventional MAC unit consists of (fast multiplier) multiplier and an accumulator that contains the sum of the previous consecutive products. The function of the MAC unit is given by the following equation: F= ΣAiBi (1) The main goal of a DSP processor design is to enhance the speed of the MAC unit, 96
and at the same time limit the power consumption. In a pipelined MAC circuit, the delay of pipeline stage is the delay of a 1-bit full adder. Estimating this delay will assist in identifying the overall delay of the pipelined MAC. In this work, 1-bit full adder is designed. Area, power and delay are calculated for the full adder, MAC unit is designed for low power. High-Speed Booth Encoded Parallel Multiplier Design Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. In the past multiplication was generally implemented via a sequence of addition, subtraction, and shift operations. Multiplication can be considered as a series of repeated additions. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. In most computers, the operand usually contains the same number of bits. When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one collects and adds them. The basic multiplication principle is two fold i.e. evaluation of partial products and accumulation of the shifted partial products. It is performed by the successive additions of the columns of the shifted partial product matrix. The multiplier is successfully shifted and gates the appropriate bit of the multiplicand. The delayed, gated instance of the multiplicand must all be in the same column of the shifted partial product matrix. They are then added to form the product bit for the particular form. Multiplication is therefore a multi operand operation. To extend the multiplication to both signed and unsigned.[11][12] Modified Booth Encoder: In order to achieve high-speed multiplication, multiplication algorithms using parallel counters, such as the modified Booth algorithm has been proposed, and some multipliers based on the algorithms have been implemented for practical use. This type of multiplier operates much faster than an array multiplier for longer operands because its computation time is proportional to the logarithm of the word length of operands. Booth multiplication is a technique that allows for smaller, faster multiplication circuits, by recoding the numbers that are multiplied. It is possible to reduce the number of partial products by using the technique of radix-2booth recoding. The basic idea is that, instead of shifting and adding for every column of the multiplier term and multiplying by 1 or 0, we only take every second column, and multiply by ±1, or 0, to obtain the same results. [4][10][12]The advantage of this method is the to reduce the number of partial products. To Booth encode the multiplier term, we consider the bits in blocks of three, such that each block overlaps the previous block by one bit. Grouping starts from the LSB, and the first block only uses two bits of the multiplier. Each block is decoded to generate the correct partial product. The encoding of the multiplier Y, using the 97
modified booth algorithm, generates the following five signed digits, -1, 0, +1, Each encoded digit in the multiplier performs a certain operation on the multiplicand, X proposed FIR filter ArchitectureRadix-2 booth multiplier is used to implement FIR filter. In this we perform all our optimization in multiplier. Here the multiplications are divided into additions and shifts. Hence the complexity of multiplication is reduced. The coefficients in most of digital signal processing applications for the multiply accumulate operation are constants. In this method, first we arrange decimal coefficients according to positive and negative powers of two. Because of this, the hardware complexity of finite impulse response filter and the power consumption will be reduced. A finite impulse response (FIR) filter is a filter structure that can be used to implement almost any sort of frequency response digitally. An FIR filter is usually implemented by using a series of delays, multipliers, and adders to create the filter's output. Figure 2 shows the basic block Fig.2. Direct form of FIR fil ter Architecture RESULTS AND COMPARISIONS Designs equipped to 16 bit carry look ahead adder, 8 bit Radix-2 booth multipliers and are accomplished via Verilog hardware description language and synthesized using Altera cyclone II EP2C35F672C6. The simulation and RTL schematic of proposed FIR filter Architecture shown in fig.3 and fig4 98
Fig.3. Simulation waveform of fir filter architecture Table 1 Proposed FIR filter Architecture Description Proposed FIR using Radix-2 Mul Conventional FIR using normal Mul Power(nw) Delay(ns) 113.01 2.380 114.07 2.480 Table 1 depicts the synthesis results of the proposed FIR filter architecture when implemented on Altera cyclone II EP2C35F672C6 FPGA. The power consumption of proposed fir filter implemented using accumulator based radix-2 multiplier achieves low power than conventional architecture. CONCLUSION In this paper a low power and low area digital FIR filter is presented. For reduce power consumption and area we using radix2 booth multiplier These filters are compared for power. The proposed FIR filters have been synthesized and implemented using Altera cyclone II EP2C35F672C6 FPGA. REFERENCES 1. A. Avizienis. Signed-digit number representation for fast parallel arithmetic, in IRE Transactions on 99
Electronic Computers, vol. EC-10, no. 9, pp. 389-400, Sept. 1969. 2. [M.Kameyama, T.Sekibe, and T.Higuchi, Highly Parallel Residue Arithmetic Chip Based on Multiple- Valued Bidirectionakl Current- Mode Logic, IEEE J. of Solid-State Circuits, vol. 24(5), Oct. 1989, pp. 1404-1411 3. S. Wei and K. Shimizu. A Novel Residue Arithmetic Hardware Algorithm Using a Signed-Digit Number Representation, in IEICE Trans. Inf. and Syst, vol. E83-D, no. 12, pp. 2056-2064, Dec. 2000. 4. A. Lindström, M. Nordseth, L. Bengtsson, VHDL Library of Nonstandard Arithmetic Units. [Online]. Available: http:// www.ce.chalmers.se/arithdb/, Mars 2003. 5. R.Zimmermann. VHDL Library of Arithmetic Units.[Online]. Available: http://www.iis.ethz.ch/~zimmi/arith_li b/, Sept. 1998. 6. Lindström, M. Nordseth, L. Bengtsson,, A. Omondi. Arithmetic Circuits Combining Residue and Signed-Digit Representations In Lecture Notes in Computer Science (LNCS), vol. 2823, pp. 246-257, Aizu-Wakamatsu, Japan, Sept. 2003. Springer-Verlag. 7. R. Conway, J. Nelson. Improved RNS FIR Filter Architectures, in IEEE Transactions on Circuits & Systems-II, vol. 51, no. 1, pp. 26-28, Jan. 2004. 8. A. Nannarelli, M. Re and C. G. Cardarilli. Tradeoffs Between Residue Number System and Traditional FIR Filters, in Proceedings of 2001 IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 305-308, May 2001. 9. A. Del Re, A. Nannarelli and M. Re. Implementation of Digital Filters in Carry-Save Residue Number System, in Record of 35th Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 1309-1313, Nov. 2001. 10. G.C. Cardarilli, A. Del Re, A. Nannarelli, M. Re, Low-power implementation of polyphase filters in Quadratic Residue Number system, Proceedings of the 2004 International Symposium on Circuits and Systems, Volume: 2, pp.725-8, 23-26 May 2004. 11.A.D. Booth, A Signed Binary Multiplication Technique, Quarterly J. Mechanics and Applied Mathematics, Vol. 4, No. 2, p.236, 1951. 12 Young-Ho Seo and Dong-Wook Kim, A New VLSI Architecture of parallel multiplier Accumlator Based on Radix-2 Modified Booth Algorithm, IEEE Transactions on VLSI Systems, Vol.18, No.2, Feb 2010. 100