LOW POWER HIGH SPEED MODIFIED SQRT DESIGN USING D-LATCH & BK ADDER Athira.V.S 1, Shankari. C 2, R. Arun Sekar 3 1 (PG Student, Department of ECE, SNS College of Technology, Coimbatore-35, India, athira.sudhakaran.39@gmail.com) 2 (PG Student, Department of ECE, SNS College of Technology, Coimbatore-35, India, shankarisindhu6@gmail.com) 3 (Assistant Professor, Department of ECE, SNS College of Technology, Coimbatore-35, India, rarunsekar007@gmail.com) Abstract The basic building blocks of any processor is adders. In VLSI design the adders used as fundamental requirements to achieve high performance processors and multi-core devices. To acquire fast arithmetic functions in many processors, fastest adder carry select adder is used. Conventional designs like Modified SQRT (M) and Binary to Excess one Converter (BEC) based and are compared with proposed D-latch and Brent Kung based, which shows better performance in terms of delay and power. In this paper 16 bit carry select adder with different models have been analyzed based on parameters like speed, area of utilization and power. The design is written in Verilog Hardware Description Language (HDL) and synthesized using Xilinx ISE 14.5. Keywords Ripple Carry Adder (RCA); Carry Select Adder; Square Root ; Modified SQRT ; Brent Kung based Modified SQRT and D-latch Carry select adder 1. INTRODUCTION The three important parameters for designing digital circuits are area, power and speed. Adder is the basic unit of any arithmetic operation. Its performance affects the total system. In modern electronics requires the design of VLSI circuits with less delay, low power and less area that will be very useful for portable and mobile devices. These factors are modified to get an efficient design based on the applications [5]. Adders are used as the fundamental units of the digital signal processors and their design is important. There are different adder circuits are designed that gives which adder has the better performance. The design of ripple carry adder is simple but the major disadvantage is high propagation delay. The propagation delay will be increases with size of bit. The propagation delay will be effectively reduced with help of carry select adder. A regular carry select adder () is an RCA-RCA combination [10] that generates a pair of sum and carry outputs corresponding to the carry input Cin= 0 and Cin=1. Multiplexer is used to select one of the final sum and carry output. Conventional carry select adder uses dual RCA s, then the design is not more attractive. In speed will be obtained with the dues of area. In order to overcome this defect the BEC based modified SQRT is used. It replaces one RCA of Cin=1 with BEC circuit. Hence the area will be reduced. The BEC based modified SQRT uses less number of logic units but their routing delay is a little higher than the regular [11]. To achieve high speed and low power consumption, RCA of Cin=1 replaced with BEC and RCA of Cin=0 is replaced by parallel prefix adder, i.e Brent Kung Adder. In order to achieves more efficiency for battery life of electronics equipment the important factors like power consumption and area have to reduce. The goal of this paper is to replace the ripple carry of Cin=1 using D-latch in the conventional to accomplish High speed, less area and low power consumption. The main advantage of using D- Latch logic is High Speed than the n-bit full adder structure. The power consumption and delay of Modified Square root carry select adder reduced by replacing the two RCA s by using Brent Kung adder and D-latch. 2. EXISTING SYSTEM A. Square root carry select adder FIG 1: BLOCK DIAGRAM OF 16-BIT SQUARE ROOT CARRY SELECT ADDER The fastest adder used in many processors is Square root carry select adder and it is also used for fast arithmetic functions [8]. The main problem in many system is propagation delay of carry and that will solve by generating the carries and sum independently and sum is generated by selecting one of the carry. A consists of a number of blocks each run with a pair of ripple carry adder chain in parallel [1]. The 16 bit slices of a carry select adder are divided into different length bit. In SQRT additions of two blocks are performed in parallel. Each block is evaluated by using carry-input value 0 and 1. When the carry input value to a block has been assigned its final value, then it is used to select the sum bits from one of the two blocks. At this time, the block carry output value can also be calculated, Volume: 04 Issue: 08 2017 www.ijmtes.com 13
which is used to select the sum bits and carry output value of the next block. The 16 bit adder block consists of RCA. In case of dual RCA based SQRT a duplicate chain is used for addition cost of carry select adder over ripple carry adder. The critical path for carry select adder is the longer because of carry select chain. Figure 1 shows block diagram of 16 bits SQRT which consists of two RCA s in each block, one for Cin=0 and other for Cin=1, which having 5 groups of different size. By the use dual ripple carry structure consumes more area in SQRT. B. Modified carry select adder BEC-1 is one of the combinational circuits that used for incrementing the input by one. The output of RCA with Cin=0 is the input to the BEC-1. Thus, it replaces the RCA in the SQRT with Cin=1. By using BEC-1, RCA- RCA configuration in the regular SQRT is eliminated [3]. BEC-1 adopts one extra bit than the bits used in RCA. The multiplexer collects two inputs, one is from RCA with Cin=0 and other one from BEC-1. According to the bit position multiplexer selects the appropriate input signal. The control signal of multiplexer is the previous carry output of the adder. The figure 2 shows the block diagram of 16 bit modified SQRT and it is divided into 5 groups of RCA and BEC with variable order of bit size. FIG 2: BLOCK DIAGRAM OF 16-BIT MODIFIED SQUARE ROOT CARRY SELECT ADDER Group 1 composed of only one RCA block of 2 bit size, which gives 2 bit output sum and carry out. The next coming groups consist of combination of 2 blocks of variable bits. One is RCA with Cin=0 and other is BEC block [9]. The multiplexer receives two outputs, one comes from the RCA block and other output from the BEC. If the carry=0 then output is chosen from RCA block and if previous carry=1 then the output is chosen from BEC block with the help of multiplexer. the multiplexers which select either BEC output or RCA output. The equations of 4 bit BEC is listed below: E0=~D0 E1=D0^D1 E2=D2^ (D0&D1) E3=D3^ (D0&D1&D2) E=Excess-1 output D=Binary input FIG 3: CIRCUIT DIAGRAM OF 4- BIT BINARY TO EXCESS-1 CODE CONVERTER TABLE 1: 4-BIT BINARY TO EXCESS-1 CONVERTER TRUTH TABLE BINARY LOGIC D3 D2 D1 D0 EXCESS-1 LOGIC E3 E2 E1 E0 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 011 1 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0000 The main idea of modified SQRT is to replace RCA with Cin=1 and places BEC in order to achieve minimum area utilization and low power consumption [12]. One extra bit BEC circuit is needed for N-bit RCA. The Modified designed for higher number of bits achieving less silicon area by replacing the RCA with Cin=1 by BEC. Binary to excess-1 converter BEC-1 is one of the combinational circuits used to add the input numbers with one. The 4 bit binary to excess-1 converter is shown in figure 3. The multiplexer with BEC configuration is used for achieving addition process and the multiplexer-bec combination is shown in figure 4. The BEC input and output are the two inputs of 8:4 multiplexer [6]. This combination gives the two partial results in parallel and FIG 4: 4-BIT BINARY TO EXCESS-1 LOGIC WITH 8:4 MULTIPLEXER Volume: 04 Issue: 08 2017 www.ijmtes.com 14
B. Modified Brent Kung carry select adder Parallel Prefix Adder In order to get the high speed binary additions one of the fastest adders such as parallel prefix adder is used. The basic structure of Parallel prefix adders comes in from CLA structure. The parallel prefix adder tree structure helps to fastest addition. Parallel prefix are used for high performance arithmetic circuits in industries. Three main steps are used for composition of parallel prefix adder: stages are loading in asymmetric manner [2]. The main advantage of bk adder is cost and wiring complexity gets reduced, but the logic depth of Brent-Kung adders increases to 2log (2n-1), so BK adder has low power with small penalty of speed. The 4 bit Brent Kung Adder block diagram is shown in figure 6. 1. Generate and propagate signal computation 2. Calculation of intermediate signals 3. Final sum and carry signal calculation Generate and propagate signal computation: two input A and B are used to calculate the propagate and generate signals. The propagate signal calculate the previous carry to the next bit and generate signal helps to generate carry bit. The equation of generate and propagate signal are given in (1) & (2): Pn= An Bn... (1) Gn=An. Bn... (2) Calculation of intermediate signal: Calculate carry of generate and propagate signal for each bit [4]. The operation is carried out in parallel and equation is given in (3) & (4): CPin=Pcurrent. Ppreview... (3) CGin=Gcurrent + (Pcurrent. Gpreview)... (4) FIG 6: 4 BIT BK ADDER BLOCK DIAGRAM FIG 5: CARRY NETWORK CP0=Pi and Pj... (4) CG0= (Pi and Gj) or Gi... (5) Final sum and carry signal calculation: In final step, the sum and carry output is calculated and equations are given in (6) & (7): Cn=(Pn. Cpreview) + Gn... (6) Sn=Pn Cpreview... (7) Brent Kung Adder One of the parallel prefix adder such as Brent Kung Adder which gives propagate and generate signals. Tree structure of Brent Kung adder gives the minimal number of gates from its input to outputs. In Brent Kung adder al the intermediate FIG 7: 16 BIT MODIFIED SQUARE ROOT BK BLOCK DIAGRAM The is modified by using Brent Kung Adder in Cin=0 and BEC in Cin=1. It contains 5 groups of different bit size of BK adder and each group consist the combination of multiplexer, BEC and Brent Kung adder. One extra bit BEC circuit is needed for N bit Brent Kung adder and BEC circuit is used to add one to the input bit. The main advantage of Modified BK compared to conventional is less area utilization because minimum numbers of logic gates are used. Modified BK block diagram is shown in figure 7. 3. PROPOSED CARRY SELECT ADDER The proposed Modified carry select adder use D- latch with clock signal instead of BEC circuit as shown in figure 8. Latches are used to store one bit information. When the enable input is on, the signal directs through the circuit, from the input D to the output Q. The D-latch circuit is shown in figure 9. The 16-bit proposed adder in which LSB adder is Brent Kung Adder, which is 2-bit size. Volume: 04 Issue: 08 2017 www.ijmtes.com 15
FIG 8: BLOCK DIAGRAM OF 16-BIT PROPOSED CARRY SELECT ADDER Proposed adder works depend to the enable input. When the clock goes high, the carry input is assumed as one and addition is performed [7]. Carry input assumed as zero when clock goes low and sum output from BK is stored in the adder. Multiplexer to select the final sum and carry output of the adder and carry output from previous stage used as control signal. The proposed adder group2 inward architecture is shown in the figure 10. The group 2 consist the 2 bit size and addition is performed. This addition is done by using two full adders FA2 and FA3. The third input to the FA2 is the clock signal and carry output of FA2 is same as the carry input of FA3. Out of three D-latches two is used to store the sum from both FA2 and FA3 and the third D-latch is used to store carry output from FA3. Depend on the previous carry multiplexer select the output sum and carry. In group2 architecture three 2:1 multiplexer combines to form the 6:3 multiplexer. FIG 9: D-LATCH STRUCTURE FIG 10: INTERNAL STRUCTURE OF GROUP 2 4. SIMULATION AND RESULT COMPARISON Modified Square Root Carry Select Adder using BK and D- latch is designed by replacing BEC and BK adder and D- latch combination is used in order to minimize the power consumption and delay. Out of parallel prefix adder Brent Kung Adder is the efficient adder and which helps to minimize the area utilization, delay and power consumption. The synthesized result shows that delay and power consumption of Modified SQRT using D-latch and BK adder is reduced in comparison to other architectures. The design is written in Verilog Hardware Description Language (HDL) and synthesized and using Xilinx ISE 14.5. The eight different models of carry select adder are designed for 16 bit and can be extended for higher number of bit. The result shows that proposed carry select adder gives improved performance in terms of power consumption and delay and it can be used in multipliers and digital signal applications such as Finite Impulse Response. FIG 11: SIMULATION OF 256 BIT SQUARE ROOT CARRY SELECT ADDER USING D-LATCH AND BK ADDER TABLE 2: COMPARISON OF AREA, POWER AND DELAY OF DIFFERENT CARRY SELECT ADDERS ADDER POWER(w) AREA DELAY(ns) (LUT S) Regular carry 0.081 41 17.413 select adder Square root 0.078 43 16.644 Modified 0.069 48 17.131 Regular 0.065 64 15.627 linear BK Linear 0.063 61 16.996 modified BK Regular 0.059 58 15.024 BK Modified 0.054 60 13.737 BK Proposed 0.052 50 12.147 Table 2 shows the comparison of existing and proposed in terms of power, area and delay. Also plotted is the percentage delay and power reduced of the new design of CSA using D latch when compared to other CSA. It is clear that the power consumption of the modified SQRT is reduced by 11.53% when compared to regular SQRT. Volume: 04 Issue: 08 2017 www.ijmtes.com 16
Delay of SQRT is reduced to 4.42% when compared to regular. The power consumption and delay of modified SQRT BK is reduced to 21.74% and 19.81% respectively when compared to modified SQRT. The compared results show that the proposed modified SQRT has a slightly larger area, but the power consumption and delay of proposed carry select adder is reduced by 11.57% and 3.7% respectively when compared to modified SQRT BK. 5. CONCLUSION A carry select adder consists of two carry appraisement block one with carry input is zero and another with carry input one. Main drawback of the regular SQRT is the more usage of chip area. In this work, proposed carry select adder is designed using BK adder and D-latch instead of RCA and BEC. The proposed system minimizes the delay and power consumption by using d-latch and BK adder as compared to different architecture of. REFERENCES [1] G. Karthik Reddy, D. Sharat Babu Rao, A Comparative Study on Low Power and High Speed Carry Select Adder, IEEE Sponsored 9th International Conference on Intelligent System and Control (ISCO), 2015. [2] Pallavi Saxena, Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder, International Conference on VLSI Systems, Architecture, Technology and Applications, 2015. [3] Shivani Pamar, Kirat Pal Singh, Design of High Speed Hybrid Carry Select Adder, IEEE 3rd International Advance Computing Conference, 2013. [4] Adilakshmi Silveru, M. Bharati, Design of Kogg Stone and Brent Kung Adders using Degenerate Pass Transistor Logic, International Journal of Engineering Science and Engineering, 2013. [5] K. Saranya, Low Power and Area Efficient Carry Select Adder, International Journal of Soft Computing and Engineering, vol-2, issue-6, 2013. [6] Sudhanshu Shekhar, Amit Bakshi, Vikash Sharma, 128 Bit Low Power Area Efficient Carry Select, International Journal of Computer Applications, 2013. [7] J. Pravin Adlin, C. Palaniapan, An Area Delay Efficient Architecture IOSR Journal of Electronics and Communication Engineering, 2013. [8] B. Ramkumar and Harish M Kittur, Low Power and Area Efficient Carry Select Adder, IEEE Transaction on Very Large Scale Integration System, 2012. [9] P. Saxena, Design of Low Power Adder using Brent Kung Adder, International Conference on VLSI Systems, Architecture, Technology and Applications, pp. 1-6, 2015. [10] J. Eric Clapten, E. Konguvel, M. Thangamani, VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder, International Journal of Computer Applications, Vol.115, issue 6, pp. 5-8,2015. [11] B. K. Mohanty, S. K. Patel, Area Delay Power Efficient Carry Select Adder, IEEE Transactions on Circuits and Systems-II, vol. 61, issue 6, pp. 418-422, 2014. [12] Y. D. Ykuntam, M. V. N. Rao, G. R. Locharla, Design of 32 bit Carry Select Adder with Reduced Area, International Journal of Computer Applications, Vol. 75, issue 2, pp. 47-51, 2013. Volume: 04 Issue: 08 2017 www.ijmtes.com 17