Semiconductor ugust 1997 MOS 2 Microsecond, 12-it, Sampling /D onverter with Internal Track and Hold Features Description onversion Time........................... 2µs Throughput Rate........................5 KSPS uilt-in Track and Hold Guaranteed No Missing odes Over Temperature Single Supply Voltage........................+5V Maximum Power onsumption...............25mw Internal or External lock pplications Remote Low Power Data cquisition Systems Digital udio DSP Modems General Purpose DSP Front End µp ontrolled Measurement System Professional udio Positioner/Fader The is a fast, low power, 12-bit, successive approximation analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws just 1.9m when operating at 5V. The features a built-in track and hold. The conversion time is as low as 15µs with a 5V supply. The twelve data outputs feature full high speed MOS threestate bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable: (i.e.) 12- bit, 8-bit (MSs), and/or 4-bit (LSs). data ready flag, and conversion-start inputs complete the digital interface. n internal clock is provided and is available as an output. The clock may also be over-driven by an external source. Ordering Information PRT NUMER INL (LS) (MX OVER TEMP.) TEMP. RNGE ( o ) PKGE PKG. NO. JIP ±1.5-4 to 85 24 Ld PDIP E24.3 KIP ±1. -4 to 85 24 Ld PDIP E24.3 JI ±1.5-4 to 85 24 Ld SOI M24.3 KI ±1. -4 to 85 24 Ld SOI M24.3 JIJ ±1.5-4 to 85 24 Ld ERDIP F24.3 KIJ ±1. -4 to 85 24 Ld ERDIP F24.3 Pinout (PDIP, ERDIP, SOI) TOP VIEW 1 24 V DD (LS) D 2 23 OEL D1 3 22 D2 4 21 D3 5 2 V REF - D4 6 19 V REF + D5 7 18 D6 8 17 V + D7 9 16 V - D8 1 15 OEM D9 11 14 D11 (MS) V SS 12 13 D1 UTION: These devices are sensitive to electrostatic discharge. Users should follow proper I Handling Procedures. opyright Harris orporation 1997 6-1789 File Number 3214.4
Functional lock Diagram V DD V SS TO INTERNL LOGI 32 ONTROL + TIMING LOK V REF + 5Ω SUSTRTE 16 8 4 OEM D11 (MS) D1 V + 2 D9 D8 V - 64 63 32 16 8 4 12-IT SUESSIVE PPROXIMTION REGISTER 12-IT EDGE TRIGGERED D LTHED D7 D6 D5 2 D4 P1 D3 D2 V REF - D1 D (LS) OEL 6-179
bsolute Maximum Ratings Supply Voltage V DD to V SS....................(V SS -.5V) < V DD < +6.5V V + to V -.................... (V SS -.5V) to (V SS +6.5V) V + to V DD.................................... ±.3V nalog and Reference Inputs, V REF +, V REF -......... (V SS -.3V) < < (V DD +.3V) Digital I/O Pins.............. (V SS -.3V) < VI/O < (V DD +.3V) Operating onditions Temperature Range PDIP, SOI, and ERDIP Packages............. -4 o to 85 o Thermal Information Thermal Resistance (Typical, Note 1) θ J ( o /W) θ J ( o /W) ERDIP Package................ 6 12 PDIP Package................... 8 N/ SOI Package................... 75 N/ Maximum Junction Temperature Plastic Packages................................. 15 o eramic Package................................ 175 o Maximum Storage Temperature Range..........-65 ο to 15 o Maximum Lead Temperature (Soldering, 1s)............ 3 o (SOI - Lead Tips Only) UTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θ J is measured with the component mounted on an evaluation P board in free air. Electrical Specifications V DD = V + = 5V, V REF + = +4.68V, V SS = V - = V REF - = GND, = External 75kHz, Unless Otherwise Specified 25 o -4 o TO 85 o PRMETER TEST ONDITIONS MIN TYP MX MIN MX UNITS URY Resolution 12 - - 12 - its Integral Linearity Error, INL J - - ±1.5 - ±1.5 LS (End Point) K - - ±1. - ±1. LS Differential Linearity Error, DNL J - - ±2. - ±2. LS K - - ±1. - ±1. LS Gain Error, FSE J - - ±3. - ±3. LS (djustable to Zero) K - - ±2.5 - ±2.5 LS Offset Error, V OS J - - ±2. - ±2. LS (djustable to Zero) K - - ±1. - ±1. LS Power Supply Rejection, PSRR Offset Error PSRR Gain Error PSRR DYNMI HRTERISTIS Signal to Noise Ratio, SIND RMS Signal RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal RMS Noise J K J V REF = 4V V DD = V + = 5V ±5% V DD = V + = 5V ±5% f S = Internal lock, f IN = 1kHz f S = Internal lock, f IN = 1kHz f S = Internal lock, f IN = 1kHz f S = Internal lock, f IN = 1kHz Total Harmonic Distortion, THD J f S = Internal lock, f IN = 1kHz K f S = Internal lock, f IN = 1kHz Spurious Free Dynamic Range, SFDR K J K f S =Internal lock, f IN = 1kHz f S = Internal lock, f IN = 1kHz.1.1-68.8 69.2-71. 71.5-7.5 71.1-71.5 72.1 - -73.9-73.8-8.3-79. - -75.4-75.1 - -8.9-79.6 ±.5 ±.5 ±.5 ±.5 LS LS - - - d d - - - d d - - - d d - - - d d - - - dc dc - - - dc dc - - - d d - - - d d 6-1791
Electrical Specifications V DD = V + = 5V, V REF + = +4.68V, V SS = V - = V REF - = GND, = External 75kHz, Unless Otherwise Specified (ontinued) PRMETER TEST ONDITIONS 25 o -4 o TO 85 o MIN TYP MX MIN MX NLOG INPUT Input urrent, Dynamic t = V REF +, V - ±5 ±1 - ±1 µ Input urrent, Static onversion Stopped - ±.4 ±1 - ±1 µ Input andwidth -3d - 1 - - - MHz Reference Input urrent - 16 - - - µ Input Series Resistance, R S In Series with Input SMPLE - 42 - - - Ω Input apacitance, SMPLE During Sample State - 38 - - - pf Input apacitance, HOLD During Hold State - 2 - - - pf DIGITL INPUTS OEL, OEM, High-Level Input Voltage, V IH 2.4 - - 2.4 - V Low-Level Input Voltage, V IL - -.8 -.8 V Input Leakage urrent, I IL Except, = V, 5V - - ±1 - ±1 µ Input apacitance, IN - 1 - - - pf DIGITL OUTPUTS High-Level Output Voltage, V OH I SOURE = -4µ 4.6 - - 4.6 - V Low-Level Output Voltage, V OL I SINK = 1.6m - -.4 -.4 V Three-State Leakage, I OZ Except, V OUT = V, 5V - - ±1 - ±1 µ Output apacitance, OUT Except - 2 - - - pf LOK High-Level Output Voltage, V OH I SOURE = -1µ (Note 2) 4 - - 4 - V Low-Level Output Voltage, V OL I SINK = 1µ (Note 2) - - 1-1 V Input urrent Only, = V, 5V - - ±5 - ±5 m TIMING onversion Time (t ONV + t Q ) (Includes cquisition Time) 2 - - 2 - µs lock Frequency Internal lock, ( = Open) 2 3 4 15 5 khz External (Note 2).5 2 1.5.5 1.5 MHz lock Pulse Width, t LOW, t HIGH External (Note 2) 1 - - 1 - ns perture Delay, t D PR (Note 2) - 35 5-7 ns lock to Data Ready Delay, t D1 (Note 2) - 15 15-18 ns lock to Data Ready Delay, t D2 (Note 2) - 1 16-195 ns Start Removal Time, t R (Note 2) 75 3-75 - ns Start Setup Time, t SU (Note 2) 85 6-1 - ns Start Pulse Width, t W (Note 2) 1 4-15 - ns Start to Data Ready Delay, t D3 (Note 2) - 65 15-12 ns lock Delay from Start, t D (Note 2) - 6 - - - ns Output Enable Delay, t EN (Note 2) - 2 3-5 ns Output Disabled Delay, t DIS (Note 2) - 8 95-12 ns POWER SUPPLY HRTERISTIS Supply urrent, I DD + I - 1.9 5-8 m NOTE: 2. Parameter guaranteed by design or characterization, not production tested. UNITS 6-1792
Timing Diagrams 1 2 3 4 5-14 15 1 2 3 (EXTERNL OR INTERNL) t D1 t LOW t D2 t HIGH D - D11 DT N - 1 DT N HOLD N TRK N TRK N + 1 OEL = OEM = V SS FIGURE 1. ONTINUOUS ONVERSION MODE (EXTERNL) 15 1 2 2 2 3 4 5 t R t SU t W t D3 HOLD TRK HOLD FIGURE 2. SINGLE SHOT MODE EXTERNL LOK 6-1793
Timing Diagrams (ontinued) (INTERNL) 15 1 2 3 4 5 t R t D t W DON T RE t D3 HOLD TRK HOLD FIGURE 3. SINGLE SHOT MODE INTERNL LOK OEL OR OEM t EN t DIS 1.6m D - D3 OR D4 - D11 HIGH IMPEDNE TO HIGH HIGH IMPEDNE TO LOW 5% 5% 9% 1% TO OUTPUT PIN 5pF -1.6m +2.1V FIGURE 4. FIGURE 4. FIGURE 4. OUTPUT ENLE/DISLE TIMING DIGRM 1.6m 5pF +2.1V -4µ FIGURE 5. GENERL TIMING LOD IRUIT 6-1794
Typical Performance urves 1..75 V DD = V + = 5V, V REF + = 4.68V 1.5 V DD = V + = 5V V REF + = 4.68V. = INTERNL. = 75kHz. = 1MHz INL ERROR (LSs).5.25. = INTERNL. = 75kHz. = 1MHz -6-4 -2 2 4 6 8 1 12 14 TEMPERTURE ( o ) V OS ERROR (LSs) 1.5-6 -4-2 2 4 6 8 1 12 14 TEMPERTURE ( o ) FIGURE 6. INL vs TEMPERTURE FIGURE 7. OFFSET VOLTGE vs TEMPERTURE 1. V DD = V + = 5V, V REF + = 4.68V 2 V DD = V + = 5V, T = 25 o = 75kHz.75 1.5 DNL ERROR (LSs).5.25. = INTERNL. = 75kHz. = 1MHz -6-4 -2 2 4 6 8 1 12 14 TEMPERTURE ( o ) ERROR (LSs) 1.5 FSE DNL INL V OS 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 REFERENE VOLTGE, V REF (V) FIGURE 8. DNL vs TEMPERTURE FIGURE 9. URY vs REFERENE VOLTGE FSE ERROR (LSs) 2 1.5 1.5 V DD = V + = 5V, V REF + = 4.68V. = INTERNL. = 75kHz. = 1MHz PSRR (LSs).5.375.25.125 V DD = V + = 5V ±5% = 75kHz V REF + = 4.V PSRR V OS -6-4 -2 2 4 6 8 1 12 14 TEMPERTURE ( o ) PSRR FSE -6-4 -2 2 4 6 8 1 12 14 TEMPERTURE ( o ) FIGURE 1. FULL SLE ERROR vs TEMPERTURE FIGURE 11. POWER SUPPLY REJETION vs TEMPERTURE 6-1795
Typical Performance urves (ontinued) SUPPLY URRENT, I DD (m) 8 V DD = V + = 5V, V REF + = 4.68V 7 6 5 4 3 INTERNL LOK 2 1-6 -4-2 2 4 6 8 1 12 14 TEMPERTURE ( o ) FIGURE 12. SUPPLY URRENT vs TEMPERTURE MPLITUDE (d). INPUT FREQUENY = 1kHz -1. SMPLING RTE = 5kHz -2. SNR = 72.1d -3. SIND = 71.4d EFFETIVE ITS = 11.5-4. THD = -79.1dc -5. PEK NOISE = -8.9d -6. SFDR = -8.9d -7. -8. -9. -1. -11. -12. -13. -14. 5 1 15 2 FREQUENY INS FIGURE 13. FFT SPETRUM INTERNL LOK FREQUENY (khz) 5 V DD = V + = 5V, V REF + = 4.68V 45 4 35 3 25 2 15-6 -4-2 2 4 6 8 1 12 14 ENO (ITS) 12 11 1 V DD = V + = 5V V REF + = 4.68V 9 T = 25 o. = INTERNL 8. = 75kHz. = 1MHz 7.1 1 1 1 TEMPERTURE ( o ) INPUT FREQUENY (khz) FIGURE 14. INTERNL LOK FREQUENY vs TEMPERTURE FIGURE 15. EFFETIVE ITS vs INPUT FREQUENY -8 75 7 THD (dc) -7-6 -5 V DD = V + = 5V V REF + = 4.68V T = 25 o. =INTERNL. = 75kHz. = 1MHz SNR (dc) 65 6 55 5 V DD = V + = 5V V REF + = 4.68V T = 25 o. = INTERNL. = 75kHz. = 1MHz.1 1 1 1 INPUT FREQUENY (khz).1 1 1 1 INPUT FREQUENY (khz) FIGURE 16. TOTL HRMONI DISTORTION vs INPUT FREQUENY FIGURE 17. SIGNL NOISE RTIO vs INPUT FREQUENY 6-1796
TLE 1. PIN DESRIPTIONS PIN NO. NME DESRIPTION 1 Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. 2 D it (Least Significant it, LS). 3 D1 it 1. 4 D2 it 2. 5 D3 it 3. 6 D4 it 4. 7 D5 it 5. 8 D6 it 6. 9 D7 it 7. 1 D8 it 8. 11 D9 it 9. 12 V SS Digital Ground (V). 13 D1 it 1. 14 D11 it 11 (Most Significant it, MS). 15 OEM Three-State Enable for D4-D11. ctive low input. 16 V - nalog Ground, (V). 17 V + nalog Positive Supply. (+5V) (See text.) 18 nalog Input. 19 V REF + Reference Voltage Positive Input, sets 495 code end of input range. 2 V REF - Reference Voltage Negative Input, sets code end of input range. 21 Start onversion Input ctive Low, recognized after end of clock period 15. During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto-balanced at the capacitor common node. During the fourth period, all capacitors are disconnected from the input; the one representing the MS (D11) is connected to the V REF + terminal; and the remaining capacitors to V REF -. The capacitor-common node, after the charges balance out, will indicate whether the input was above 1 / 2 of (V REF + - V REF -). t the end of the fourth period, the comparator output is stored and the MS capacitor is either left connected to V REF + (if the comparator was high) or returned to V REF -. This allows the next comparison to be at either 3 / 4 or 1 / 4 of (V REF + - V REF -). t the end of periods 5 through 14, capacitors representing D1 through D1 are tested, the result stored, and each capacitor either left at V REF + or at V REF -. t the end of the 15th period, when the LS (D) capacitor is tested, (D) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data-ready output goes active. The conversion cycle is now complete. nalog Input The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5µ and 2pF. t the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period as shown in Figure 18. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. 22 Input or Output. onversion functions are synchronized to positive going edge. (See text.) 23 OEL Three-State Enable for D D3. ctive Low Input. 24 V DD Digital Positive Supply (+5V). I IN 2m 1m m Theory of Operation 5V is a MOS 12-it nalog-to-digital onverter that uses capacitor-charge balancing to successively approximate the analog input. binarily weighted capacitor network forms the /D heart of the device. See the block diagram for the. The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, V REF + or V REF -. V 5V V 2ns/DIV. ONDITIONS: V DD = V + = 5.V, V REF + = 4.68V, = 4.68V, = 75kHz, T = 25 o FIGURE 18. TYPIL NLOG INPUT URRENT 6-1797
s long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. The analog input is tracked for 3 clock cycles. With an external clock of 75kHz the track period is 4µs. simplified analog input model is presented in Figure 19. During tracking, the /D input ( ) typically appears as a 38pF capacitor being charged through a 42Ω internal switch resistance. The time constant is 16ns. To charge this capacitor from an external zero Ω source to.5 LS (1/8192), the charging time must be at least 9 time constants or 1.4µs. The maximum source impedance (R SOURE Max) for a 4µs acquisition time settling to within.5ls is 75Ω. If the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated. Reference Input RSW 42Ω R SOURE R SOURE(MX) = ------------------------------------------------------------- t Q SMPLE In[ 2 N+ 1) R SW ] SMPLE 38pF The reference input V REF + should be driven from a low impedance source and be well decoupled. s shown in Figure 2, current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the charge-balancing capacitors are switched between V REF - and V REF + (clock periods 5-14). These current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. Therefore V REF + and V REF - should be well bypassed. Reference input V REF - is normally connected directly to the analog ground plane. If V REF - is biased for nulling the converters offset it must be stable during the conversion cycle. I REF+ FIGURE 19. NLOG INPUT MODEL IN TRK MODE 2m 1m m 5V V 5V V 2µs/DIV. ONDITIONS: V DD = V + = 5.V, V REF + = 4.68V, = 2.3V, = 75kHz, T = 25 o FIGURE 2. TYPIL REFERENE INPUT URRENT The is specified with a 4.68V reference, however, it will operate with a reference down to 3V having a slight degradation in performance. typical graph of accuracy vs reference voltage is presented. Full Scale and Offset djustment In many applications the accuracy of the would be sufficient without any adjustments. In applications where accuracy is of utmost importance full scale and offset errors may be adjusted to zero. The V REF + and V REF - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. In a typical system the V REF - might be returned to a clean ground, and the offset adjustment done on an input amplifier. V REF + would then be adjusted to null out the full scale error. When this is not possible, the V REF - input can be adjusted to null the offset error, however, V REF - must be well decoupled. Full scale and offset error can also be adjusted to zero in the signal conditioning amplifier driving the analog input ( ). ontrol Signal The may be synchronized from an external source by using the (Start onversion) input to initiate conversion, or if is tied low, may be allowed to free run. Each conversion cycle takes 15 clock periods. The input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. fter the start of the next period 1 (specified by t D data), the output is updated. The (Data Ready) status output goes high (specified by t D1 ) after the start of clock period 1, and returns low (specified by t D2 ) after the start of clock period 2. The 12 data bits are available in parallel on three-state bus driver outputs. When low, the OEM input enables the most significant byte (D4 through D11) while the OEL input enables the four least significant bits (D - D3). t EN and t DIS specify the output enable and disable times. If the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. When input is used to initiate conversions, operation is slightly different depending on whether an internal or external clock is used. Figure 3 illustrates operation with an internal clock. If the signal is removed (at least t R ) before clock period 1, and is not reapplied during that period, the clock will shut off after entering period 2. The input will continue to track and the output will remain high during this time. low signal applied to (at least t W wide) can now initiate a new conversion. The signal (after a delay of (t D )) causes the clock to restart. Depending on how long the clock was shut off, the low portion of clock period 2 may be longer than during the remaining cycles. 6-1798
The input will continue to track until the end of period 3, the same as when free running. Figure 2 illustrates the same operation as above but with an external clock. If is removed (at least t R ) before clock period 2, a low signal applied to will drop the flag as before, and with the first positive-going clock edge that meets the (t SU ) setup time, the converter will continue with clock period 3. lock The can operate either from its internal clock or from one externally supplied. The pin functions either as the clock output or input. ll converter functions are synchronized with the rising edge of the clock signal. Figure 21 shows the configuration of the internal clock. The clock output drive is low power: if used as an output, it should not have more than 1 MOS gate load applied, and stray wiring capacitance should be kept to a minimum. The internal clock will shut down if the /D is not restarted after a conversion. The clock could also be shut down with an open collector driver applied to the pin. This should only be done during the sample portion (the first three clock periods) of a conversion cycle, and might be useful for using the device as a digital sample and hold. If an external clock is supplied to the pin, it must have sufficient drive to overcome the internal clock source. The external clock can be shut off, but again, only during the sample portion of a conversion cycle. t other times, it must be above the minium frequency shown in the specifications. In the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. This might cause an internal charge-pump voltage to decay. If the internal or external clock was shut off during the conversion time (clock cycles 4 through 15) of the /D, the output might be invalid due to balancing capacitor droop. n external clock must also meet the minimum t LOW and t HIGH times shown in the specifications. violation may cause an internal miscount and invalidate the results. Except for V +, which is a substrate connection to V DD, all pins have protection diodes connected to V DD and V SS. Input transients above V DD or below V SS will get steered to the digital supplies. The V + and V - terminals supply the charge-balancing comparator only. ecause the comparator is autobalanced between conversions, it has good low-frequency supply rejection. It does not reject well at high frequencies however; V - should be returned to a clean analog ground and V + should be R decoupled from the digital supply as shown in Figure 22. There is approximately 5Ω of substrate impedance between V DD and V +. This can be used, for example, as part of a low-pass R filter to attenuate switching supply noise. 1µF capacitor from V + to ground would attenuate 3kHz noise by approximately 4d. Note that back-to-back diodes should be placed from V DD to V + to handle supply to capacitor turn-on or turn-off current spikes. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the /D. low distortion sine wave is applied to the input of the /D converter. The input is sampled by the /D and its output stored in RM. The data is than transformed into the frequency domain with a 496 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling frequency. The noise is the RMS sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.2N + 1.76) d. For an ideal 12-bit converter the SNR is 74d. Differential and integral linearity errors will degrade SNR. SNR = 1 Log Sinewave Signal Power Total Noise Power OPTIONL EXTERNL LOK 1kΩ INTERNL ENLE LOK 18pF Signal-To-Noise + Distortion Ratio SIND is the measured RMS signal to RMS sum of noise plus harmonic power and is expressed by the following: SIND = 1 Log Sinewave Signal Power Noise + Harmonic Power (2nd - 6th) FIGURE 21. INTERNL LOK IRUITRY Power Supplies and Grounding V DD and V SS are the digital supply pins: they power all internal logic and the output drivers. ecause the output drivers can cause fast current spikes in the V DD and V SS lines, V SS should have a low impedance path to digital ground and V DD should be well bypassed. Effective Number of its The effective number of bits (ENO) is derived from the SIND data; ENO = SIND - 1.76 6.2 6-1799
Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. Total Harmonic Power (2nd - 6th Harmonic) THD = 1 Log Sinewave Signal Power SFDR = 1 Log Sinewave Signal Power Highest Spurious Signal Power TLE 2. ODE TLE ODE DESRIPTION INPUT VOLTGE V REF+ = 4.68V V REF- =.V (V) DEIML OUNT INRY OUTPUT ODE MS LS D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Full Scale (FS) 4.669 495 1 1 1 1 1 1 1 1 1 1 1 1 FS - 1 LS 4.658 494 1 1 1 1 1 1 1 1 1 1 1 3 /4 FS 3.456 372 1 1 1 /2 FS 2.34 248 1 1 /4 FS 1.152 124 1 1 LS.1125 1 1 Zero The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage. +5V.1µF 4.7µF 1µF.1µF.1µF V + V DD V REF 4.7µF.1µF.1µF V REF+ D11. D OUTPUT DT OEM NLOG INPUT OEL 75kHz LOK V REF- V - V SS FIGURE 22. GROUND ND SUPPLY DEOUPLING 6-18
Die haracteristics DIE DIMENSIONS: 32µm x 394µm METLLIZTION: Type: lsi Thickness: 11kÅ ±1kÅ PSSIVTION: Type: PSG Thickness: 13kÅ ±2.5kÅ WORST SE URRENT DENSITY: 1.84 x 1 5 /cm 2 Metallization Mask Layout D1 D (LS) V DD OEL D2 D3 V REF - D4 D5 D6 V REF + D7 D8 V + V - D9 V SS D1 D11 (MS) OEM 6-181