3A, 30, 340KHz ynchronous tep-down Converter DECRIPTION The is a synchronous current mode buck regulator capable o driving 3A continuous load current with excellent line and load regulation. The can operate with an input range 4.5 to 30 and the output can be externally set rom 0.925 to 20 with a resistor divider. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. In shutdown mode the regulator draws 1µA o supply current. Programmable sot-start minimizes the inrush supply current and the output overshoot at initial startup. Automatic pulse skipping mode operation increase eiciency at light loads. The require a minimum number o external components. Typical Application Circuit FEATURE 3A Output Current Automatic Pulse kipping Mode at Light Load 35 Input urge Protection Integrated 160mΩ/110mΩ DMO witches 4.5 to 30 Input Operating Range Output Adjustable rom 0.925 to 20 Up to 95% Eiciency 1µA hutdown Current Fixed 340KHz Frequency Programmable ot-tart Thermal hutdown and Overcurrent Protection Input upply Overvoltage and Undervoltage Lockout 230ns Minimum On Time Available in OP-8 (EP) Package RoH Compliant and 100% Lead(Pb)-Free Halogen-Free APPLICATION Distributed Power ystems Networking ystems PC Monitors Portable Electronics 1 Figure 1. 12 to 3.3/5 Application Circuit
Typical Application Circuit (continued) Pin Conigurations Package Type Figure2. 24 to 3.3/5 Application Circuit Pin Conigurations OP-8 (EP) Pin Description P P NAME DECRIPTION 1 B 2 2 High-ide Gate Drive Boost Input. B supplies the drive or the high-side N-Channel DMO switch. Connect a 0.01µF or greater capacitor rom W to B to power the high side switch. Input upply Pin. supplies the power to the IC, as well as the step-down converter switches. Drive with a 4.5 to 30 power source. Bypass to GND with a suitably large capacitor to minimize input ripple to the IC. ee Input Capacitor ection o the applications notes. 3 W Power witching Output. Connect the output LC ilter rom W to the output load. 4 9 (Exposed Pad) GND 5 FB 6 COMP 7 EN 8 Ground. GND pin should be connected to the exposed thermal pad or proper operation. This power thermal pad should be connected to PCB ground plane using multiple vias or good thermal perormance. Output Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage divider connected to it rom the output voltage. The eedback threshold is 0.925. ee etting the Output oltage. Loop compensation Input. Connect a series RC network rom COMP to GND to compensate the regulation control loop. ee Compensation. Enable Input. EN is a logic input that controls the regulator on or o. Drive EN high to turn on the regulator; low to turn it o. Don t leave EN pin loating. Directly connect EN to (or through a resistance) or automatic startup. ot-tart Control Input. Connect an external capacitor to program the sot-start. I unused, leave it open, which means internal sot-start unction.
Ordering Inormation Order Number Package Type Marking Operating Temperature Range DIR1 OP-8 (EP) xxxxx 3484A -40 C to +85 C Lead Free Code 1: Lead Free, Halogen-Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry tandard Package Type D: OP Block Diagram Figure 3.Functional Block Diagram 3
Absolute Maximum Ratings (1) 4 upply oltage ( ) -------------------------------------------------------- -0.3 to +35 Enable oltage ( EN ) ------------------------------------------------------ -0.3 to +35 witch oltages ( W ) ------------------------------------------------------ -1 to +0.3 Boot oltage ( B ) -------------------------------------------------- W -0.3 to W +6 All Other Pins ---------------------------------------------------------------------- -0.3 to +6 Junction Temperature -------------------------------------------------------------------- 150 C Lead Temperature -------------------------------------------------------------- 260 C torage Temperature -------------------------------------------------------- -65 C to +150 C Output oltage ----------------------------------------------------------- 0.925 to 20 Thermal Resistance θ JA (OP-8_EP) ------------------------------------------------------------ 60 C /W Thermal Resistance θ JC (OP-8_EP) ------------------------------------------------------------ 20 C /W Maximum Power Dissipation (P D ) ------------------------------------------------------- 2.083W Recommend Operating Conditions (2) Input oltage --------------------------------------------------------------------- 4.5 to 30 Ambient Operating Temp ----------------------------------------------------- -40 C to +85 C Note(1):tress beyond those listed under Absolute Maximum Ratings may damage the device. Note(2):The device is not guaranteed to unction outside the recommended operating conditions. Electrical Characteristics The denote speciications which apply over the ull operating temperature range, otherwise speciication are 12, T A 25 C unless otherwise speciied. Parameter Conditions Min Typ Max. Unit hutdown upply Current EN 0 1 5 µa upply Current FB 1 0.45 0.9 ma Feedback oltage 4.5 30 0.907 0.925 0.943 0.897 0.925 0.953 Error Ampliier oltage Gain 360 / Error Ampliier Transconductance I C ±10µA 800 µa/ High-ide witch On-Resistance 160 mω Low-ide witch On-Resistance 110 mω High-ide witch Leakage Current EN 0, W 0 5 µa Upper witch Current Limit Minimum Duty Cycle 3.8 5.5 A Lower witch Current Limit From Drain to ource 0 A COMP to Current ense Transconductance 7.5 A/ Oscillation Frequency 300 340 380 KHz hort Circuit Oscillation Frequency FB 0 110 KHz Maximum Duty Cycle FB 0.7 90 % Minimum On Time 230 ns EN Disable Threshold 0.36 1.5 2.0 EN Lockout Threshold EN Rising 2.3 2.5 2.8 2 2.5 3 EN Lockout Threshold Hysteresis 210 m Input Under oltage Lockout Threshold Rising 3.8 4.1 4.4 Input Over oltage Lockout Threshold Rising 35 Input Over oltage Lockout Threshold Hysteresis 2 ot-tart Charge Current 0 6 µa Thermal hutdown 160 C
Typical Operating Characteristics (ee Figure1, C1 10µF, C222µF 2, L10µH, T A +25 C) 5
Typical Operating Characteristics (continued) (ee Figure1, C1 10µF, C222µF 2, L10µH, T A +25 C) 6
Typical Operating Characteristics (continued) (ee Figure1, C1 10µF, C222µF 2, L10µH, T A +25 C) 7
Functional Description The regulates input voltages rom 4.5 to 30 down to an output voltage as low as 0.925, and supplies up to 3A o load current. The uses current-mode control to regulate the output voltage. The output voltage is measured at FB through a resistive voltage divider and ampliied through the internal transconductance error ampliier. The voltage at the COMP pin is compared to the switch current (measured internally) to control the output voltage. The converter uses internal N-Channel MOFET switches to step-down the input voltage to the regulated output voltage. ince the high side MOFET requires a gate voltage greater than the input voltage, a boost capacitor connected between W and B is needed to drive the high side gate. The boost capacitor is charged rom the internal 5 rail when W is low. At light loads, the inductor current may reach zero or reverse on each pulse. The bottom DMO is turned o by the current reversal comparator and the switch voltage will ring. This is discontinuous mode operation, and is normal behavior or the switching regulator. At light load, the will automatically skip pulses in pulse skipping mode operation to maintain output regulation and increases eiciency. When the FB pin voltage exceeds 15% o the nominal regulation value o 0.925, the over voltage comparator is tripped and orcing the high-side switch o. Application Inormation etting the Output oltage The output voltage is set using a resistive voltage divider connected rom the output voltage to FB. The voltage divider divides the output voltage down to the eedback voltage by the ratio: R2 FB R1 + R2 Thus the output voltage is: R1 + R2 0.925 R2 R2 can be as high as 100kΩ, but a typical value is 10kΩ. Using the typical value or R2, R1 is determined by: R1 10.81 ( 0.925) ( kω) For example, or a 3.3 output voltage, R2 is 10kΩ and R1 is 26.1kΩ. Inductor The inductor is required to supply constant current to the load while being driven by the switched input voltage. A larger value inductor will result in less ripple current that will in turn result in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule or determining inductance is to allow the peak-to-peak ripple current to be approximately 30% o the maximum switch current limit. Also, make sure that the peak inductor current is below the maximum switch current limit. The inductance value can be calculated by: Where is the output voltage, is the input voltage, is the switching requency, and I L is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current, calculated by: I LP L I LOAD Where I LOAD is the load current. The choice o which style inductor to use mainly depends on the price vs. size requirements and any EMI constraints. Optional chottky Diode During the transition between the high-side switch and low-side switch, the body diode o the low-side power MOFET conducts the inductor current. The orward voltage o this body diode may be high and cause eiciency loss. An optional small 1A chottky diode B130 in parallel with low-side switch is recommended to improve overall eiciency when input voltage is higher. Input Capacitor I L + 2 1 1 L The input current to the step-down converter is discontinuous, thereore a capacitor is required to supply the AC current while maintaining the DC input voltage. Use low ER capacitors or the best perormance. Ceramic capacitors are preerred, but tantalum or low-er electrolytic capacitors will also suice. Choose X5R or X7R dielectrics when using ceramic capacitors. ince the input capacitor (C1) absorbs the input switching current, it requires an adequate ripple current rating. The RM current in the input capacitor can be estimated by: I C1 The worst-case condition occurs at 2, where I C1 I LOAD /2. For simpliication, use an input capacitor with a RM current rating greater than hal o the maximum load current. I 1 LOAD 8
The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1µF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide suicient charge to prevent excessive voltage ripple at input. The input voltage ripple or low ER capacitors can be estimated by: I LOAD C1 Where C1 is the input capacitance value. For simpliication, choose the input capacitor whose RM current rating greater than hal o the maximum load current. Output Capacitor 1 The output capacitor (C2) is required to maintain the DC output voltage. Ceramic, tantalum, or low ER electrolytic capacitors are recommended. Low ER capacitors are preerred to keep the output voltage ripple low. The output voltage ripple can be estimated by: L 1 1 R + ER 8 C2 Where C2 is the output capacitance value and R ER is the equivalent series resistance (ER) value o the output capacitor. When using ceramic capacitors, the impedance at the switching requency is dominated by the capacitance which is the main cause or the output voltage ripple. For simpliication, the output voltage ripple can be estimated by: 1 L C2 When using tantalum or electrolytic capacitors, the ER dominates the impedance at the switching requency. For simpliication, the output ripple can be approximated to: 8 2 1 L The characteristics o the output capacitor also aect the stability o the regulation system. The can be optimized or a wide range o capacitance and ER values. 9 R ER Compensation Components employs current mode control or easy compensation and ast transient response. The system stability and transient response are controlled through the COMP pin. COMP is the output o the internal transconductance error ampliier. A series capacitorresistor combination sets a pole-zero combination to govern the characteristics o the control system. The DC gain o the voltage eedback loop is given by: A DC R LOAD G C A EA FB Where FB is the eedback voltage (0.925), A EA is the error ampliier voltage gain, G C is the current sense transconductance and R LOAD is the load resistor value. The system has two poles o importance. One is due to the compensation capacitor (C3) and the output resistor o the error ampliier, and the other is due to the output capacitor and the load resistor. These poles are located at: P1 P2 G EA 2π C3 A EA 1 2π C2 R LOAD Where G EA is the error ampliier transconductance. The system has one zero o importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: Z1 1 2π C3 R3 The system may have another zero o importance, i the output capacitor has a large capacitance and/or a high ER value. The zero, due to the ER and capacitance o the output capacitor, is located at: ER 1 2π C2 R ER In this case, a third pole set by the compensation capacitor (C4) and the compensation resistor (R3) is used to compensate the eect o the ER zero on the loop gain. This pole is located at: P3 1 2π C4 R3 The goal o compensation design is to shape the converter transer unction to get a desired loop gain. The system crossover requency where the eedback
loop has the unity gain is important. Lower crossover requencies result in slower line and load transient responses, while higher crossover requencies could cause the system instability. A good standard is to set the crossover requency below one-tenth o the switching requency. To optimize the compensation components, the ollowing procedure can be used: 1. Choose the compensation resistor (R3) to set the desired crossover requency. Determine R3 by the ollowing equation: 2π C2 R3 C G EA G C FB 2π C2 0.1 < G EA G C FB Where C is the desired crossover requency, which is typically below one tenth o the switching requency. 2. Choose the compensation capacitor (C3) to achieve the desired phase margin. For applications with typical inductor values, setting the compensation zero ( Z1 ) below one-orth o the crossover requency provides suicient phase margin. Determine C3 by the ollowing equation: 4 C3 > 2π R3 C Where R3 is the compensation resistor. 3. Determine i the second compensation capacitor (C4) is required. It is required i the ER zero o the output capacitor is located at less than hal o the switching requency, or the ollowing relationship is valid: 1 < 2π C2 R 2 ER I this is the case, then add the second compensation capacitor (C4) to set the pole P3 at the location o the ER zero. Determine C4 by the equation: To simpliy design eorts using the,the typical design or common application are listed in Table1. External Bootstrap Diode It is recommended that an external bootstrap diode be added when the system has a 5 ixed input or the power supply generates a 5 output. This helps improve the eiciency o the regulator. Figure 4. Add Optional External Bootstrap Diode to Enhance This diode is also recommended or high duty cycle operation ( when C2 R C4 ER R3 voltage ( >12) applications. >65% ) and high output Table1. External Components or Typical Designs in() out() L1(µH) C2(µF) R1(KΩ) R2(KΩ) R3(KΩ) C3(nF) C4(pF) 5 1.0 3.3 22*2 0.820 10 6.8 3.9 open 5 1.2 4.7 22*2 3.0 10 6.8 3.9 open 5 3.3 10 22*2 26.1 10 6.8 3.9 open 12 1.0 3.3 22*2 0.820 10 2.2 10 open 12 1.2 4.7 22*2 3.0 10 2.2 10 open 12 3.3 10 22*2 26.1 10 6.8 3.9 open 12 5.0 10 22*2 44.2 10 6.8 3.9 open 24 3.3 10 22*2 26.1 10 6.8 3.9 open 24 5.0 10 22*2 44.2 10 6.8 3.9 open 10
Packaging Inormation OP-8 (EP) YMBOL MILLIMETER CHE M. MAX. M. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 D 4.90 0.193 E1 3.90 0.153 D1 2.97 0.117 E2 2.18 0.086 E 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 b 0.31 0.51 0.012 0.020 e 1.27 0.050 11