Supporting Information High throughput ultra-long (20cm) nanowire fabrication using a wafer-scale nanograting template Jeongho Yeon 1, Young Jae Lee 2, Dong Eun Yoo 3, Kyoung Jong Yoo 2, Jin Su Kim 2, Jun Lee 2, Jeong Oen Lee 1, Seon-Jin Choi 1, Gun-Wook Yoon 1, Dong Wook Lee 3, Gi Seong Lee 3, Hae Chul Hwang 3 and Jun-Bo Yoon 1 * 1 Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon, 305-701, Republic of Korea. 2 LG Innotek Components & Materials R&D Center, 55 Hanyang Daehak-ro, Ansan-si, Gyeonggi-do, 426-791, Republic of Korea. 3 Korea National NanoFab Center (NNFC), 291 Daehak-ro, Yuseong-gu, Daejeon, 305-701, Republic of Korea. *Correspondence to: jbyoon@ee.kaist.ac.kr The first two authors contributed equally to this work. Materials and Methods: Master template fabrication: Two undoped poly-si thin films vertically separated by tetraethylorthosilicate (TEOS) SiO 2 and SiN layers were pre-deposited on an 8-inch Si wafer using a low pressure chemical vapor deposition (LPCVD) system (Centrotherm Corporation, E1200). An initial pattern with a period of 400 nm was formed using a krypton fluoride (KrF) 1
step and repeat scanning system (PAS 5500/700D, ASML Corporation). A reticle containing lines and spaces with widths of 600 nm and 1 µm, respectively, was used as a photomask to form an initial pattern of 400 nm-pitch lines. Inductively coupled plasma reactive ion etching systems (Lam Research Corporation, Ltd., TCP-9400DFM), were used to etch the structure s materials in the dry phase. A Cl 2, HBr and O 2 based gas mixture was used to etch poly-si. For SiN and SiO 2, we used C 4 F 8 /Ar/O 2 and CF 4 /CH 2 F 2 /He based gas mixtures as the reactants for etching, respectively. The operating power and etching times were precisely adjusted for accurate etching stops. Pattern transfer for disposable template: A customized low-viscosity UV curable monomer was used as the imprinting resin. After dropping the imprinting resin on the Si nanograting mold, a polyethylene terephthalate (PET) film was used to cover it and was followed by a rolling-over process. The imprinting resin was cured under UV exposure (wavelength of 365 nm) and manually peeled off from the mold. Fabrication of ordered nanowire array: To fabricate regularly ordered nanowire arrays, we deposited the target materials on the plastic disposable templates by thermal evaporation or sputtering processes. For separation of the nanowires, we performed glancing angle deposition, in which the target materials are deposited at an oblique angle, so that the nanowire arrays are naturally separated from each other. For each single metal, dielectric or ferroelectric material, the deposition thickness was set at 400 Å. Extraction of random nanowire network: Aluminium, copper, and gold thin films were deposited on the plastic disposable templates by conventional thermal evaporation or sputtering systems. The thickness of the aluminium sacrificial layer was 200 Å. Gold and Cu were deposited with a target thickness of 400 Å. We used a commercial Cu etchant (APS-100, 2
Transene Corporation) and a Au etchant (C&C Tech. Corporation). To prevent rapid etch-out of the nanowire materials, the etchants were diluted with de-ionized (DI) water, at a ratio of 10:1. The nanowires were peeled off the substrate by removing the sacrificial Al layer in 5% sodium hydroxide (NaOH) solutions. SEM characterization: Samples for cross-sectional SEM imaging were cut into pieces with sizes from several millimeters to 1cm. To show the multi-layered structure in the cross-sectional view, the cut samples were lightly etched in a dilute HNO 3 and HF solution for 10 s after covering the top surface with a positive photoresist (AZ1512, Clariant Corporation). The cross-sectional structures were imaged by a field-emission SEM (S-4800, Hitachi Corporation) operating at 5 10 kev. All SEM samples were coated with platinum in a sputtering system (SCD005, Baltec Corporation) with a thickness of 15 nm to avoid charging effects. 3
Supplementary Text: S1. Conventional spacer lithography limits Figure S1 shows the conceptual view of conventional spacer lithography. First, a sacrificial pattern with a pitch that is double the target pitch is formed (Figures S1a S1c). Second, a thin film spacer is deposited on the sacrificial pattern (Figure S1d) by chemical vapour deposition (CVD). In this step, step coverage should be sufficient for the thin film to be grown not only at the top and bottom parts but also at the sidewalls of the sacrificial pattern. Next, the spacer thin film is vertically (anisotropically) etched by a reactive ion etching (RIE) process, so that the spacer sidewall remains (Figure S1e). Following the vertical spacer etching process, the sacrificial pattern is removed, leaving the spacer sidewalls (Figure S1f). After sacrificial pattern removal, the remaining spacer sidewall pattern has a pitch that is half of that of the initial sacrificial pattern. However, as shown in Figure S1f, the cross-section of the spacer is no longer rectangular but is severely distorted. This pattern distortion prevents continuous reduction, and limits multiple pattern downscaling. Figure S1. Process sequence for pattern pitch reduction using conventional spacer lithography. (a) Wafer preparation. (b) Sacrificial layer deposition. (c) Sacrificial layer patterning. (d) Spacer deposition. (e) Anisotropic etch of the spacer, leaving the sidewall behind. (f) Sacrificial layer removal. 4
S2. Modified spacer lithography Figure S2 shows the basic concept of the proposed pattern pitch reduction method. First, multiple polycrystalline Si (poly-si) layers were vertically stacked by CVD on an 8-inch Si wafer, being isolated by alternately deposited silicon dioxide (SiO 2 ) and silicon nitride (SiN) films. These dielectric films function as a protection layer during the pattern reduction process. After patterning of the top poly-si layer, SiO 2 spacer material is deposited by CVD on the pattern, with the required step coverage (Figures S2a and S2b). Following the spacer deposition, an RIE process is conducted along the vertical direction to etch out the top SiO 2 and uncover the top part of the poly-si pattern, leaving the spacer sidewall (Figure S2c). We then remove the poly-si pattern, leaving the SiO 2 sidewall behind (Figure S2d). During the poly-si removal process, the dielectric film protects the underlying poly-si film. As noted above, the sidewall pattern at this point is severely distorted. To recover the distorted sidewall pattern shape, the sidewall pattern was then transferred to another underlying poly- Si layer by another vertical dry etching process (Figures S2e and S2f). After the spacer sidewall is removed, the scaled pattern shape is fully recovered (Figure S2g). Because the multiple layers remain under the scaled patterns, identical pattern scaling processes can be conducted repetitively, thus scaling down the pattern pitch further. Figures S2h-S2n shows a repetition of the pattern reduction process to finally obtain a 1/4-scaled grating from the initial pattern shown in Figure S2a. 5
Figure S2. Overall process sequence of repetitive pattern pitch reduction and recovery technology. (a) Wafer preparation and initial layer patterning. (b) Spacer deposition. (c) Anisotropic etch of the spacer. (d) Sacrificial pattern removal. (e-f) Pattern transfer to the underlying layer. (g) Pattern shape recovery by spacer mask removal. (h-n), Second pattern reduction process through identical process to that shown in (a-g). 6
S3. Fabrication of a disposable template Figure S3 illustrates the process for fabrication of the disposable template from the Si master template. Figure S3. Overall pattern transfer process for fabrication of plastic disposable templates from Si nanograting master template. (a) Starting nanograting master template. (b) UV-curable pre-polymer resin is dropped on the master template. (c) Covering with a PET substrate and rolling. (d) Pre-curing of pre-polymer resin under moderate UV dose. (e) Removal of pre-cured pattern from the master template. (f) Hard-curing of patterned resin under strong UV dose. 7
S4. Shadowing effect in material deposition During nanowire material deposition on the plastic nanograting template, the pattern valleys were shadowed by the pattern peaks, as shown in Figure S4. When the target material is first deposited on a patterned substrate at an incident angle, parts of the pattern valleys are shadowed by the adjacent pattern peaks (Figures S4a and S4b). This shadow effect causes the deposited materials to be much thicker at the pattern peaks than at the valleys (Figure S4c). Because the nanowire material in the valleys is much thinner than that at the peaks, deposited thin films in the valleys are more easily etched during the subsequent slight etching in an aqueous solution, leaving the separated nanowires at the pattern peaks. Figure S4. Conceptual illustration of the deposition mechanism. (a) Pattern valleys are shadowed by the pattern peaks, making it more difficult to deposit in the valleys. (b) Deposited material is piled up, except in the shadowed region. (c) Shadowed region gets wider as the deposition thickness increases. 8
S5. Random nanowire network extraction By depositing additional sacrificial layers prior to deposition of the target nanowire materials, the nanowires can be easily extracted (detached) from the substrate, forming random nanowire networks. In this study, we used a 200 Å Al thin film as the sacrificial material. For example, to extract Cu nanowires from the substrate, we sequentially deposited Al and Cu thin films with thicknesses of 200 Å and 400 Å, respectively. After dipping the sample into a dilute Cu etching solution for a short time, the underlying Al layer is exposed in the pattern valleys. The separated top Cu nanowires can now be detached from the nanograting substrate by removal of the underlying Al layer in an etching solution. Schematic illustrations of the nanowire extraction process are shown in Figure S5a to S5d. Figure S5. Nanowire network extraction from nanograting template. (a) Sacrificial layer deposition on the plastic disposable template. (b) Target material deposition on the sacrificial layer. (c) Nanowire separation and diameter adjustment through wet etching process. (d) Nanowire extraction by releasing the sacrificial layer. 9
The nanowire network thickness can be controlled via the wet etching time. Figure S6a shows the average diameter of the Cu nanowire network versus the etching time of the Cu thin film. The graph shows a clear trend where the average nanowire diameter decreases as the Cu etching time increases. We achieved a nanowire array with a diameter as low as 50 nm by this wet etching method. SEM images of the Cu nanowire networks extracted after different wet etching times for the Cu thin films are shown in Figures S6b and S6c. We can see that the diameter of the nanowires decreases as the etching time increases. Figure S6. Control of the average diameter of the Cu nanowire network. (a) Trend of the average diameter of the Cu nanowire array relative to the Cu etching time. (b) and (c) SEM photographs of the Cu nanowire network with wet etching times of 10 s and 30 s, respectively. All scale bars indicate 500 nm. 10
S6. Regularly aligned nanowire releasing The highly ordered nanowire array on disposable template can be released with its perfect array structure maintained. We treated the polymer disposable template, on which highly aligned Al nanowire array is deposited, under oxygen plasma (200W, 30s) to etch out the polymer grating and release the nanowire array on it. Through the oxygen plasma treatment, the polymer grating template under the highly ordered nanowire array was selectively attacked and the anchoring force becomes weak. Because of the weakened anchoring force of the underlying polymer grating template, the regular nanowire array becomes easy to be peeled off from the substrate. Figure S7 shows the schematic illustration of the nanowire releasing process. Figure S7. Schematic illustration of the aligned nanowire transferring. (a) Ordered nanowire deposition on the plastic disposable template. (b) Oxygen plasma treatment for etching the underlying grating pattern. (c) Detaching the aligned nanowire array. To verify the feasibility of nanowire peeling off process, we detached the Al nanowire array by sticky tape, as shown in Figure S8a to S8c. From SEM observation, we could see the Al nanowire array transfer to the sticky tape with its perfect alignment maintained, as shown in Figure S9a and S9b. Although some defect area are shown in Figure S9a, we could know that the nanowire can be released with maintained array structure over several centimeter of area. 11
Figure S8. Optical view of aligned nanowire transferring process. (a) Plasma treated nanowire array on a plastic disposable template. (b) Nanowire being peeled off from the disposable template. (c) Peeled-off nanowire array with its alignment maintained. Figure S9. SEM photographs of the peeled-off Al nanowire array. (a) Low magnification and (b) High magnification. Scale bars in (a) and (b) indicate 1µm and 500nm, respectively. Another method can be used to release nanowire array with perfect alignment as follows. Using a poor adhesion force between certain pair of material, nanowire array pattern can be easily peeled off from the substrate. (C. H. Lee et al. Nano Lett. 11, 3435-3439) As an example, we deposited Au nanowire array on the silicon master template with a native SiO 2 interstitial layer. Because of the poor adhesion between Au and SiO 2, the top Au nanowire array was easily trasnferred to the target sticky substrate. Figures S10 and S11 show the process schematic and SEM image of the Au 12
nanowire transferred onto a sticky tape, respectively. Although some defects and fails of transferred nanowires are shown in the Figure S11a, we could see that the Au nanowires were generally well transferred with their 100-nm pitch and high alignment maintained. Figure S10. Schematic illustration of the aligned nanowire transferring from the master template. (a) Si grating master template with native SiO 2 on it. (b) Au nanowire deposition. (c) Detaching the aligned nanowire array. Figure S11. SEM images of Au nanowires array transferred from the Si master grating template to a sticky tape. (a) Low magnification and (b) High magnification. Scale bars in (a) and (b) indicate 2µm and 500nm, respectively. 13